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arm: socfpga: soc64: Add SDM triggered warm reset bit mask

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Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Chee Hong Ang 2020-08-05 21:15:56 +08:00 committed by Ley Foon Tan
parent 289ebe077a
commit d7a1ff40d6
1 changed files with 9 additions and 2 deletions
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11
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
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@ -21,8 +21,15 @@ void socfpga_bridges_reset(int enable);
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
/* Watchdogs and MPU warm reset mask */
#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
/* SDM, Watchdogs and MPU warm reset mask */
#define RSTMGR_STAT_SDMWARMRST BIT(1)
#define RSTMGR_STAT_MPU0RST_BITPOS 8
#define RSTMGR_STAT_L4WD0RST_BITPOS 16
#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \
GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
RSTMGR_STAT_MPU0RST_BITPOS) | \
GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
RSTMGR_STAT_L4WD0RST_BITPOS))
/*
* SocFPGA Stratix10 reset IDs, bank mapping is as follows: