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https://github.com/brain-hackers/u-boot-brain
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net: emaclite: Add MDIO support to driver
Add MDIO support before move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
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8ce6947831
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@ -10,9 +10,13 @@
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#include <common.h>
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#include <net.h>
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#include <config.h>
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#include <console.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <fdtdec.h>
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#include <asm-generic/errno.h>
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#undef DEBUG
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@ -46,11 +50,36 @@
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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/* MDIO */
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#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
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#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
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#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
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#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
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/* MDIO Address Register Bit Masks */
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#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
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#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
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#define XEL_MDIOADDR_PHYADR_SHIFT 5
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#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
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/* MDIO Write Data Register Bit Masks */
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#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
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/* MDIO Read Data Register Bit Masks */
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#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
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/* MDIO Control Register Bit Masks */
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#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
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#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
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struct xemaclite {
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u32 nexttxbuffertouse; /* Next TX buffer to write to */
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u32 nextrxbuffertouse; /* Next RX buffer to read from */
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u32 txpp; /* TX ping pong buffer */
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u32 rxpp; /* RX ping pong buffer */
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int phyaddr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
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@ -107,11 +136,177 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
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*to32ptr++ = alignbuffer;
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
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bool set, unsigned int timeout)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout)
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break;
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if (ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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func, reg, mask, set);
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return -ETIMEDOUT;
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}
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static int mdio_wait(struct eth_device *dev)
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{
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return wait_for_bit(__func__,
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(u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET),
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XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
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}
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static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
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u16 *data)
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{
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if (mdio_wait(dev))
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return 1;
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u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET);
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out_be32(dev->iobase + XEL_MDIOADDR_OFFSET,
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XEL_MDIOADDR_OP_MASK |
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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if (mdio_wait(dev))
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return 1;
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/* Read data */
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*data = in_be32(dev->iobase + XEL_MDIORD_OFFSET);
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return 0;
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}
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static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
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u16 data)
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{
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if (mdio_wait(dev))
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return 1;
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/*
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* Write the PHY address, register number and clear the OP bit in the
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* MDIO Address register and then write the value into the MDIO Write
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* Data register. Finally, set the Status bit in the MDIO Control
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* register to start a MDIO write transaction.
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*/
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u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET);
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out_be32(dev->iobase + XEL_MDIOADDR_OFFSET,
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~XEL_MDIOADDR_OP_MASK &
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data);
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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if (mdio_wait(dev))
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return 1;
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return 0;
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}
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#endif
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static void emaclite_halt(struct eth_device *dev)
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{
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debug("eth_halt\n");
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}
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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static int setup_phy(struct eth_device *dev)
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{
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int i;
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u16 phyreg;
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struct xemaclite *emaclite = dev->priv;
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struct phy_device *phydev;
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u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full;
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if (emaclite->phyaddr != -1) {
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phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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debug("Default phy address %d is valid\n",
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emaclite->phyaddr);
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} else {
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debug("PHY address is not setup correctly %d\n",
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emaclite->phyaddr);
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emaclite->phyaddr = -1;
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}
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}
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if (emaclite->phyaddr == -1) {
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/* detect the PHY address */
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for (i = 31; i >= 0; i--) {
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phyread(dev, i, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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emaclite->phyaddr = i;
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debug("emaclite: Found valid phy address, %d\n",
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i);
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break;
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}
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}
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}
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/* interface - look at tsec */
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phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
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PHY_INTERFACE_MODE_MII);
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/*
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* Phy can support 1000baseT but device NOT that's why phydev->supported
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* must be setup for 1000baseT. phydev->advertising setups what speeds
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* will be used for autonegotiation where 1000baseT must be disabled.
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*/
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phydev->supported = supported | SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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phydev->advertising = supported;
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emaclite->phydev = phydev;
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phy_config(phydev);
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phy_startup(phydev);
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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/* Do not setup anything */
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return 1;
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}
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#endif
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static int emaclite_init(struct eth_device *dev, bd_t *bis)
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{
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struct xemaclite *emaclite = dev->priv;
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@ -156,6 +351,13 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
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out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
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XEL_RSR_RECV_IE_MASK);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK);
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if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) &
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XEL_MDIOCTRL_MDIOEN_MASK)
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if (!setup_phy(dev))
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return -1;
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#endif
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debug("EmacLite Initialization complete\n");
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return 0;
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}
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@ -327,6 +529,28 @@ static int emaclite_recv(struct eth_device *dev)
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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static int emaclite_miiphy_read(const char *devname, uchar addr,
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uchar reg, ushort *val)
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{
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u32 ret;
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struct eth_device *dev = eth_get_dev();
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ret = phyread(dev, addr, reg, val);
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debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
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return ret;
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}
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static int emaclite_miiphy_write(const char *devname, uchar addr,
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uchar reg, ushort val)
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{
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struct eth_device *dev = eth_get_dev();
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debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
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return phywrite(dev, addr, reg, val);
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}
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#endif
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int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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int txpp, int rxpp)
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{
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@ -356,7 +580,21 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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dev->send = emaclite_send;
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dev->recv = emaclite_recv;
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#ifdef CONFIG_PHY_ADDR
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emaclite->phyaddr = CONFIG_PHY_ADDR;
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#else
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emaclite->phyaddr = -1;
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#endif
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
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emaclite->bus = miiphy_get_dev_by_name(dev->name);
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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XEL_MDIOCTRL_MDIOEN_MASK);
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#endif
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return 1;
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}
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