mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
commit
d71be19902
|
|
@ -548,6 +548,7 @@ S: Maintained
|
|||
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
|
||||
F: arch/arm/mach-zynq/
|
||||
F: doc/board/xilinx/
|
||||
F: doc/device-tree-bindings/video/syncoam,seps525.txt
|
||||
F: drivers/clk/clk_zynq.c
|
||||
F: drivers/fpga/zynqpl.c
|
||||
F: drivers/gpio/zynq_gpio.c
|
||||
|
|
@ -589,6 +590,7 @@ F: drivers/spi/zynq_qspi.c
|
|||
F: drivers/spi/zynq_spi.c
|
||||
F: drivers/timer/cadence-ttc.c
|
||||
F: drivers/usb/host/ehci-zynq.c
|
||||
F: drivers/video/seps525.c
|
||||
F: drivers/watchdog/cdns_wdt.c
|
||||
F: include/zynqmppl.h
|
||||
F: include/zynqmp_firmware.h
|
||||
|
|
|
|||
12
Makefile
12
Makefile
|
|
@ -1005,7 +1005,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
|
|||
append = cat $(filter-out $< $(PHONY), $^) >> $@
|
||||
|
||||
quiet_cmd_pad_cat = CAT $@
|
||||
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
|
||||
cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
|
||||
|
||||
quiet_cmd_lzma = LZMA $@
|
||||
cmd_lzma = lzma -c -z -k -9 $< > $@
|
||||
|
|
@ -1312,7 +1312,7 @@ endif
|
|||
shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); }
|
||||
|
||||
quiet_cmd_objcopy_uboot = OBJCOPY $@
|
||||
cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || rm -f $@
|
||||
cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || { rm -f $@; false; }
|
||||
|
||||
u-boot-nodtb.bin: u-boot FORCE
|
||||
$(call if_changed,objcopy_uboot)
|
||||
|
|
@ -1584,12 +1584,12 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
|
|||
ifneq ($(CONFIG_ARCH_SOCFPGA),)
|
||||
quiet_cmd_gensplx4 = GENSPLX4 $@
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||||
cmd_gensplx4 = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
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||||
spl/u-boot-spl.sfp spl/u-boot-spl.sfp > $@ || rm -f $@
|
||||
spl/u-boot-spl.sfp spl/u-boot-spl.sfp > $@ || { rm -f $@; false; }
|
||||
spl/u-boot-splx4.sfp: spl/u-boot-spl.sfp FORCE
|
||||
$(call if_changed,gensplx4)
|
||||
|
||||
quiet_cmd_socboot = SOCBOOT $@
|
||||
cmd_socboot = cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
|
||||
cmd_socboot = cat spl/u-boot-splx4.sfp u-boot.img > $@ || { rm -f $@; false; }
|
||||
u-boot-with-spl.sfp: spl/u-boot-splx4.sfp u-boot.img FORCE
|
||||
$(call if_changed,socboot)
|
||||
|
||||
|
|
@ -1599,12 +1599,12 @@ cmd_gensplpadx4 = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \
|
|||
spl/u-boot-spl.sfp spl/u-boot-spl.pad \
|
||||
spl/u-boot-spl.sfp spl/u-boot-spl.pad \
|
||||
spl/u-boot-spl.sfp spl/u-boot-spl.pad > $@ || \
|
||||
rm -f $@ spl/u-boot-spl.pad
|
||||
{ rm -f $@ spl/u-boot-spl.pad; false; }
|
||||
u-boot-spl-padx4.sfp: spl/u-boot-spl.sfp FORCE
|
||||
$(call if_changed,gensplpadx4)
|
||||
|
||||
quiet_cmd_socnandboot = SOCNANDBOOT $@
|
||||
cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@
|
||||
cmd_socnandboot = cat u-boot-spl-padx4.sfp u-boot.img > $@ || { rm -f $@; false; }
|
||||
u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
|
||||
$(call if_changed,socnandboot)
|
||||
|
||||
|
|
|
|||
7
README
7
README
|
|
@ -1925,13 +1925,6 @@ The following options need to be configured:
|
|||
try longer timeout such as
|
||||
#define CONFIG_NFS_TIMEOUT 10000UL
|
||||
|
||||
- Command Interpreter:
|
||||
CONFIG_SYS_PROMPT_HUSH_PS2
|
||||
|
||||
This defines the secondary prompt string, which is
|
||||
printed when the command interpreter needs more input
|
||||
to complete a command. Usually "> ".
|
||||
|
||||
Note:
|
||||
|
||||
In the current implementation, the local variables
|
||||
|
|
|
|||
14
arch/Kconfig
14
arch/Kconfig
|
|
@ -7,6 +7,17 @@ config HAVE_ARCH_IOREMAP
|
|||
config NEEDS_MANUAL_RELOC
|
||||
bool
|
||||
|
||||
config LINKER_LIST_ALIGN
|
||||
int
|
||||
default 32 if SANDBOX
|
||||
default 8 if ARM64 || X86
|
||||
default 4
|
||||
help
|
||||
Force the each linker list to be aligned to this boundary. This
|
||||
is required if ll_entry_get() is used, since otherwise the linker
|
||||
may add padding into the table, thus breaking it.
|
||||
See linker_lists.rst for full details.
|
||||
|
||||
choice
|
||||
prompt "Architecture select"
|
||||
default SANDBOX
|
||||
|
|
@ -112,6 +123,7 @@ config SANDBOX
|
|||
imply BITREVERSE
|
||||
select BLOBLIST
|
||||
imply CMD_DM
|
||||
imply CMD_EXCEPTION
|
||||
imply CMD_GETTIME
|
||||
imply CMD_HASH
|
||||
imply CMD_IO
|
||||
|
|
@ -146,6 +158,8 @@ config SANDBOX
|
|||
imply ACPI_PMC_SANDBOX
|
||||
imply CMD_PMC
|
||||
imply CMD_CLONE
|
||||
imply SILENT_CONSOLE
|
||||
imply BOOTARGS_SUBST
|
||||
|
||||
config SH
|
||||
bool "SuperH architecture"
|
||||
|
|
|
|||
0
arch/arc/include/asm/spl.h
Normal file
0
arch/arc/include/asm/spl.h
Normal file
|
|
@ -52,7 +52,11 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
|
|||
continue;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DM_ETH
|
||||
priv = dev_get_priv(dev);
|
||||
#else
|
||||
priv = dev->priv;
|
||||
#endif
|
||||
if (priv->flags & TSEC_SGMII)
|
||||
continue;
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#include <asm/system.h>
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
int psci_update_dt(void *fdt)
|
||||
{
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#endif
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/arch-fsl-layerscape/soc.h>
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
#endif
|
||||
#include <asm/arch/speed.h>
|
||||
|
|
@ -81,7 +81,7 @@ void ft_fixup_cpu(void *blob)
|
|||
"device_type", "cpu", 4);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
int node;
|
||||
u32 psci_ver;
|
||||
|
|
@ -383,7 +383,7 @@ static void fdt_fixup_msi(void *blob)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
/* Remove JR node used by SEC firmware */
|
||||
void fdt_fixup_remove_jr(void *blob)
|
||||
{
|
||||
|
|
@ -490,7 +490,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|||
else {
|
||||
ccsr_sec_t __iomem *sec;
|
||||
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
fdt_fixup_remove_jr(blob);
|
||||
fdt_fixup_kaslr(blob);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -192,6 +192,7 @@ ENTRY(lowlevel_init)
|
|||
#endif
|
||||
|
||||
/* Initialize GIC Secure Bank Status */
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
|
||||
branch_if_slave x0, 1f
|
||||
bl get_gic_offset
|
||||
|
|
@ -205,6 +206,7 @@ ENTRY(lowlevel_init)
|
|||
bl gic_init_secure_percpu
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
100:
|
||||
branch_if_master x0, x1, 2f
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#include <asm/arch/immap_lsch2.h>
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
#endif
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@ u32 spl_boot_device(void)
|
|||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
|
||||
/* Define board data structure */
|
||||
static struct bd_info bdata __attribute__ ((section(".data")));
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
|
||||
|
|
@ -74,7 +77,7 @@ void board_init_f(ulong dummy)
|
|||
get_clocks();
|
||||
|
||||
preloader_console_init();
|
||||
spl_set_bd();
|
||||
gd->bd = &bdata;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
ethernet3 = &enetc6;
|
||||
};
|
||||
|
||||
binman {
|
||||
binman: binman {
|
||||
filename = "u-boot.rom";
|
||||
pad-byte = <0xff>;
|
||||
|
||||
|
|
@ -80,21 +80,18 @@
|
|||
conf-1 {
|
||||
description = "fsl-ls1028a-kontron-sl28";
|
||||
firmware = "uboot";
|
||||
loadables = "uboot";
|
||||
fdt = "fdt-1";
|
||||
};
|
||||
|
||||
conf-2 {
|
||||
description = "fsl-ls1028a-kontron-sl28-var3";
|
||||
firmware = "uboot";
|
||||
loadables = "uboot";
|
||||
fdt = "fdt-2";
|
||||
};
|
||||
|
||||
conf-3 {
|
||||
description = "fsl-ls1028a-kontron-sl28-var4";
|
||||
firmware = "uboot";
|
||||
loadables = "uboot";
|
||||
fdt = "fdt-3";
|
||||
};
|
||||
};
|
||||
|
|
@ -102,6 +99,81 @@
|
|||
};
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31
|
||||
&binman {
|
||||
fit {
|
||||
images {
|
||||
bl31 {
|
||||
description = "ARM Trusted Firmware (bl31)";
|
||||
type = "firmware";
|
||||
arch = "arm";
|
||||
os = "arm-trusted-firmware";
|
||||
compression = "none";
|
||||
load = <CONFIG_SL28_BL31_ENTRY_ADDR>;
|
||||
entry = <CONFIG_SL28_BL31_ENTRY_ADDR>;
|
||||
|
||||
blob-ext {
|
||||
filename = "bl31.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
conf-1 {
|
||||
firmware = "bl31";
|
||||
loadables = "uboot";
|
||||
};
|
||||
|
||||
conf-2 {
|
||||
firmware = "bl31";
|
||||
loadables = "uboot";
|
||||
};
|
||||
|
||||
conf-3 {
|
||||
firmware = "bl31";
|
||||
loadables = "uboot";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32
|
||||
&binman {
|
||||
fit {
|
||||
images {
|
||||
bl32 {
|
||||
description = "OP-TEE Trusted OS (bl32)";
|
||||
type = "firmware";
|
||||
arch = "arm";
|
||||
os = "tee";
|
||||
compression = "none";
|
||||
load = <CONFIG_SL28_BL32_ENTRY_ADDR>;
|
||||
entry = <CONFIG_SL28_BL32_ENTRY_ADDR>;
|
||||
|
||||
blob-ext {
|
||||
filename = "tee.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
conf-1 {
|
||||
loadables = "uboot", "bl32";
|
||||
};
|
||||
|
||||
conf-2 {
|
||||
loadables = "uboot", "bl32";
|
||||
};
|
||||
|
||||
conf-3 {
|
||||
loadables = "uboot", "bl32";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
rtc: rtc@32 {
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
mmc0 = &sdhci1;
|
||||
ethernet0 = &gem1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -40,6 +41,29 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
|
||||
rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
|
||||
txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
|
||||
txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
|
||||
rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
|
||||
rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
|
||||
rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
|
||||
rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
|
||||
rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
|
||||
txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
|
||||
txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
|
||||
txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
|
||||
txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
mmc0 = &sdhci1;
|
||||
ethernet0 = &gem1; /* EMIO */
|
||||
i2c = &i2c0; /* EMIO */
|
||||
};
|
||||
|
||||
|
|
@ -222,6 +223,28 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
|
||||
rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
|
||||
txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
|
||||
txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
|
||||
rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
|
||||
rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
|
||||
rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
|
||||
rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
|
||||
rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
|
||||
txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
|
||||
txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
|
||||
txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
|
||||
txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
|
|
|
|||
|
|
@ -115,8 +115,10 @@
|
|||
<0x0 0xff9905e0 0x0 0x20>,
|
||||
<0x0 0xff990e80 0x0 0x20>,
|
||||
<0x0 0xff990ea0 0x0 0x20>;
|
||||
reg-names = "local_request_region", "local_response_region",
|
||||
"remote_request_region", "remote_response_region";
|
||||
reg-names = "local_request_region",
|
||||
"local_response_region",
|
||||
"remote_request_region",
|
||||
"remote_response_region";
|
||||
#mbox-cells = <1>;
|
||||
xlnx,ipi-id = <4>;
|
||||
};
|
||||
|
|
@ -145,15 +147,10 @@
|
|||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
#power-domain-cells = <1>;
|
||||
method = "smc";
|
||||
#power-domain-cells = <0x1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
|
||||
zynqmp_power: zynqmp-power {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
|
|
@ -163,6 +160,11 @@
|
|||
mbox-names = "tx", "rx";
|
||||
};
|
||||
|
||||
zynqmp_pcap: pcap {
|
||||
compatible = "xlnx,zynqmp-pcap-fpga";
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
|
||||
zynqmp_reset: reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
|
|
@ -206,26 +208,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
amba_apu: amba-apu@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0 0xffffffff>;
|
||||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x10000>,
|
||||
<0x0 0xf9020000 0x20000>,
|
||||
<0x0 0xf9040000 0x20000>,
|
||||
<0x0 0xf9060000 0x20000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
amba: axi {
|
||||
compatible = "simple-bus";
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -380,6 +363,18 @@
|
|||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x0 0x10000>,
|
||||
<0x0 0xf9020000 0x0 0x20000>,
|
||||
<0x0 0xf9040000 0x0 0x20000>,
|
||||
<0x0 0xf9060000 0x0 0x20000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd4b0000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,mali-400", "arm,mali-utgard";
|
||||
|
|
@ -590,7 +585,7 @@
|
|||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
compatible = "cdns,i2c-r1p14";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 4>;
|
||||
|
|
@ -601,7 +596,7 @@
|
|||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
compatible = "cdns,i2c-r1p14";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 18 4>;
|
||||
|
|
@ -639,8 +634,8 @@
|
|||
<0x0 0xfd480000 0x0 0x1000>,
|
||||
<0x80 0x00000000 0x0 0x1000000>;
|
||||
reg-names = "breg", "pcireg", "cfg";
|
||||
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
|
||||
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
|
||||
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
|
||||
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
|
||||
|
|
@ -770,7 +765,7 @@
|
|||
clock-output-names = "clk_out_sd1", "clk_in_sd1";
|
||||
};
|
||||
|
||||
smmu: smmu@fd800000 {
|
||||
smmu: iommu@fd800000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0xfd800000 0x0 0x20000>;
|
||||
#iommu-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ struct gpio_bank {
|
|||
};
|
||||
|
||||
/* Information about a GPIO bank */
|
||||
struct hikey_gpio_platdata {
|
||||
struct hikey_gpio_plat {
|
||||
int bank_index;
|
||||
ulong base; /* address of registers in physical memory */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
#include <asm/arch/sci/types.h>
|
||||
|
||||
struct imx8_power_domain_platdata {
|
||||
struct imx8_power_domain_plat {
|
||||
sc_rsrc_t resource_id;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
|
||||
#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
|
||||
|
||||
struct imx8m_power_domain_platdata {
|
||||
struct imx8m_power_domain_plat {
|
||||
int resource_id;
|
||||
int has_pd;
|
||||
struct power_domain pd;
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ struct vybrid_gpio_regs {
|
|||
u32 gpio_pdir;
|
||||
};
|
||||
|
||||
struct vybrid_gpio_platdata {
|
||||
struct vybrid_gpio_plat {
|
||||
unsigned int chip;
|
||||
u32 base;
|
||||
const char *port_name;
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ struct mxc_i2c_bus {
|
|||
/*
|
||||
* board file can use this index to locate which i2c_pads_info is for
|
||||
* i2c_idle_bus. When pinmux is implement, this entry can be
|
||||
* discarded. Here we do not use dev->seq, because we do not want to
|
||||
* discarded. Here we do not use dev_seq(dev), because we do not want to
|
||||
* export device to board file.
|
||||
*/
|
||||
int index;
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#if CONFIG_IS_ENABLED(DM_GPIO)
|
||||
|
||||
/* Information about a GPIO bank */
|
||||
struct omap_gpio_platdata {
|
||||
struct omap_gpio_plat {
|
||||
int bank_index;
|
||||
ulong base; /* address of registers in physical memory */
|
||||
const char *port_name;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#ifdef CONFIG_DM_I2C
|
||||
|
||||
/* Information about a GPIO bank */
|
||||
struct omap_i2c_platdata {
|
||||
struct omap_i2c_plat {
|
||||
ulong base; /* address of registers in physical memory */
|
||||
int speed;
|
||||
int ip_rev;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ struct omap_musb_board_data {
|
|||
|
||||
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
|
||||
|
||||
struct ti_musb_platdata {
|
||||
struct ti_musb_plat {
|
||||
void *base;
|
||||
void *ctrl_mod_base;
|
||||
struct musb_hdrc_platform_data plat;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ int arch_fixup_fdt(void *blob)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
|
||||
defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
|
||||
CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI)
|
||||
ret = psci_update_dt(blob);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -43,10 +43,10 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_IRQ,
|
||||
DM_GET_DRIVER(arm_gic_v3_its), &dev);
|
||||
DM_DRIVER_GET(arm_gic_v3_its), &dev);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to get %s irq device\n", __func__,
|
||||
DM_GET_DRIVER(arm_gic_v3_its)->name);
|
||||
DM_DRIVER_GET(arm_gic_v3_its)->name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -74,17 +74,17 @@ static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_SYSCON,
|
||||
DM_GET_DRIVER(gic_lpi_syscon), &dev);
|
||||
DM_DRIVER_GET(gic_lpi_syscon), &dev);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to get %s syscon device\n", __func__,
|
||||
DM_GET_DRIVER(gic_lpi_syscon)->name);
|
||||
DM_DRIVER_GET(gic_lpi_syscon)->name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
regmap = syscon_get_regmap(dev);
|
||||
if (!regmap) {
|
||||
pr_err("%s: failed to regmap for %s syscon device\n", __func__,
|
||||
DM_GET_DRIVER(gic_lpi_syscon)->name);
|
||||
DM_DRIVER_GET(gic_lpi_syscon)->name);
|
||||
return -ENODEV;
|
||||
}
|
||||
priv->lpi_base = regmap->ranges[0].start;
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#include <linux/sizes.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/psci.h>
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
#include <asm/armv8/sec_firmware.h>
|
||||
#endif
|
||||
|
||||
|
|
@ -64,7 +64,7 @@ int fdt_psci(void *fdt)
|
|||
return nodeoff;
|
||||
|
||||
init_psci_node:
|
||||
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
psci_ver = sec_firmware_support_psci_version();
|
||||
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
|
||||
psci_ver = ARM_PSCI_VER_1_0;
|
||||
|
|
@ -85,7 +85,7 @@ init_psci_node:
|
|||
return tmp;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
|
||||
#if !CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
|
||||
/*
|
||||
* The Secure firmware framework isn't able to support PSCI version 0.1.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
int ast_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(aspeed_ast2500_scu), devp);
|
||||
DM_DRIVER_GET(aspeed_ast2500_scu), devp);
|
||||
}
|
||||
|
||||
void *ast_get_scu(void)
|
||||
|
|
|
|||
|
|
@ -213,13 +213,13 @@ void at91_sdram_hw_init(void)
|
|||
}
|
||||
|
||||
/* Platform data for the GPIOs */
|
||||
static const struct at91_port_platdata at91sam9260_plat[] = {
|
||||
static const struct at91_port_plat at91sam9260_plat[] = {
|
||||
{ ATMEL_BASE_PIOA, "PA" },
|
||||
{ ATMEL_BASE_PIOB, "PB" },
|
||||
{ ATMEL_BASE_PIOC, "PC" },
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(at91sam9260_gpios) = {
|
||||
U_BOOT_DRVINFOS(at91sam9260_gpios) = {
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ void at91_mci_hw_init(void)
|
|||
#endif
|
||||
|
||||
/* Platform data for the GPIOs */
|
||||
static const struct at91_port_platdata at91sam9260_plat[] = {
|
||||
static const struct at91_port_plat at91sam9260_plat[] = {
|
||||
{ ATMEL_BASE_PIOA, "PA" },
|
||||
{ ATMEL_BASE_PIOB, "PB" },
|
||||
{ ATMEL_BASE_PIOC, "PC" },
|
||||
|
|
@ -175,7 +175,7 @@ static const struct at91_port_platdata at91sam9260_plat[] = {
|
|||
{ ATMEL_BASE_PIOE, "PE" },
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(at91sam9260_gpios) = {
|
||||
U_BOOT_DRVINFOS(at91sam9260_gpios) = {
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
|
||||
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#define _ATMEL_SERIAL_H
|
||||
|
||||
/* Information about a serial port */
|
||||
struct atmel_serial_platdata {
|
||||
struct atmel_serial_plat {
|
||||
uint32_t base_addr;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio)
|
|||
}
|
||||
|
||||
/* Platform data for each GPIO port */
|
||||
struct at91_port_platdata {
|
||||
struct at91_port_plat {
|
||||
uint32_t base_addr;
|
||||
const char *bank_name;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,11 +52,11 @@ struct bcm2835_gpio_regs {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct bcm2835_gpio_platdata - GPIO platform description
|
||||
* struct bcm2835_gpio_plat - GPIO platform description
|
||||
*
|
||||
* @base: Base address of GPIO controller
|
||||
*/
|
||||
struct bcm2835_gpio_platdata {
|
||||
struct bcm2835_gpio_plat {
|
||||
unsigned long base;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -290,8 +290,8 @@ int arch_cpu_init(void)
|
|||
board_gpio_init();
|
||||
|
||||
#if !CONFIG_IS_ENABLED(DM_SERIAL)
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
#endif
|
||||
/*
|
||||
* Fix Power and Emulation Management Register
|
||||
|
|
|
|||
|
|
@ -27,9 +27,9 @@ void puts(const char *str)
|
|||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
|
||||
ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
|
||||
ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c);
|
||||
}
|
||||
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
|
||||
|
||||
|
|
|
|||
|
|
@ -44,9 +44,9 @@ static const struct imx_thermal_plat imx6_thermal_plat = {
|
|||
.fuse_word = 6,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(imx6_thermal) = {
|
||||
U_BOOT_DRVINFO(imx6_thermal) = {
|
||||
.name = "imx_thermal",
|
||||
.platdata = &imx6_thermal_plat,
|
||||
.plat = &imx6_thermal_plat,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -60,9 +60,9 @@ static const struct imx_thermal_plat imx7_thermal_plat = {
|
|||
.fuse_word = 3,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(imx7_thermal) = {
|
||||
U_BOOT_DRVINFO(imx7_thermal) = {
|
||||
.name = "imx_thermal",
|
||||
.platdata = &imx7_thermal_plat,
|
||||
.plat = &imx7_thermal_plat,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
|
||||
|
|
@ -25,9 +25,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
|
|||
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
|
||||
/* This clock is already initialized by SBL1 */
|
||||
return 0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -35,7 +34,7 @@ static int msm_clk_probe(struct udevice *dev)
|
|||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->base = devfdt_get_addr(dev);
|
||||
priv->base = dev_read_addr(dev);
|
||||
if (priv->base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -53,13 +52,19 @@ static int msm_enable(struct clk *clk)
|
|||
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
|
||||
/* This clock is already initialized by SBL1 */
|
||||
return 0;
|
||||
break;
|
||||
case GCC_PRNG_AHB_CLK: /*PRNG*/
|
||||
/* This clock is already initialized by SBL1 */
|
||||
return 0;
|
||||
break;
|
||||
default:
|
||||
case GCC_USB3_MASTER_CLK:
|
||||
case GCC_USB3_SLEEP_CLK:
|
||||
case GCC_USB3_MOCK_UTMI_CLK:
|
||||
case GCC_USB2_MASTER_CLK:
|
||||
case GCC_USB2_SLEEP_CLK:
|
||||
case GCC_USB2_MOCK_UTMI_CLK:
|
||||
/* These clocks is already initialized by SBL1 */
|
||||
return 0;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -78,6 +83,6 @@ U_BOOT_DRIVER(clk_msm) = {
|
|||
.id = UCLASS_CLK,
|
||||
.of_match = msm_clk_ids,
|
||||
.ops = &msm_clk_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
|
||||
.priv_auto = sizeof(struct msm_clk_priv),
|
||||
.probe = msm_clk_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
|
|||
.name = "pinctrl_msm",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = msm_pinctrl_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
|
||||
.priv_auto = sizeof(struct msm_pinctrl_priv),
|
||||
.ops = &msm_pinctrl_ops,
|
||||
.probe = msm_pinctrl_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -208,7 +208,7 @@ void board_init_f(ulong dummy)
|
|||
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
||||
* to initialize its pin settings.
|
||||
*/
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
|
|
@ -238,7 +238,7 @@ void board_init_f(ulong dummy)
|
|||
do_board_detect();
|
||||
|
||||
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
|
||||
&dev);
|
||||
if (ret)
|
||||
printf("AVS init failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ struct ti_sci_handle *get_ti_sci_handle(void)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
|
||||
DM_GET_DRIVER(ti_sci), &dev);
|
||||
DM_DRIVER_GET(ti_sci), &dev);
|
||||
if (ret)
|
||||
panic("Failed to get SYSFW (%d)\n", ret);
|
||||
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ void board_init_f(ulong dummy)
|
|||
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
||||
* to initialize its pin settings.
|
||||
*/
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
|
|
@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
|
|||
do_board_detect();
|
||||
|
||||
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
|
||||
&dev);
|
||||
if (ret)
|
||||
printf("AVS init failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ static void *k3_sysfw_get_spi_addr(void)
|
|||
int ret;
|
||||
|
||||
ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS,
|
||||
true, &dev);
|
||||
&dev);
|
||||
if (ret)
|
||||
return NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ int arch_cpu_init(void)
|
|||
* driver doesn't handle this.
|
||||
*/
|
||||
#ifndef CONFIG_DM_SERIAL
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
|
||||
ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
|
|||
}
|
||||
|
||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
static const struct ns16550_platdata lpc32xx_uart[] = {
|
||||
static const struct ns16550_plat lpc32xx_uart[] = {
|
||||
{ .base = UART3_BASE, .reg_shift = 2,
|
||||
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
|
||||
{ .base = UART4_BASE, .reg_shift = 2,
|
||||
|
|
@ -55,14 +55,14 @@ static const struct ns16550_platdata lpc32xx_uart[] = {
|
|||
};
|
||||
|
||||
#if defined(CONFIG_LPC32XX_HSUART)
|
||||
static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
|
||||
static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
|
||||
{ HS_UART1_BASE, },
|
||||
{ HS_UART2_BASE, },
|
||||
{ HS_UART7_BASE, },
|
||||
};
|
||||
#endif
|
||||
|
||||
U_BOOT_DEVICES(lpc32xx_uarts) = {
|
||||
U_BOOT_DRVINFOS(lpc32xx_uarts) = {
|
||||
#if defined(CONFIG_LPC32XX_HSUART)
|
||||
{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
|
||||
{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
|
||||
|
|
@ -124,7 +124,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
|
|||
writel(ctrl, &clk->i2cclk_ctrl);
|
||||
}
|
||||
|
||||
U_BOOT_DEVICE(lpc32xx_gpios) = {
|
||||
U_BOOT_DRVINFO(lpc32xx_gpios) = {
|
||||
.name = "gpio_lpc32xx"
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ int mtk_pll_early_init(void)
|
|||
int ret, i;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
|
||||
DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -59,7 +59,7 @@ int mtk_pll_early_init(void)
|
|||
|
||||
/* setup mcu bus */
|
||||
ret = uclass_get_device_by_driver(UCLASS_SYSCON,
|
||||
DM_GET_DRIVER(mtk_mcucfg), &dev);
|
||||
DM_DRIVER_GET(mtk_mcucfg), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ int mtk_pll_early_init(void)
|
|||
int ret, i;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
|
||||
DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ struct dp_hdmi_dev {
|
|||
};
|
||||
|
||||
/* platform data for the driver model */
|
||||
struct nx_display_platdata {
|
||||
struct nx_display_plat {
|
||||
int module;
|
||||
struct dp_sync_info sync;
|
||||
struct dp_ctrl_info ctrl;
|
||||
|
|
@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps);
|
|||
|
||||
#if defined CONFIG_SPL_BUILD || \
|
||||
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
|
||||
int nx_display_probe(struct nx_display_platdata *plat);
|
||||
int nx_display_probe(struct nx_display_plat *plat);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ int dram_init_banksize(void)
|
|||
}
|
||||
|
||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
static const struct ns16550_platdata am33xx_serial[] = {
|
||||
static const struct ns16550_plat am33xx_serial[] = {
|
||||
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
|
||||
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
|
||||
# ifdef CONFIG_SYS_NS16550_COM2
|
||||
|
|
@ -99,7 +99,7 @@ static const struct ns16550_platdata am33xx_serial[] = {
|
|||
# endif
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(am33xx_uarts) = {
|
||||
U_BOOT_DRVINFOS(am33xx_uarts) = {
|
||||
{ "ns16550_serial", &am33xx_serial[0] },
|
||||
# ifdef CONFIG_SYS_NS16550_COM2
|
||||
{ "ns16550_serial", &am33xx_serial[1] },
|
||||
|
|
@ -113,13 +113,13 @@ U_BOOT_DEVICES(am33xx_uarts) = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_DM_I2C
|
||||
static const struct omap_i2c_platdata am33xx_i2c[] = {
|
||||
static const struct omap_i2c_plat am33xx_i2c[] = {
|
||||
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
|
||||
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
|
||||
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(am33xx_i2c) = {
|
||||
U_BOOT_DRVINFOS(am33xx_i2c) = {
|
||||
{ "i2c_omap", &am33xx_i2c[0] },
|
||||
{ "i2c_omap", &am33xx_i2c[1] },
|
||||
{ "i2c_omap", &am33xx_i2c[2] },
|
||||
|
|
@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
|
|||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_GPIO)
|
||||
static const struct omap_gpio_platdata am33xx_gpio[] = {
|
||||
static const struct omap_gpio_plat am33xx_gpio[] = {
|
||||
{ 0, AM33XX_GPIO0_BASE },
|
||||
{ 1, AM33XX_GPIO1_BASE },
|
||||
{ 2, AM33XX_GPIO2_BASE },
|
||||
|
|
@ -138,7 +138,7 @@ static const struct omap_gpio_platdata am33xx_gpio[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(am33xx_gpios) = {
|
||||
U_BOOT_DRVINFOS(am33xx_gpios) = {
|
||||
{ "gpio_omap", &am33xx_gpio[0] },
|
||||
{ "gpio_omap", &am33xx_gpio[1] },
|
||||
{ "gpio_omap", &am33xx_gpio[2] },
|
||||
|
|
@ -155,9 +155,9 @@ static const struct omap3_spi_plat omap3_spi_pdata = {
|
|||
.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(am33xx_spi) = {
|
||||
U_BOOT_DRVINFO(am33xx_spi) = {
|
||||
.name = "omap3_spi",
|
||||
.platdata = &omap3_spi_pdata,
|
||||
.plat = &omap3_spi_pdata,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
static struct ti_musb_platdata usb0 = {
|
||||
static struct ti_musb_plat usb0 = {
|
||||
.base = (void *)USB0_OTG_BASE,
|
||||
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
|
||||
.plat = {
|
||||
|
|
@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct ti_musb_platdata usb1 = {
|
||||
static struct ti_musb_plat usb1 = {
|
||||
.base = (void *)USB1_OTG_BASE,
|
||||
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
|
||||
.plat = {
|
||||
|
|
@ -234,7 +234,7 @@ static struct ti_musb_platdata usb1 = {
|
|||
},
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(am33xx_usbs) = {
|
||||
U_BOOT_DRVINFOS(am33xx_usbs) = {
|
||||
#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
|
||||
{ "ti-musb-peripheral", &usb0 },
|
||||
#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void);
|
|||
#if CONFIG_IS_ENABLED(DM_GPIO)
|
||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
|
||||
static const struct omap_gpio_platdata omap34xx_gpio[] = {
|
||||
static const struct omap_gpio_plat omap34xx_gpio[] = {
|
||||
{ 0, OMAP34XX_GPIO1_BASE },
|
||||
{ 1, OMAP34XX_GPIO2_BASE },
|
||||
{ 2, OMAP34XX_GPIO3_BASE },
|
||||
|
|
@ -47,7 +47,7 @@ static const struct omap_gpio_platdata omap34xx_gpio[] = {
|
|||
{ 5, OMAP34XX_GPIO6_BASE },
|
||||
};
|
||||
|
||||
U_BOOT_DEVICES(omap34xx_gpios) = {
|
||||
U_BOOT_DRVINFOS(omap34xx_gpios) = {
|
||||
{ "gpio_omap", &omap34xx_gpio[0] },
|
||||
{ "gpio_omap", &omap34xx_gpio[1] },
|
||||
{ "gpio_omap", &omap34xx_gpio[2] },
|
||||
|
|
|
|||
|
|
@ -16,12 +16,14 @@ choice
|
|||
config TARGET_QEMU_ARM_32BIT
|
||||
bool "ARMv7-A, 32bit"
|
||||
select ARCH_SUPPORT_PSCI
|
||||
select BOARD_LATE_INIT
|
||||
select CPU_V7A
|
||||
select SYS_ARCH_TIMER
|
||||
|
||||
config TARGET_QEMU_ARM_64BIT
|
||||
bool "ARMv8, 64bit"
|
||||
select ARM64
|
||||
select BOARD_LATE_INIT
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
|
|||
|
|
@ -67,10 +67,10 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
|
|||
/* retrieve the device */
|
||||
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(rockchip_efuse), &dev);
|
||||
DM_DRIVER_GET(rockchip_efuse), &dev);
|
||||
#elif CONFIG_IS_ENABLED(ROCKCHIP_OTP)
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(rockchip_otp), &dev);
|
||||
DM_DRIVER_GET(rockchip_otp), &dev);
|
||||
#endif
|
||||
if (ret) {
|
||||
debug("%s: could not find efuse device\n", __func__);
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_px30_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_px30_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int px30_syscon_bind_of_platdata(struct udevice *dev)
|
||||
static int px30_syscon_bind_of_plat(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
|
@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = {
|
|||
.name = "rockchip_px30_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = px30_syscon_ids,
|
||||
.bind = px30_syscon_bind_of_platdata,
|
||||
.bind = px30_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
|
||||
.name = "rockchip_px30_pmugrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = px30_syscon_ids + 1,
|
||||
.bind = px30_syscon_bind_of_platdata,
|
||||
.bind = px30_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_px30_grf) = {
|
||||
.name = "rockchip_px30_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = px30_syscon_ids + 2,
|
||||
.bind = px30_syscon_bind_of_platdata,
|
||||
.bind = px30_syscon_bind_of_plat,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3036_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3036_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3128_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3128_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3188_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3188_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
|
||||
static int rk3188_syscon_bind_of_plat(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
|
@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = {
|
|||
.name = "rockchip_rk3188_noc",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3188_syscon_ids,
|
||||
.bind = rk3188_syscon_bind_of_platdata,
|
||||
.bind = rk3188_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3188_grf) = {
|
||||
.name = "rockchip_rk3188_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3188_syscon_ids + 1,
|
||||
.bind = rk3188_syscon_bind_of_platdata,
|
||||
.bind = rk3188_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
|
||||
.name = "rockchip_rk3188_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3188_syscon_ids + 2,
|
||||
.bind = rk3188_syscon_bind_of_platdata,
|
||||
.bind = rk3188_syscon_bind_of_plat,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk322x_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk322x_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3288_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3288_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
|
||||
static int rk3288_syscon_bind_of_plat(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
|
@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = {
|
|||
.name = "rockchip_rk3288_noc",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
.bind = rk3288_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
|
||||
.name = "rockchip_rk3288_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 1,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
.bind = rk3288_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
|
||||
.name = "rockchip_rk3288_sgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 2,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
.bind = rk3288_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
|
||||
.name = "rockchip_rk3288_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3288_syscon_ids + 3,
|
||||
.bind = rk3288_syscon_bind_of_platdata,
|
||||
.bind = rk3288_syscon_bind_of_plat,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3308_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3308_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3328_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3328_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3368_cru), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3368_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
|
||||
static int rk3368_syscon_bind_of_plat(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
|
@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = {
|
|||
.name = "rockchip_rk3368_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
.bind = rk3368_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
|
||||
.name = "rockchip_rk3368_pmugrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 1,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
.bind = rk3368_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
|
||||
.name = "rockchip_rk3368_msch",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 2,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
.bind = rk3368_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
|
||||
.name = "rockchip_rk3368_sgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3368_syscon_ids + 3,
|
||||
.bind = rk3368_syscon_bind_of_platdata,
|
||||
.bind = rk3368_syscon_bind_of_plat,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
static int rockchip_get_cruclk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(clk_rk3399), devp);
|
||||
DM_DRIVER_GET(clk_rk3399), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
@ -35,7 +35,7 @@ void *rockchip_get_cru(void)
|
|||
static int rockchip_get_pmucruclk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
|
||||
DM_DRIVER_GET(rockchip_rk3399_pmuclk), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_pmucru(void)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ U_BOOT_DRIVER(syscon_rk3399) = {
|
|||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
|
||||
static int rk3399_syscon_bind_of_plat(struct udevice *dev)
|
||||
{
|
||||
dev->driver_data = dev->driver->of_match->data;
|
||||
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
|
||||
|
|
@ -40,34 +40,34 @@ U_BOOT_DRIVER(rockchip_rk3399_grf) = {
|
|||
.name = "rockchip_rk3399_grf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
.bind = rk3399_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
|
||||
.name = "rockchip_rk3399_pmugrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 1,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
.bind = rk3399_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
|
||||
.name = "rockchip_rk3399_pmusgrf",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 2,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
.bind = rk3399_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_cic) = {
|
||||
.name = "rockchip_rk3399_cic",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 3,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
.bind = rk3399_syscon_bind_of_plat,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
|
||||
.name = "rockchip_rk3399_pmu",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3399_syscon_ids + 4,
|
||||
.bind = rk3399_syscon_bind_of_platdata,
|
||||
.bind = rk3399_syscon_bind_of_plat,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(clk_rv1108), devp);
|
||||
DM_DRIVER_GET(clk_rv1108), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static int spl_node_to_boot_device(int node)
|
|||
dev;
|
||||
device_find_next_child(&dev)) {
|
||||
if (device_get_uclass_id(dev) == UCLASS_BLK) {
|
||||
desc = dev_get_uclass_platdata(dev);
|
||||
desc = dev_get_uclass_plat(dev);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -99,7 +99,7 @@ __weak const char *board_spl_was_booted_from(void)
|
|||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
/* In case of no fdt (or only platdata), use spl_boot_device() */
|
||||
/* In case of no fdt (or only plat), use spl_boot_device() */
|
||||
if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) {
|
||||
spl_boot_list[0] = spl_boot_device();
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -143,6 +143,6 @@ U_BOOT_DRIVER(clk_msm) = {
|
|||
.id = UCLASS_CLK,
|
||||
.of_match = msm_clk_ids,
|
||||
.ops = &msm_clk_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
|
||||
.priv_auto = sizeof(struct msm_clk_priv),
|
||||
.probe = msm_clk_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
|
|||
.name = "pinctrl_msm",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = msm_pinctrl_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
|
||||
.priv_auto = sizeof(struct msm_pinctrl_priv),
|
||||
.ops = &msm_pinctrl_ops,
|
||||
.probe = msm_pinctrl_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(socfpga_agilex_clk),
|
||||
DM_DRIVER_GET(socfpga_agilex_clk),
|
||||
&dev);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -280,13 +280,13 @@ static int bsec_program_otp(long base, u32 val, u32 otp)
|
|||
}
|
||||
|
||||
/* BSEC MISC driver *******************************************************/
|
||||
struct stm32mp_bsec_platdata {
|
||||
struct stm32mp_bsec_plat {
|
||||
u32 base;
|
||||
};
|
||||
|
||||
static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
u32 tmp_data = 0;
|
||||
int ret;
|
||||
|
||||
|
|
@ -295,7 +295,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
|
|||
STM32_SMC_READ_OTP,
|
||||
otp, 0, val);
|
||||
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
/* read current shadow value */
|
||||
ret = bsec_read_shadow(plat->base, &tmp_data, otp);
|
||||
|
|
@ -319,21 +319,21 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
|
|||
|
||||
static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
|
||||
if (IS_ENABLED(CONFIG_TFABOOT))
|
||||
return stm32_smc(STM32_SMC_BSEC,
|
||||
STM32_SMC_READ_SHADOW,
|
||||
otp, 0, val);
|
||||
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
return bsec_read_shadow(plat->base, val, otp);
|
||||
}
|
||||
|
||||
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
|
||||
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
|
||||
|
||||
/* return OTP permanent write lock status */
|
||||
*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
|
||||
|
|
@ -343,14 +343,14 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
|
|||
|
||||
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
|
||||
if (IS_ENABLED(CONFIG_TFABOOT))
|
||||
return stm32_smc_exec(STM32_SMC_BSEC,
|
||||
STM32_SMC_PROG_OTP,
|
||||
otp, val);
|
||||
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
return bsec_program_otp(plat->base, val, otp);
|
||||
|
||||
|
|
@ -358,14 +358,14 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
|
|||
|
||||
static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
|
||||
if (IS_ENABLED(CONFIG_TFABOOT))
|
||||
return stm32_smc_exec(STM32_SMC_BSEC,
|
||||
STM32_SMC_WRITE_SHADOW,
|
||||
otp, val);
|
||||
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
return bsec_write_shadow(plat->base, val, otp);
|
||||
}
|
||||
|
|
@ -473,9 +473,9 @@ static const struct misc_ops stm32mp_bsec_ops = {
|
|||
.write = stm32mp_bsec_write,
|
||||
};
|
||||
|
||||
static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
|
||||
static int stm32mp_bsec_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
|
||||
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
|
||||
|
||||
plat->base = (u32)dev_read_addr_ptr(dev);
|
||||
|
||||
|
|
@ -485,7 +485,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
|
|||
static int stm32mp_bsec_probe(struct udevice *dev)
|
||||
{
|
||||
int otp;
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
|
||||
/*
|
||||
* update unlocked shadow for OTP cleared by the rom code
|
||||
|
|
@ -493,7 +493,7 @@ static int stm32mp_bsec_probe(struct udevice *dev)
|
|||
*/
|
||||
|
||||
if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
|
||||
if (!bsec_read_SR_lock(plat->base, otp))
|
||||
|
|
@ -512,8 +512,8 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
|
|||
.name = "stm32mp_bsec",
|
||||
.id = UCLASS_MISC,
|
||||
.of_match = stm32mp_bsec_ids,
|
||||
.ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
|
||||
.of_to_plat = stm32mp_bsec_of_to_plat,
|
||||
.plat_auto = sizeof(struct stm32mp_bsec_plat),
|
||||
.ops = &stm32mp_bsec_ops,
|
||||
.probe = stm32mp_bsec_probe,
|
||||
};
|
||||
|
|
@ -521,17 +521,17 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
|
|||
bool bsec_dbgswenable(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
struct stm32mp_bsec_platdata *plat;
|
||||
struct stm32mp_bsec_plat *plat;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec), &dev);
|
||||
DM_DRIVER_GET(stm32mp_bsec), &dev);
|
||||
if (ret || !dev) {
|
||||
pr_debug("bsec driver not available\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
plat = dev_get_platdata(dev);
|
||||
plat = dev_get_plat(dev);
|
||||
if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
|
||||
return true;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ static void fuse_hash_value(u32 addr, bool print)
|
|||
int i, ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
DM_DRIVER_GET(stm32mp_bsec),
|
||||
&dev);
|
||||
if (ret) {
|
||||
pr_err("Can't find stm32mp_bsec driver\n");
|
||||
|
|
|
|||
|
|
@ -1340,7 +1340,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
|
|||
|
||||
pr_debug("%s: %x %lx\n", __func__, offset, *size);
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stpmic1_nvm),
|
||||
DM_DRIVER_GET(stpmic1_nvm),
|
||||
&dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1351,7 +1351,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
|
|||
memset(data->pmic_part, 0, PMIC_SIZE);
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stpmic1_nvm),
|
||||
DM_DRIVER_GET(stpmic1_nvm),
|
||||
&dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1389,7 +1389,7 @@ int stm32prog_pmic_start(struct stm32prog_data *data)
|
|||
}
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stpmic1_nvm),
|
||||
DM_DRIVER_GET(stpmic1_nvm),
|
||||
&dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -318,7 +318,7 @@ static u32 get_otp(int index, int shift, int mask)
|
|||
u32 otp = 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
DM_DRIVER_GET(stm32mp_bsec),
|
||||
&dev);
|
||||
|
||||
if (!ret)
|
||||
|
|
@ -563,7 +563,7 @@ __weak int setup_mac_address(void)
|
|||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
DM_DRIVER_GET(stm32mp_bsec),
|
||||
&dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -601,7 +601,7 @@ static int setup_serial_number(void)
|
|||
return 0;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
||||
DM_GET_DRIVER(stm32mp_bsec),
|
||||
DM_DRIVER_GET(stm32mp_bsec),
|
||||
&dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <syscon.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/err.h>
|
||||
#include <power/pmic.h>
|
||||
|
|
@ -59,7 +60,7 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
|
||||
static int stm32mp_pwr_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
|
||||
|
||||
|
|
@ -80,7 +81,7 @@ static int stm32mp_pwr_bind(struct udevice *dev)
|
|||
{
|
||||
int children;
|
||||
|
||||
children = pmic_bind_children(dev, dev->node, pwr_children_info);
|
||||
children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info);
|
||||
if (!children)
|
||||
dev_dbg(dev, "no child found\n");
|
||||
|
||||
|
|
@ -103,8 +104,8 @@ U_BOOT_DRIVER(stm32mp_pwr_pmic) = {
|
|||
.of_match = stm32mp_pwr_ids,
|
||||
.bind = stm32mp_pwr_bind,
|
||||
.ops = &stm32mp_pwr_ops,
|
||||
.ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
|
||||
.priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv),
|
||||
.of_to_plat = stm32mp_pwr_of_to_plat,
|
||||
.priv_auto = sizeof(struct stm32mp_pwr_priv),
|
||||
};
|
||||
|
||||
static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
|
||||
|
|
@ -135,9 +136,9 @@ static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = {
|
|||
static int stm32mp_pwr_regulator_probe(struct udevice *dev)
|
||||
{
|
||||
const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos;
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
struct dm_regulator_uclass_plat *uc_pdata;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
uc_pdata = dev_get_uclass_plat(dev);
|
||||
|
||||
while (*p) {
|
||||
int rc;
|
||||
|
|
@ -165,16 +166,16 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev)
|
|||
}
|
||||
|
||||
uc_pdata->type = REGULATOR_TYPE_FIXED;
|
||||
dev->priv = (void *)*p;
|
||||
dev_set_priv(dev, (void *)*p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
struct dm_regulator_uclass_plat *uc_pdata;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
uc_pdata = dev_get_uclass_plat(dev);
|
||||
if (!uc_pdata)
|
||||
return -ENXIO;
|
||||
|
||||
|
|
@ -188,9 +189,9 @@ static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
|
|||
|
||||
static int stm32mp_pwr_regulator_get_value(struct udevice *dev)
|
||||
{
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
struct dm_regulator_uclass_plat *uc_pdata;
|
||||
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
uc_pdata = dev_get_uclass_plat(dev);
|
||||
if (!uc_pdata)
|
||||
return -ENXIO;
|
||||
|
||||
|
|
|
|||
|
|
@ -257,14 +257,14 @@ void board_init_uart_f(void)
|
|||
}
|
||||
|
||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
static struct ns16550_platdata ns16550_com1_pdata = {
|
||||
static struct ns16550_plat ns16550_com1_pdata = {
|
||||
.base = CONFIG_SYS_NS16550_COM1,
|
||||
.reg_shift = 2,
|
||||
.clock = CONFIG_SYS_NS16550_CLK,
|
||||
.fcr = UART_FCR_DEFVAL,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(ns16550_com1) = {
|
||||
U_BOOT_DRVINFO(ns16550_com1) = {
|
||||
"ns16550_serial", &ns16550_com1_pdata
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
|
||||
U_BOOT_DEVICE(tegra_gpios) = {
|
||||
U_BOOT_DRVINFO(tegra_gpios) = {
|
||||
"gpio_tegra"
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ void support_card_init(void)
|
|||
|
||||
/* The system bus must be initialized for access to the support card. */
|
||||
ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS,
|
||||
DM_GET_DRIVER(uniphier_system_bus_driver),
|
||||
DM_DRIVER_GET(uniphier_system_bus_driver),
|
||||
&dev);
|
||||
if (ret)
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ int set_cpu_clk_info(void)
|
|||
int i, ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(zynq_clk), &dev);
|
||||
DM_DRIVER_GET(zynq_clk), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -75,7 +75,7 @@ int soc_clk_dump(void)
|
|||
int i, ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(zynq_clk), &dev);
|
||||
DM_DRIVER_GET(zynq_clk), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ int timer_init(void)
|
|||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_GET_DRIVER(zynq_clk), &dev);
|
||||
DM_DRIVER_GET(zynq_clk), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
0
arch/m68k/include/asm/spl.h
Normal file
0
arch/m68k/include/asm/spl.h
Normal file
|
|
@ -74,7 +74,7 @@ int print_cpuinfo(void)
|
|||
ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
|
||||
chipmode & 0x02 ? "XTAL" : "CPLL");
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk),
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk),
|
||||
&clkdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
0
arch/nds32/include/asm/spl.h
Normal file
0
arch/nds32/include/asm/spl.h
Normal file
0
arch/nios2/include/asm/spl.h
Normal file
0
arch/nios2/include/asm/spl.h
Normal file
|
|
@ -28,7 +28,7 @@ enum gpio_state {
|
|||
};
|
||||
|
||||
/* Details about a GPIO bank */
|
||||
struct sifive_gpio_platdata {
|
||||
struct sifive_gpio_plat {
|
||||
void *base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ enum gpio_state {
|
|||
};
|
||||
|
||||
/* Details about a GPIO bank */
|
||||
struct sifive_gpio_platdata {
|
||||
struct sifive_gpio_plat {
|
||||
void *base; /* address of registers in physical memory */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ int riscv_init_ipi(void)
|
|||
struct udevice *dev;
|
||||
|
||||
ret = uclass_get_device_by_driver(UCLASS_TIMER,
|
||||
DM_GET_DRIVER(sifive_clint), &dev);
|
||||
DM_DRIVER_GET(sifive_clint), &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,15 @@ config HOST_64BIT
|
|||
|
||||
endchoice
|
||||
|
||||
config SANDBOX_CRASH_RESET
|
||||
bool "Reset on crash"
|
||||
help
|
||||
If an illegal instruction or an illegal memory access occurs, the
|
||||
sandbox by default writes a crash dump and exits. If you set this
|
||||
flag, the sandbox is reset instead. This may be useful when running
|
||||
test suites like the UEFI self certification test which continue
|
||||
with the next test after a crash.
|
||||
|
||||
config SANDBOX_BITS_PER_LONG
|
||||
int
|
||||
default 32 if HOST_32BIT
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
obj-y := cpu.o state.o
|
||||
obj-y := cache.o cpu.o state.o
|
||||
extra-y := start.o os.o
|
||||
extra-$(CONFIG_SANDBOX_SDL) += sdl.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
|
|
|
|||
23
arch/sandbox/cpu/cache.c
Normal file
23
arch/sandbox/cpu/cache.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <asm/state.h>
|
||||
|
||||
void flush_cache(unsigned long addr, unsigned long size)
|
||||
{
|
||||
/* Clang uses (char *) parameters, GCC (void *) */
|
||||
__builtin___clear_cache((void *)addr, (void *)(addr + size));
|
||||
}
|
||||
|
||||
void invalidate_icache_all(void)
|
||||
{
|
||||
struct sandbox_state *state = state_get_current();
|
||||
|
||||
/* Clang uses (char *) parameters, GCC (void *) */
|
||||
__builtin___clear_cache((void *)state->ram_buf,
|
||||
(void *)(state->ram_buf + state->ram_size));
|
||||
}
|
||||
|
|
@ -3,6 +3,8 @@
|
|||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
*/
|
||||
|
||||
#define _GNU_SOURCE
|
||||
|
||||
#include <dirent.h>
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
|
|
@ -15,11 +17,13 @@
|
|||
#include <string.h>
|
||||
#include <termios.h>
|
||||
#include <time.h>
|
||||
#include <ucontext.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/types.h>
|
||||
#include <linux/compiler_attributes.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/getopt.h>
|
||||
|
|
@ -191,6 +195,42 @@ static void os_sigint_handler(int sig)
|
|||
raise(SIGINT);
|
||||
}
|
||||
|
||||
static void os_signal_handler(int sig, siginfo_t *info, void *con)
|
||||
{
|
||||
ucontext_t __maybe_unused *context = con;
|
||||
unsigned long pc;
|
||||
|
||||
#if defined(__x86_64__)
|
||||
pc = context->uc_mcontext.gregs[REG_RIP];
|
||||
#elif defined(__aarch64__)
|
||||
pc = context->uc_mcontext.pc;
|
||||
#elif defined(__riscv)
|
||||
pc = context->uc_mcontext.__gregs[REG_PC];
|
||||
#else
|
||||
const char msg[] =
|
||||
"\nUnsupported architecture, cannot read program counter\n";
|
||||
|
||||
os_write(1, msg, sizeof(msg));
|
||||
pc = 0;
|
||||
#endif
|
||||
|
||||
os_signal_action(sig, pc);
|
||||
}
|
||||
|
||||
int os_setup_signal_handlers(void)
|
||||
{
|
||||
struct sigaction act;
|
||||
|
||||
act.sa_sigaction = os_signal_handler;
|
||||
sigemptyset(&act.sa_mask);
|
||||
act.sa_flags = SA_SIGINFO | SA_NODEFER;
|
||||
if (sigaction(SIGILL, &act, NULL) ||
|
||||
sigaction(SIGBUS, &act, NULL) ||
|
||||
sigaction(SIGSEGV, &act, NULL))
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Put tty into raw mode so <tab> and <ctrl+c> work */
|
||||
void os_tty_raw(int fd, bool allow_sigs)
|
||||
{
|
||||
|
|
@ -750,6 +790,11 @@ int os_find_u_boot(char *fname, int maxlen)
|
|||
|
||||
int os_spl_to_uboot(const char *fname)
|
||||
{
|
||||
struct sandbox_state *state = state_get_current();
|
||||
|
||||
printf("%s\n", __func__);
|
||||
/* U-Boot will delete ram buffer after read: "--rm_memory"*/
|
||||
state->ram_buf_rm = true;
|
||||
return os_jump_to_file(fname);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <dm/root.h>
|
||||
#include <efi_loader.h>
|
||||
#include <errno.h>
|
||||
#include <init.h>
|
||||
#include <os.h>
|
||||
|
|
@ -406,6 +407,15 @@ void state_show(struct sandbox_state *state)
|
|||
printf("\n");
|
||||
}
|
||||
|
||||
void __efi_runtime EFIAPI efi_reset_system(
|
||||
enum efi_reset_type reset_type,
|
||||
efi_status_t reset_status,
|
||||
unsigned long data_size, void *reset_data)
|
||||
{
|
||||
os_fd_restore();
|
||||
os_relaunch(os_argv);
|
||||
}
|
||||
|
||||
void sandbox_reset(void)
|
||||
{
|
||||
/* Do this here while it still has an effect */
|
||||
|
|
@ -447,10 +457,21 @@ int main(int argc, char *argv[])
|
|||
if (os_parse_args(state, argc, argv))
|
||||
return 1;
|
||||
|
||||
/* Remove old memory file if required */
|
||||
if (state->ram_buf_rm && state->ram_buf_fname) {
|
||||
os_unlink(state->ram_buf_fname);
|
||||
state->write_ram_buf = false;
|
||||
state->ram_buf_fname = NULL;
|
||||
}
|
||||
|
||||
ret = sandbox_read_state(state, state->state_fname);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = os_setup_signal_handlers();
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
|
||||
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -415,10 +415,6 @@ int state_uninit(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* Remove old memory file if required */
|
||||
if (state->ram_buf_rm && state->ram_buf_fname)
|
||||
os_unlink(state->ram_buf_fname);
|
||||
|
||||
/* Delete this at the last moment so as not to upset gdb too much */
|
||||
if (state->jumped_fname)
|
||||
os_unlink(state->jumped_fname);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
|
||||
cros_ec: cros-ec {
|
||||
reg = <0 0>;
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
compatible = "google,cros-ec-sandbox";
|
||||
};
|
||||
|
||||
|
|
@ -83,7 +83,7 @@
|
|||
};
|
||||
|
||||
spi: spi@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0>;
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
};
|
||||
|
||||
gpio_a: gpios@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
gpio-controller;
|
||||
compatible = "sandbox,gpio";
|
||||
#gpio-cells = <1>;
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
};
|
||||
|
||||
gpio_b: gpios@1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
gpio-controller;
|
||||
compatible = "sandbox,gpio";
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -120,7 +120,7 @@
|
|||
};
|
||||
|
||||
lcd {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
compatible = "sandbox,lcd-sdl";
|
||||
xres = <1366>;
|
||||
yres = <768>;
|
||||
|
|
@ -209,7 +209,7 @@
|
|||
|
||||
spi@0 {
|
||||
firmware_storage_spi: flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
reg = <0>;
|
||||
compatible = "spansion,m25p16", "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
|
|
@ -248,11 +248,6 @@
|
|||
stringarray = "one";
|
||||
};
|
||||
|
||||
spl-test4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "sandbox,spl-test.2";
|
||||
};
|
||||
|
||||
spl-test5 {
|
||||
u-boot,dm-tpl;
|
||||
compatible = "sandbox,spl-test";
|
||||
|
|
@ -283,7 +278,6 @@
|
|||
};
|
||||
|
||||
tpm {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "google,sandbox-tpm";
|
||||
};
|
||||
|
||||
|
|
@ -420,6 +414,6 @@
|
|||
};
|
||||
|
||||
keyboard-controller {
|
||||
u-boot,dm-pre-reloc;
|
||||
u-boot,dm-pre-proper;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,10 +33,11 @@
|
|||
testfdt6 = "/e-test";
|
||||
testbus3 = "/some-bus";
|
||||
testfdt0 = "/some-bus/c-test@0";
|
||||
testfdt1 = "/some-bus/c-test@1";
|
||||
testfdt12 = "/some-bus/c-test@1";
|
||||
testfdt3 = "/b-test";
|
||||
testfdt5 = "/some-bus/c-test@5";
|
||||
testfdt8 = "/a-test";
|
||||
testfdtm1 = &testfdtm1;
|
||||
fdt-dummy0 = "/translation-test@8000/dev@0,0";
|
||||
fdt-dummy1 = "/translation-test@8000/dev@1,100";
|
||||
fdt-dummy2 = "/translation-test@8000/dev@2,200";
|
||||
|
|
@ -864,13 +865,21 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0 1>;
|
||||
compatible = "sandbox,spi";
|
||||
cs-gpios = <0>, <&gpio_a 0>;
|
||||
cs-gpios = <0>, <0>, <&gpio_a 0>;
|
||||
spi.bin@0 {
|
||||
reg = <0>;
|
||||
compatible = "spansion,m25p16", "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
sandbox,filename = "spi.bin";
|
||||
};
|
||||
spi.bin@1 {
|
||||
reg = <1>;
|
||||
compatible = "spansion,m25p16", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
sandbox,filename = "spi.bin";
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
syscon0: syscon@0 {
|
||||
|
|
@ -917,6 +926,18 @@
|
|||
idle-state = <0xabcd>;
|
||||
};
|
||||
|
||||
testfdtm0 {
|
||||
compatible = "denx,u-boot-fdtm-test";
|
||||
};
|
||||
|
||||
testfdtm1: testfdtm1 {
|
||||
compatible = "denx,u-boot-fdtm-test";
|
||||
};
|
||||
|
||||
testfdtm2 {
|
||||
compatible = "denx,u-boot-fdtm-test";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
compatible = "sandbox,timer";
|
||||
clock-frequency = <1000000>;
|
||||
|
|
|
|||
14
arch/sandbox/include/asm/i2c.h
Normal file
14
arch/sandbox/include/asm/i2c.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2020 Google LLC
|
||||
* Written by Simon Glass <sjg@chromium.org>
|
||||
*/
|
||||
|
||||
#ifndef __asn_i2c_h
|
||||
#define __asn_i2c_h
|
||||
|
||||
struct sandbox_i2c_priv {
|
||||
bool test_mode;
|
||||
};
|
||||
|
||||
#endif /* __asn_i2c_h */
|
||||
30
arch/sandbox/include/asm/serial.h
Normal file
30
arch/sandbox/include/asm/serial.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2020 Google LLC
|
||||
* Written by Simon Glass <sjg@chromium.org>
|
||||
*/
|
||||
|
||||
#ifndef __asm_serial_h
|
||||
#define __asm_serial_h
|
||||
|
||||
#include <dt-structs.h>
|
||||
|
||||
struct sandbox_serial_plat {
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
struct dtd_sandbox_serial dtplat;
|
||||
#endif
|
||||
int colour; /* Text colour to use for output, -1 for none */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct sandbox_serial_priv - Private data for this driver
|
||||
*
|
||||
* @buf: holds input characters available to be read by this driver
|
||||
*/
|
||||
struct sandbox_serial_priv {
|
||||
struct membuff buf;
|
||||
char serial_buf[16];
|
||||
bool start_of_line;
|
||||
};
|
||||
|
||||
#endif /* __asm_serial_h */
|
||||
|
|
@ -32,14 +32,4 @@ struct sandbox_spi_emu_ops {
|
|||
int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes);
|
||||
};
|
||||
|
||||
/*
|
||||
* Extract the bus/cs from the spi spec and return the start of the spi
|
||||
* client spec. If the bus/cs are invalid for the current config, then
|
||||
* it returns NULL.
|
||||
*
|
||||
* Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo"
|
||||
*/
|
||||
const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
|
||||
unsigned long *cs);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user