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armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Priyanka Jain
York Sun
parent
db1e3df7ce
commit
d6fdec211f
@ -180,6 +180,9 @@ config FSL_LSCH2
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config FSL_LSCH3
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bool
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config NXP_LSCH3_2
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bool
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config FSL_MC_ENET
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bool "Management Complex network"
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depends on ARCH_LS2080A || ARCH_LS1088A
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@ -120,6 +120,13 @@ static struct mm_region early_map[] = {
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#ifdef CONFIG_SYS_FSL_DRAM_BASE3
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{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
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CONFIG_SYS_FSL_DRAM_SIZE3,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
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CONFIG_SYS_FSL_CCSR_SIZE,
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@ -266,6 +273,13 @@ static struct mm_region final_map[] = {
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#ifdef CONFIG_SYS_FSL_DRAM_BASE3
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{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
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CONFIG_SYS_FSL_DRAM_SIZE3,
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PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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},
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
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CONFIG_SYS_FSL_BOOTROM_SIZE,
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@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1)
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{
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enum boot_src src = BOOT_SOURCE_RESERVED;
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u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
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#if !defined(CONFIG_FSL_LSCH3_2)
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#if !defined(CONFIG_NXP_LSCH3_2)
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u32 val;
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#endif
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debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
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#if defined(CONFIG_FSL_LSCH3)
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#if defined(CONFIG_FSL_LSCH3_2)
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#if defined(CONFIG_NXP_LSCH3_2)
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switch (rcw_src) {
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case RCW_SRC_SDHC1_VAL:
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src = BOOT_SOURCE_SD_MMC;
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27
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2
Normal file
27
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2
Normal file
@ -0,0 +1,27 @@
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#
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# Copyright 2018 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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NXP LayerScape with Chassis Generation 3.2
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This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
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for example LX2160A.
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This architecture is enhancement over Chassis Generation 3 with
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few differences mentioned below
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1)DDR Layout
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============
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Entire DDR region splits into three regions.
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- Region 1 is at address 0x8000_0000 to 0xffff_ffff.
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- Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
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- Region 3 is at address 0x60_0000_0000 to the top of memory,
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for example 140GB, 0x63_7fff_ffff.
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All DDR memory is marked as cache-enabled.
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2)IFC is removed
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3)Number of I2C controllers increased to 8
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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* Copyright 2017-2018 NXP
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* Copyright 2014-2015, Freescale Semiconductor
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*/
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@ -12,15 +12,19 @@
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
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#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
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#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
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#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
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#endif
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
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#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
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#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
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#endif
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#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
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#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
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@ -40,8 +44,15 @@
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#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
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#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
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#ifdef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
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#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
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#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
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#else
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
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#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
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@ -2,7 +2,7 @@
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/*
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* LayerScape Internal Memory Map
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*
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* Copyright (C) 2017 NXP Semiconductors
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* Copyright 2017-2018 NXP
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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@ -21,7 +21,9 @@
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#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
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#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
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#ifndef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
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#endif
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
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#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
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@ -45,6 +47,12 @@
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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#ifdef CONFIG_NXP_LSCH3_2
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#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
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#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
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#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
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#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
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#endif
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#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
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#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
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#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
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@ -83,7 +91,7 @@
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
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#ifdef CONFIG_TFABOOT
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#ifdef CONFIG_FSL_LSCH3_2
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#ifdef CONFIG_NXP_LSCH3_2
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/* RCW_SRC field in Power-On Reset Control Register 1 */
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#define RCW_SRC_MASK 0x07800000
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#define RCW_SRC_BIT 23
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