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ARM: DRA7: emif: Fix disabling/enabling of refreshes
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that are needed to be set/clear. But emif driver passes the shift of the bits. Fixing it here. Reported-by: Mark Mckeown <m-mckeown@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
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EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
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/* Disable refreshed before leveling */
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/* Disable refreshed before leveling */
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clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
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clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
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EMIF_REG_INITREF_DIS_SHIFT);
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EMIF_REG_INITREF_DIS_MASK);
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/* Start Full leveling */
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/* Start Full leveling */
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writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
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writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
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@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
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}
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}
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/* Enable refreshes after leveling */
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/* Enable refreshes after leveling */
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clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
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clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
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debug("HW leveling success\n");
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debug("HW leveling success\n");
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/*
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/*
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