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ppc/arm: zap EMK boards

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The following bard configurations have been without active maintenance
for a long time, and the board maintainer agrees to have them removed:

MPC5200:	TOP5200, MINI5200, EVAL5200
MPC860:		TOP860
at91sam9xeXXX:	top9000eval_xe, top9000su_xe

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
[trini: Add missing Kconfig removals]
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Wolfgang Denk 2014-10-28 15:44:10 +01:00 committed by Tom Rini
parent 1a929f7ceb
commit d58a9451e7
30 changed files with 3 additions and 2623 deletions
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1
arch/arm/Kconfig
View File

@ -670,7 +670,6 @@ source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/emk/top9000/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"

1
arch/powerpc/cpu/mpc5xxx/Kconfig
View File

@ -120,7 +120,6 @@ source "board/a4m072/Kconfig"
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
source "board/emk/top5200/Kconfig"
source "board/esd/cpci5200/Kconfig"
source "board/esd/mecp5200/Kconfig"
source "board/esd/pf5200/Kconfig"

1
arch/powerpc/cpu/mpc8xx/Kconfig
View File

@ -114,7 +114,6 @@ endchoice
source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/emk/top860/Kconfig"
source "board/esteem192e/Kconfig"
source "board/hermes/Kconfig"
source "board/ip860/Kconfig"

13
board/emk/common/am79c874.c
View File

@ -1,13 +0,0 @@
/*
* (C) Copyright 2003
* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
/*****************************************************************************
* check fiber optic link present, and then copper link present. do auto switch
* between both
*****************************************************************************/

575
board/emk/common/flash.c
View File

@ -1,575 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003
* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined (CONFIG_TOP860)
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFF
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x02aa
#define FLASH_ID1 0
#define FLASH_ID2 1
#define FLASH_ID3 0x0e
#define FLASH_ID4 0x0F
#endif
#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
typedef unsigned char FLASH_PORT_WIDTH;
typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFF
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x0aaa
#define FLASH_CYCLE2 0x0555
#define FLASH_ID1 0
#define FLASH_ID2 2
#define FLASH_ID3 0x1c
#define FLASH_ID4 0x1E
#endif
#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
typedef unsigned char FLASH_PORT_WIDTH;
typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFF
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x02aa
#define FLASH_ID1 0
#define FLASH_ID2 1
#define FLASH_ID3 0x0E
#define FLASH_ID4 0x0F
#endif
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size = 0;
int i = 0;
extern void flash_preinit(void);
extern void flash_afterinit(uint, ulong, ulong);
ulong flashbase = CONFIG_SYS_FLASH_BASE;
flash_preinit();
/* There is only ONE FLASH device */
memset(&flash_info[i], 0, sizeof(flash_info_t));
flash_info[i].size =
flash_get_size((FPW *)flashbase, &flash_info[i]);
size += flash_info[i].size;
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
flash_get_info(CONFIG_ENV_ADDR));
#endif
flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
return size ? size : 1;
}
/*-----------------------------------------------------------------------
*/
static void flash_reset(flash_info_t *info)
{
FPWV *base = (FPWV *)(info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = (FPW)0x00F000F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->size &&
info->start[0] <= base && base <= info->start[0] + info->size - 1)
break;
}
return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
uchar *boottype;
uchar *bootletter;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
uchar topboottype[] = "top boot sector";
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
#if 0
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
#endif
default: printf ("Unknown Vendor "); break;
}
/* check for top or bottom boot, if it applies */
if (info->flash_id & FLASH_BTYPE) {
boottype = botboottype;
bootletter = botbootletter;
}
else {
boottype = topboottype;
bootletter = topbootletter;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM160T:
case FLASH_AM160B:
fmt = "29LV160%s (16 Mbit, %s)\n";
break;
case FLASH_AMLV640U:
fmt = "29LV640M (64 Mbit)\n";
break;
case FLASH_AMDLV065D:
fmt = "29LV065D (64 Mbit)\n";
break;
case FLASH_AMLV256U:
fmt = "29LV256M (256 Mbit)\n";
break;
default:
fmt = "Unknown Chip Type\n";
break;
}
printf (fmt, bootletter, boottype);
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
ulong size;
int erased;
ulong *flash = (unsigned long *) info->start[i];
if ((i % 5) == 0) {
printf ("\n ");
}
/*
* Check if whole sector is erased
*/
size =
(i != (info->sector_count - 1)) ?
(info->start[i + 1] - info->start[i]) >> 2 :
(info->start[0] + info->size - info->start[i]) >> 2;
for (
flash = (unsigned long *) info->start[i], erased = 1;
(flash != (unsigned long *) info->start[i] + size) && erased;
flash++
)
erased = *flash == ~0x0UL;
printf (" %08lX %s %s",
info->start[i],
erased ? "E": " ",
info->protect[i] ? "(RO)" : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (FPWV *addr, flash_info_t *info)
{
int i;
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
/* The manufacturer codes are only 1 byte, so just use 1 byte.
* This works for any bus width and any FLASH device width.
*/
udelay(100);
switch (addr[FLASH_ID1] & 0xff) {
case (uchar)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
#if 0
case (uchar)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
#endif
default:
printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
case (FPW)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
info->start[0] = (ulong)addr;
info->start[1] = (ulong)addr + 0x4000;
info->start[2] = (ulong)addr + 0x6000;
info->start[3] = (ulong)addr + 0x8000;
for (i = 4; i < info->sector_count; i++)
{
info->start[i] = (ulong)addr + 0x10000 * (i-3);
}
break;
case (FPW)AMD_ID_LV065D:
info->flash_id += FLASH_AMDLV065D;
info->sector_count = 128;
info->size = 0x00800000;
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = (ulong)addr + 0x10000 * i;
}
break;
case (FPW)AMD_ID_MIRROR:
/* MIRROR BIT FLASH, read more ID bytes */
if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
{
info->flash_id += FLASH_AMLV640U;
info->sector_count = 128;
info->size = 0x00800000;
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = (ulong)addr + 0x10000 * i;
}
break;
}
if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
{
/* attention: only the first 16 MB will be used in u-boot */
info->flash_id += FLASH_AMLV256U;
info->sector_count = 256;
info->size = 0x01000000;
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = (ulong)addr + 0x10000 * i;
}
break;
}
/* fall thru to here ! */
default:
printf ("unknown AMD device=%x %x %x",
(FPW)addr[FLASH_ID2],
(FPW)addr[FLASH_ID3],
(FPW)addr[FLASH_ID4]);
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0x800000;
break;
}
/* Put FLASH back in read mode */
flash_reset(info);
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
FPWV *addr;
int flag, prot, sect;
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM160B:
case FLASH_AMLV640U:
break;
case FLASH_UNKNOWN:
default:
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
last = get_timer(0);
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
if (info->protect[sect] != 0) /* protected, skip it */
continue;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr = (FPWV *)(info->start[sect]);
if (intel) {
*addr = (FPW)0x00500050; /* clear status register */
*addr = (FPW)0x00200020; /* erase setup */
*addr = (FPW)0x00D000D0; /* erase confirm */
}
else {
/* must be AMD style if not Intel */
FPWV *base; /* first address in bank */
base = (FPWV *)(info->start[0]);
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
*addr = (FPW)0x00300030; /* erase sector */
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer(0);
/* wait at least 50us for AMD, 80us for Intel.
* Let's wait 1 ms.
*/
udelay (1000);
while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
/* suspend erase */
*addr = (FPW)0x00B000B0;
}
flash_reset(info); /* reset to read mode */
rcode = 1; /* failed */
break;
}
/* show that we're waiting */
if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
putc ('.');
last = get_timer(0);
}
}
/* show that we're waiting */
if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
putc ('.');
last = get_timer(0);
}
flash_reset(info); /* reset to read mode */
}
printf (" done\n");
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
int bytes; /* number of bytes to program in current word */
int left; /* number of bytes left to program */
int i, res;
for (left = cnt, res = 0;
left > 0 && res == 0;
addr += sizeof(data), left -= sizeof(data) - bytes) {
bytes = addr & (sizeof(data) - 1);
addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
for (i = 0; i < sizeof(data); i++) {
data <<= 8;
if (i < bytes || i - bytes >= left )
data += *((uchar *)addr + i);
else
data += *src++;
}
/* write one word to the flash */
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
res = write_word_amd(info, (FPWV *)addr, data);
break;
default:
/* unknown flash type, error! */
printf ("missing or unknown FLASH type\n");
res = 1; /* not really a timeout, but gives error */
break;
}
}
return (res);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
{
ulong start;
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (FPWV *)(info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
/* data polling for D7 */
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00F000F0; /* reset bank */
res = 1;
}
}
return (res);
}

63
board/emk/common/vpd.c
View File

@ -1,63 +0,0 @@
/*
* (C) Copyright 2003
* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
/*****************************************************************************
* read "factory" part of EEPROM and set some environment variables
*****************************************************************************/
void read_factory_r (void)
{
/* read 'factory' part of EEPROM */
uchar buf[81];
uchar *p;
uint length;
uint addr;
uint len;
/* get length first */
addr = CONFIG_SYS_FACT_OFFSET;
if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
bailout:
printf ("cannot read factory configuration\n");
printf ("be sure to set ethaddr yourself!\n");
return;
}
length = buf[0] + (buf[1] << 8);
addr += 2;
/* sanity check */
if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
goto bailout;
/* read lines */
while (length > 0) {
/* read one line */
len = length > 80 ? 80 : length;
if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
goto bailout;
/* mark end of buffer */
buf[len] = 0;
/* search end of line */
for (p = buf; *p && *p != 0x0a; p++);
if (!*p)
goto bailout;
*p++ = 0;
/* advance to next line start */
length -= p - buf;
addr += p - buf;
/*printf ("%s\n", buf); */
/* search for our specific entry */
if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
setenv ("ethaddr", (char *)(buf + 19));
} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
setenv ("serial#", (char *)(buf + 15));
} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
setenv ("board_id", (char *)(buf + 13));
}
}
}

12
board/emk/top5200/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_TOP5200
config SYS_BOARD
default "top5200"
config SYS_VENDOR
default "emk"
config SYS_CONFIG_NAME
default "TOP5200"
endif

8
board/emk/top5200/MAINTAINERS
View File

@ -1,8 +0,0 @@
TOP5200 BOARD
M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
S: Maintained
F: board/emk/top5200/
F: include/configs/TOP5200.h
F: configs/EVAL5200_defconfig
F: configs/MINI5200_defconfig
F: configs/TOP5200_defconfig

8
board/emk/top5200/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o

192
board/emk/top5200/top5200.c
View File

@ -1,192 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003
* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
/*****************************************************************************
* initialize SDRAM/DDRAM controller.
* TBD: get data from I2C EEPROM
*****************************************************************************/
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
#if 0
ulong t;
ulong tap_del;
#endif
#define MODE_EN 0x80000000
#define SOFT_PRE 2
#define SOFT_REF 4
/* configure SDRAM start/end */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
#ifdef CONFIG_SYS_DRAM_DDR
/* set extended mode register */
*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
#endif
/* set mode register */
*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
/* set mode register */
*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
/* write default TAP delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
#if 0
for (tap_del = 0; tap_del < 32; tap_del++)
{
*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
for (t = 0; t < 0x04000000; t+=4)
*(vu_long *) t = t;
printf ("Checking DRAM...\n");
for (t = 0; t < 0x04000000; t+=4)
{
ulong rval = *(vu_long *) t;
if (rval != t)
{
printf ("mismatch at %x: ", t);
printf (" 1.read %x", rval);
printf (" 2.read %x", *(vu_long *) t);
printf (" 3.read %x", *(vu_long *) t);
break;
}
}
}
#endif
#endif /* CONFIG_SYS_RAMBOOT */
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
/* return total ram size */
return dramsize;
}
/*****************************************************************************
* print board identification
*****************************************************************************/
int checkboard (void)
{
#if defined (CONFIG_EVAL5200)
puts ("Board: EMK TOP5200 on EVAL5200\n");
#else
#if defined (CONFIG_LITE5200)
puts ("Board: LITE5200\n");
#else
#if defined (CONFIG_MINI5200)
puts ("Board: EMK TOP5200 on MINI5200\n");
#else
puts ("Board: EMK TOP5200\n");
#endif
#endif
#endif
return 0;
}
/*****************************************************************************
* prepare for FLASH detection
*****************************************************************************/
void flash_preinit(void)
{
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
/*****************************************************************************
* finalize FLASH setup
*****************************************************************************/
void flash_afterinit(uint bank, ulong start, ulong size)
{
if (bank == 0) { /* adjust mapping */
*(vu_long *)MPC5XXX_BOOTCS_START =
*(vu_long *)MPC5XXX_CS0_START = START_REG(start);
*(vu_long *)MPC5XXX_BOOTCS_STOP =
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
}
}
/*****************************************************************************
* otherinits after RAM is there and we are relocated to RAM
* note: though this is an int function, nobody cares for the result!
*****************************************************************************/
int misc_init_r (void)
{
#if !defined (CONFIG_LITE5200)
/* read 'factory' part of EEPROM */
extern void read_factory_r (void);
read_factory_r ();
#endif
return (0);
}
/*****************************************************************************
* initialize the PCI system
*****************************************************************************/
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
/*****************************************************************************
* provide the IDE Reset Function
*****************************************************************************/
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif

12
board/emk/top860/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_TOP860
config SYS_BOARD
default "top860"
config SYS_VENDOR
default "emk"
config SYS_CONFIG_NAME
default "TOP860"
endif

6
board/emk/top860/MAINTAINERS
View File

@ -1,6 +0,0 @@
TOP860 BOARD
M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
S: Maintained
F: board/emk/top860/
F: include/configs/TOP860.h
F: configs/TOP860_defconfig

8
board/emk/top860/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o

132
board/emk/top860/top860.c
View File

@ -1,132 +0,0 @@
/*
* (C) Copyright 2003
* EMK Elektronik GmbH <www.emk-elektronik.de>
* Reinhard Meyer <r.meyer@emk-elektronik.de>
*
* Board specific routines for the TOP860
*
* - initialisation
* - interface to VPD data (mac address, clock speeds)
* - memory controller
* - serial io initialisation
* - ethernet io initialisation
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <commproc.h>
#include <mpc8xx.h>
#include <asm/io.h>
/*****************************************************************************
* UPM table for 60ns EDO RAM at 25 MHz bus/external clock
*****************************************************************************/
static const uint edo_60ns_25MHz_tbl[] = {
/* single read (offset 0x00 in upm ram) */
0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
/* burst read (offset 0x08 in upm ram) */
0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
/* single write (offset 0x18 in upm ram) */
0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
/* burst write (offset 0x20 in upm ram) */
0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
/* refresh (offset 0x30 in upm ram) */
0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
/* exception (offset 0x3C in upm ram) */
0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
};
/*****************************************************************************
* Print Board Identity
*****************************************************************************/
int checkboard (void)
{
puts ("Board:"CONFIG_IDENT_STRING"\n");
return (0);
}
/*****************************************************************************
* Initialize DRAM controller
*****************************************************************************/
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/*
* Only initialize memory controller when running from FLASH.
* When running from RAM, don't touch it.
*/
if ((ulong) initdram & 0xff000000) {
volatile uint *addr1, *addr2;
uint i;
upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = 0x0ca20330;
memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
/*
* Do 8 read accesses to DRAM
*/
addr1 = (volatile uint *) 0;
addr2 = (volatile uint *) 0x00400000;
for (i = 0; i < 8; i++)
in_be32(addr1);
/*
* Now check whether we got 4MB or 16MB populated
*/
addr1[0] = 0x12345678;
addr1[1] = 0x9abcdef0;
addr2[0] = 0xfeedc0de;
addr2[1] = 0x47110815;
if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
/* only 4MB populated */
memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
}
}
return -(memctl->memc_or2 & 0xffff0000);
}
/*****************************************************************************
* prepare for FLASH detection
*****************************************************************************/
void flash_preinit(void)
{
}
/*****************************************************************************
* finalize FLASH setup
*****************************************************************************/
void flash_afterinit(uint bank, ulong start, ulong size)
{
}
/*****************************************************************************
* otherinits after RAM is there and we are relocated to RAM
* note: though this is an int function, nobody cares for the result!
*****************************************************************************/
int misc_init_r (void)
{
/* read 'factory' part of EEPROM */
extern void read_factory_r (void);
read_factory_r ();
return (0);
}

115
board/emk/top860/u-boot.lds.debug
View File

@ -1,115 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

18
board/emk/top9000/Kconfig
View File

@ -1,18 +0,0 @@
if TARGET_TOP9000
config SYS_CPU
default "arm926ejs"
config SYS_BOARD
default "top9000"
config SYS_VENDOR
default "emk"
config SYS_SOC
default "at91"
config SYS_CONFIG_NAME
default "top9000"
endif

7
board/emk/top9000/MAINTAINERS
View File

@ -1,7 +0,0 @@
TOP9000 BOARD
M: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
S: Maintained
F: board/emk/top9000/
F: include/configs/top9000.h
F: configs/top9000eval_xe_defconfig
F: configs/top9000su_xe_defconfig

12
board/emk/top9000/Makefile
View File

@ -1,12 +0,0 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010
# Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += top9000.o
obj-$(CONFIG_ATMEL_SPI) += spi.o

44
board/emk/top9000/spi.c
View File

@ -1,44 +0,0 @@
/*
* Copyright (C) 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h>
#include <spi.h>
static const struct {
u32 port;
u32 bit;
} cs_to_portbit[2][4] = {
{{AT91_PIO_PORTA, 3}, {AT91_PIO_PORTC, 11},
{AT91_PIO_PORTC, 16}, {AT91_PIO_PORTC, 17} },
{{AT91_PIO_PORTB, 3}, {AT91_PIO_PORTC, 5},
{AT91_PIO_PORTC, 4}, {AT91_PIO_PORTC, 3} }
};
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs);
if (bus < 2 && cs < 4)
return 1;
return 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs);
at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
cs_to_portbit[slave->bus][slave->cs].bit, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs);
at91_set_pio_output(cs_to_portbit[slave->bus][slave->cs].port,
cs_to_portbit[slave->bus][slave->cs].bit, 1);
}

273
board/emk/top9000/top9000.c
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@ -1,273 +0,0 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <mmc.h>
#include <atmel_mci.h>
#include <i2c.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwn.h>
#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Assign CS3 to NAND/SmartMedia Interface */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable EMAC clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/* Initialize EMAC=MACB hardware */
at91_macb_hw_init();
}
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable MCI clock */
writel(1 << ATMEL_ID_MCI, &pmc->pcer);
/* Initialize MCI hardware */
at91_mci_hw_init();
/* This calls the atmel_mmc_init in gen_atmel_mci.c */
return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
/* this is a weak define that we are overriding */
int board_mmc_getcd(struct mmc *mmc)
{
return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
}
#endif
int board_early_init_f(void)
{
struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/*
* make sure the board can be powered on by
* any transition on WKUP
*/
writel(AT91_SHDW_MR_WKMODE0H2L | AT91_SHDW_MR_WKMODE0L2H,
&shdwn->mr);
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOC),
&pmc->pcer);
/* set SCL0 and SDA0 to open drain */
at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SCL0_PIN, 1);
at91_set_pio_output(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_multi_drive(I2C0_PORT, SDA0_PIN, 1);
at91_set_pio_pullup(I2C0_PORT, SDA0_PIN, 1);
/* set SCL1 and SDA1 to open drain */
at91_set_pio_output(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SCL1_PIN, 1);
at91_set_pio_output(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_multi_drive(I2C1_PORT, SDA1_PIN, 1);
at91_set_pio_pullup(I2C1_PORT, SDA1_PIN, 1);
return 0;
}
int board_init(void)
{
/* arch number of TOP9000 Board */
gd->bd->bi_arch_number = MACH_TYPE_TOP9000;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
nand_hw_init();
#endif
#ifdef CONFIG_MACB
macb_hw_init();
#endif
#ifdef CONFIG_ATMEL_SPI0
/* (n+4) denotes to use nSPISEL(0) in GPIO mode! */
at91_spi0_hw_init(1 << (FRAM_CS_NUM + 4));
#endif
#ifdef CONFIG_ATMEL_SPI1
at91_spi1_hw_init(1 << (ENC_CS_NUM + 4));
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
/* read 'factory' part of EEPROM */
read_factory_r();
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
/*
* Initialize ethernet HW addresses prior to starting Linux,
* needed for nfsroot.
* TODO: We need to investigate if that is really necessary.
*/
eth_init(gd->bd);
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
int num = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0,
(void *)ATMEL_BASE_EMAC0,
CONFIG_SYS_PHY_ID);
if (!rc)
num++;
#endif
#ifdef CONFIG_ENC28J60
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# ifdef CONFIG_ENC28J60_2
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+1,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# ifdef CONFIG_ENC28J60_3
rc = enc28j60_initialize(ENC_SPI_BUS, ENC_CS_NUM+2,
ENC_SPI_CLOCK, SPI_MODE_0);
if (!rc)
num++;
# endif
# endif
#endif
return num;
}
/*
* I2C access functions
*
* Note:
* We need to access Bus 0 before relocation to access the
* environment settings.
* However i2c_get_bus_num() cannot be called before
* relocation.
*/
#ifdef CONFIG_SYS_I2C_SOFT
void iic_init(void)
{
/* ports are now initialized in board_early_init_f() */
}
int iic_read(void)
{
switch (I2C_ADAP_HWNR) {
case 0:
return at91_get_pio_value(I2C0_PORT, SDA0_PIN);
case 1:
return at91_get_pio_value(I2C1_PORT, SDA1_PIN);
}
return 1;
}
void iic_sda(int bit)
{
switch (I2C_ADAP_HWNR) {
case 0:
at91_set_pio_value(I2C0_PORT, SDA0_PIN, bit);
break;
case 1:
at91_set_pio_value(I2C1_PORT, SDA1_PIN, bit);
break;
}
}
void iic_scl(int bit)
{
switch (I2C_ADAP_HWNR) {
case 0:
at91_set_pio_value(I2C0_PORT, SCL0_PIN, bit);
break;
case 1:
at91_set_pio_value(I2C1_PORT, SCL1_PIN, bit);
break;
}
}
#endif

4
configs/EVAL5200_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="EVAL5200"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TOP5200=y

4
configs/MINI5200_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="MINI5200"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TOP5200=y

4
configs/TOP5200_defconfig
View File

@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="TOP5200"
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TOP5200=y

3
configs/TOP860_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_TOP860=y

3
configs/top9000eval_xe_defconfig
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@ -1,3 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="EVAL9000"
CONFIG_ARM=y
CONFIG_TARGET_TOP9000=y

3
configs/top9000su_xe_defconfig
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@ -1,3 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="SU9000"
CONFIG_ARM=y
CONFIG_TARGET_TOP9000=y

3
doc/README.scrapyard
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@ -12,6 +12,9 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de>
TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de>
IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de>

402
include/configs/TOP5200.h
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@ -1,402 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
*
* TOP5200 differences from IceCube:
* 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
* bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
* 1 SDRAM/DDRAM Bank up to 256 MB
* local VPD I2C Bus is software driven and uses
* GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
* FLASH is re-located at 0xff000000
* Internal regs are at 0xf0000000
* Reset jumps to 0x00000100
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
/*
* allowed and functional CONFIG_SYS_TEXT_BASE values:
* 0xff000000 low boot at 0x00000100 (default board setting)
* 0xfff00000 high boot at 0xfff00100 (board needs modification)
* 0x00100000 RAM load and test
*/
#define CONFIG_SYS_TEXT_BASE 0xff000000
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
# define CONFIG_PCI 1
# define CONFIG_PCI_PNP 1
# define CONFIG_PCI_SCAN_SHOW 1
# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
# define CONFIG_PCI_MEM_BUS 0x40000000
# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
# define CONFIG_PCI_MEM_SIZE 0x10000000
# define CONFIG_PCI_IO_BUS 0x50000000
# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
# define CONFIG_PCI_IO_SIZE 0x01000000
#endif
/* USB */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
# define CONFIG_USB_OHCI
# define CONFIG_USB_CLOCK 0x0001bbbb
# if defined (CONFIG_EVAL5200)
# define CONFIG_USB_CONFIG 0x00005100
# else
# define CONFIG_USB_CONFIG 0x00001000
# endif
# define CONFIG_DOS_PARTITION
# define CONFIG_USB_STORAGE
#endif
/* IDE */
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
# define CONFIG_DOS_PARTITION
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO
#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_USB
#define CONFIG_CMD_PCI
#endif
/*
* MUST be low boot - HIGHBOOT is not supported anymore
*/
#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CONFIG_SYS_LOWBOOT 1
# define CONFIG_SYS_LOWBOOT16 1
#else
# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"bootfile=/tftpboot/MPC5200/uImage\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
/*
* EEPROM configuration
*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#if defined(CONFIG_SYS_I2C_SOFT)
# define CONFIG_SYS_I2C
# define CONFIG_SYS_I2C_SOFT_SPEED 100000
# define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
/**/
# define SDA0 0x40
# define SCL0 0x80
# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
# define I2C_READ ((DVI0&SDA0)?1:0)
# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
# define I2C_DELAY {udelay(5);}
# define I2C_ACTIVE {DDR0|=SDA0;}
# define I2C_TRISTATE {DDR0&=~SDA0;}
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_FACT_ADDR 0x57
#endif
#if defined (CONFIG_HARD_I2C)
# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
# define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_FACT_ADDR 0x54
#endif
/*
* Flash configuration, expect one 16 Megabyte Bank at most
*/
#define CONFIG_SYS_FLASH_BASE 0xff000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
/*
* DRAM configuration - will be read from VPD later... TODO!
*/
#if 0
/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
#define CONFIG_SYS_DRAM_DDR 0
#define CONFIG_SYS_DRAM_EMODE 0
#define CONFIG_SYS_DRAM_MODE 0x008D
#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
#define CONFIG_SYS_DRAM_TAP_DEL 0x08
#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
#endif
#if 1
/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
#define CONFIG_SYS_DRAM_DDR 0
#define CONFIG_SYS_DRAM_EMODE 0
#define CONFIG_SYS_DRAM_MODE 0x00CD
#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
#define CONFIG_SYS_DRAM_TAP_DEL 0x08
#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
#endif
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET 0x1000
#define CONFIG_ENV_SIZE 0x0700
/*
* VPD settings
*/
#define CONFIG_SYS_FACT_OFFSET 0x1800
#define CONFIG_SYS_FACT_SIZE 0x0800
/*
* Memory map
*
* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
*/
#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x1f
#define CONFIG_PHY_TYPE 0x79c874
/*
* GPIO configuration:
* PSC1,2,3 predefined as UART
* PCI disabled
* Ethernet 100 with MD
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
#define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
#define RTC(reg) (0xf0010000+reg)
/* setup CS2 for M48T08. Must MAP 64kB */
#define CONFIG_SYS_CS2_START RTC(0)
#define CONFIG_SYS_CS2_SIZE 0x10000
/* setup CS2 configuration register: */
/* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
/* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
#define CONFIG_SYS_CS2_CFG 0x00047800
#else
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG 0x00047801
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#endif /* __CONFIG_H */

409
include/configs/TOP860.h
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@ -1,409 +0,0 @@
/*
* (C) Copyright 2003
* EMK Elektronik GmbH <www.emk-elektronik.de>
* Reinhard Meyer <r.meyer@emk-elektronik.de>
*
* Configuation settings for the TOP860 board.
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* TOP860 is a simple module:
* 16-bit wide FLASH on CS0 (2MB or more)
* 32-bit wide DRAM on CS2 (either 4MB or 16MB)
* FEC with Am79C874 100-Base-T and Fiber Optic
* Ports available, but we choose SMC1 for Console
* 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
* 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
*
* This config has been copied from MBX.h / MBX860T.h
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
/*-----------------------------------------------------------------------
* CPU and BOARD type
*/
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_MPC860T 1 /* even better... an FEC! */
#define CONFIG_TOP860 1 /* ...on a TOP860 module */
#define CONFIG_SYS_TEXT_BASE 0x80000000
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_IDENT_STRING " EMK TOP860"
/*-----------------------------------------------------------------------
* CLOCK settings
*/
#define CONFIG_SYSCLK 49152000
#define CONFIG_SYS_XTAL 32768
#define CONFIG_EBDF 1
#define CONFIG_COM 3
#define CONFIG_RTC_MPC8xx
/*-----------------------------------------------------------------------
* Physical memory map as defined by EMK
*/
#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
/*-----------------------------------------------------------------------
* derived values
*/
#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_CFI
/*-----------------------------------------------------------------------
* Command interpreter
*/
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#define CONFIG_BAUDRATE 9600
/*
* Allow partial commands to be matched to uniqueness.
*/
#define CONFIG_SYS_MATCH_PARTIAL_CMD
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG
#define CONFIG_SOURCE 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
/*-----------------------------------------------------------------------
* Memory Test Command
*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*-----------------------------------------------------------------------
* Environment handler
* only the first 6k in EEPROM are available for user. Of that we use 256b
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET 0x1000
#define CONFIG_ENV_SIZE 0x0700
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_FACT_OFFSET 0x1800
#define CONFIG_SYS_FACT_SIZE 0x0800
#define CONFIG_SYS_I2C_FACT_ADDR 0x57
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 100000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/**/
#define SDA 0x00010
#define SCL 0x00020
#define __I2C_DIR immr->im_cpm.cp_pbdir
#define __I2C_DAT immr->im_cpm.cp_pbdat
#define __I2C_PAR immr->im_cpm.cp_pbpar
#define __I2C_ODR immr->im_cpm.cp_pbodr
#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
__I2C_ODR &= ~(SDA|SCL); \
__I2C_DAT |= (SDA|SCL); \
__I2C_DIR|=(SDA|SCL); }
#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
#define I2C_DELAY { udelay(5); }
#define I2C_ACTIVE { __I2C_DIR |= SDA; }
#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*-----------------------------------------------------------------------
* defines we need to get FEC running
*/
#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
#define FEC_ENET 1 /* eth.c needs it that way... */
#define CONFIG_SYS_DISCOVER_PHY 1
#define CONFIG_MII 1
#define CONFIG_MII_INIT 1
#define CONFIG_PHY_ADDR 31
/*-----------------------------------------------------------------------
* adresses
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/* Interrupt level assignments.
*/
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
/*-----------------------------------------------------------------------
* Debug Enable Register
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_DER 0 /* used in start.S */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* set up PLPRCR (PLL, Low-Power, and Reset Control Register)
* 12 MF calculated Multiplication factor
* 4 0 0000
* 1 SPLSS 0 System PLL lock status sticky
* 1 TEXPS 1 Timer expired status
* 1 0 0
* 1 TMIST 0 Timers interrupt status
* 1 0 0
* 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
* 2 LPM 00 Low-power modes
* 1 CSR 0 Checkstop reset enable
* 1 LOLRE 0 Loss-of-lock reset enable
* 1 FIOPD 0 Force I/O pull down
* 5 0 00000
*/
#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* set up SYPCR:
* 16 SWTC 0xffff Software watchdog timer count
* 8 BMT 0xff Bus monitor timing
* 1 BME 1 Bus monitor enable
* 3 0 000
* 1 SWF 1 Software watchdog freeze
* 1 SWE 0/1 Software watchdog enable
* 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
* 1 SWP 0/1 Software watchdog prescale (1=/2048)
*/
#if defined (CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* set up SIUMCR
* 1 EARB 0 External arbitration
* 3 EARP 000 External arbitration request priority
* 4 0 0000
* 1 DSHW 0 Data show cycles
* 2 DBGC 00 Debug pin configuration
* 2 DBPC 00 Debug port pins configuration
* 1 0 0
* 1 FRC 0 FRZ pin configuration
* 1 DLK 0 Debug register lock
* 1 OPAR 0 Odd parity
* 1 PNCS 0 Parity enable for non memory controller regions
* 1 DPC 0 Data parity pins configuration
* 1 MPRE 0 Multiprocessor reservation enable
* 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
* 1 AEME 0 Async external master enable
* 1 SEME 0 Sync external master enable
* 1 BSC 0 Byte strobe configuration
* 1 GB5E 0 GPL_B5 enable
* 1 B2DD 0 Bank 2 double drive
* 1 B3DD 0 Bank 3 double drive
* 4 0 0000
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* set up SCCR (System Clock and Reset Control Register)
* 1 0 0
* 2 COM 11 Clock output module (00=full, 01=half, 11=off)
* 3 0 000
* 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
* 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
* 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
* 1 CRQEN 0 CPM request enable
* 1 PRQEN 0 Power management request enable
* 2 0 00
* 2 EBDF xx External bus division factor
* 2 0 00
* 2 DFSYNC 00 Division factor for SYNCLK
* 2 DFBRG 00 Division factor for BRGCLK
* 3 DFNL 000 Division factor low frequency
* 3 DFNH 000 Division factor high frequency
* 5 0 00000
*/
#define SCCR_MASK 0
#ifdef CONFIG_EBDF
#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
#else
#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
#endif
/*-----------------------------------------------------------------------
* Chip Select 0 - FLASH
*-----------------------------------------------------------------------
* Preliminary Values
*/
/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
/*-----------------------------------------------------------------------
* misc
*-----------------------------------------------------------------------
*
*/
/*
* Set the autoboot delay in seconds. A delay of -1 disables autoboot
*/
#define CONFIG_BOOTDELAY 5
/*
* Pass the clock frequency to the Linux kernel in units of MHz
*/
#define CONFIG_CLOCKS_IN_MHZ
#define CONFIG_PREBOOT \
"echo;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Set default IP stuff just to get bootstrap entries into the
* environment so that we can source the full default environment.
*/
#define CONFIG_ETHADDR 9a:52:63:15:85:25
#define CONFIG_SERVERIP 10.0.4.200
#define CONFIG_IPADDR 10.0.4.111
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#endif /* __CONFIG_H */

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include/configs/top9000.h
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@ -1,290 +0,0 @@
/*
* (C) Copyright 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* top9000 with at91sam9xe256 or at91sam9xe512
*
* Initial Bootloader is in embedded flash.
* Vital Product Data, U-Boot Environment are in I2C-EEPROM.
* U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
* kernel and file system are either in NAND flash or on a micro SD card.
* NAND flash is optional.
* I2C EEPROM is never optional.
* SPI FRAM is optional.
* SPI ENC28J60 is optional.
* 16 or 32 bit wide SDRAM.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* SoC must be defined first, before hardware.h is included */
#define CONFIG_AT91SAM9XE
#include <asm/hardware.h>
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
*/
#define CONFIG_SYS_TEXT_BASE 0x20000000 /* start of SDRAM */
/* Command line configuration */
#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_ASKENV
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_PROMPT "TOP9000> "
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_AT91RESET_EXTRST /* assert external reset */
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#define CONFIG_BAUDRATE 115200
/* SD/MMC card */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
#define CONFIG_CMD_MMC
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_SYS_PHY_ID 1
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
/* real time clock */
#define CONFIG_RTC_AT91SAM9_RTT
#define CONFIG_CMD_DATE
#if defined(CONFIG_AT91SAM9XE)
/*
* NOR flash - use embedded flash of SAM9XE256/512
* U-Boot will not fit into 128K !
* 2010.09 will not fit into 256K with all options enabled !
*
* Layout:
* 16kB 1st Bootloader
* Rest U-Boot
* the first sector (16kB) of EFLASH cannot be unprotected
* with u-boot commands
*/
# define CONFIG_AT91_EFLASH
# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH
# define CONFIG_SYS_MAX_FLASH_SECT 32
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_FLASH_PROTECTION
# define CONFIG_EFLASH_PROTSECTORS 1 /* protect first sector */
#endif
/* SPI */
#define CONFIG_ATMEL_SPI
#define CONFIG_CMD_SPI
/* RAMTRON FRAM */
#define CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */
#define FRAM_SPI_BUS 0
#define FRAM_CS_NUM 0
#define CONFIG_SPI_FRAM_RAMTRON
#define CONFIG_SF_DEFAULT_SPEED 1000000 /* be conservative here... */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "FM25H20"
/* Microchip ENC28J60 (second LAN) */
#if defined(CONFIG_EVAL9000)
# define CONFIG_ENC28J60
# define CONFIG_ATMEL_SPI1 /* SPI used for ENC28J60 is SPI1 */
# define ENC_SPI_BUS 1
# define ENC_CS_NUM 0
# define ENC_SPI_CLOCK 1000000
#endif /* CONFIG_EVAL9000 */
/*
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000)
#define CONFIG_SYS_LOAD_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x01000000)
/*
* Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
* leaving the correct space for initial global data structure above
* that address while providing maximum stack area below.
*/
#define CONFIG_SYS_INIT_SP_ADDR \
(ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
/*
* NAND flash: 256 MB (optional)
*
* Layout:
* 640kB: u-boot (includes space for spare sectors, handled by
* initial loader)
* 2MB: kernel
* rest: file system
*/
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
#define CONFIG_CMD_NAND
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* I2C support must always be enabled */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 400000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define I2C0_PORT AT91_PIO_PORTA
#define SDA0_PIN 23
#define SCL0_PIN 24
#define I2C1_PORT AT91_PIO_PORTB
#define SDA1_PIN 12
#define SCL1_PIN 13
#define I2C_SOFT_DECLARATIONS void iic_init(void);\
int iic_read(void);\
void iic_sda(int);\
void iic_scl(int);
#define I2C_ACTIVE
#define I2C_TRISTATE
#define I2C_INIT iic_init()
#define I2C_READ iic_read()
#define I2C_SDA(bit) iic_sda(bit)
#define I2C_SCL(bit) iic_scl(bit)
#define I2C_DELAY udelay(3)
/* EEPROM configuration */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
/* later: #define CONFIG_I2C_ENV_EEPROM_BUS 0 */
/* ENV is always in I2C-EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET 0x1000
#define CONFIG_ENV_SIZE 0x0f00
/* VPD settings */
#define CONFIG_SYS_I2C_FACT_ADDR 0x57
#define CONFIG_SYS_FACT_OFFSET 0x1F00
#define CONFIG_SYS_FACT_SIZE 0x0100
/* later: #define CONFIG_MISC_INIT_R */
/* define the next only if you want to allow users to enter VPD data */
#define CONFIG_SYS_FACT_ENTRY
#ifndef __ASSEMBLY__
extern void read_factory_r(void);
#endif
/*
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* add filesystem commands if we have at least 1 storage
* media with filesystem
*/
#if defined(CONFIG_NAND_ATMEL) \
|| defined(CONFIG_USB_ATMEL) \
|| defined(CONFIG_MMC)
# define CONFIG_DOS_PARTITION
# define CONFIG_CMD_FAT
# define CONFIG_CMD_EXT2
/* later: #define CONFIG_CMD_JFFS2 */
#endif
/* add NET commands if we have at least 1 LAN */
#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_MII
/* is this really needed ? */
# define CONFIG_RESET_PHY_R
/* BOOTP options */
# define CONFIG_BOOTP_BOOTFILESIZE
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
#endif
/* linux in NAND flash */
#define CONFIG_BOOTCOUNT_LIMIT 1
#define CONFIG_BOOTCOMMAND \
"nand read 0x21000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 " \
"root=/dev/mtdblock2 " \
"mtdparts=atmel_nand:" \
"640k(uboot)ro," \
"2M(linux)," \
"16M(root)," \
"-(rest) " \
"rw "\
"rootfstype=jffs2"
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
#endif