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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
OMAP24xx I2C: Add support for set-speed
Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Hannes Petermaier
Heiko Schocher
parent
d22643e7e8
commit
d5243359e1
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@ -32,6 +32,10 @@
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* - Status functions now read irqstatus_raw as per TRM guidelines
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* (except for OMAP243X and OMAP34XX).
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* - Driver now supports up to I2C5 (OMAP5).
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*
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* Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
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* - Added support for set_speed
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*
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*/
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#include <common.h>
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@ -53,43 +57,66 @@ static int wait_for_bb(struct i2c_adapter *adap);
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static struct i2c *omap24_get_base(struct i2c_adapter *adap);
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static u16 wait_for_event(struct i2c_adapter *adap);
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static void flush_fifo(struct i2c_adapter *adap);
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static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
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{
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unsigned int sampleclk, prescaler;
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int fsscll, fssclh;
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static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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speed <<= 1;
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prescaler = 0;
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/*
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* some divisors may cause a precission loss, but shouldn't
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* be a big thing, because i2c_clk is then allready very slow.
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*/
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while (prescaler <= 0xFF) {
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sampleclk = I2C_IP_CLK / (prescaler+1);
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fsscll = sampleclk / speed;
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fssclh = fsscll;
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fsscll -= I2C_FASTSPEED_SCLL_TRIM;
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fssclh -= I2C_FASTSPEED_SCLH_TRIM;
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if (((fsscll > 0) && (fssclh > 0)) &&
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((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
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(fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
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if (pscl)
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*pscl = fsscll;
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if (psch)
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*psch = fssclh;
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return prescaler;
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}
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prescaler++;
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}
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return -1;
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}
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static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int psc, fsscll, fssclh;
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int psc, fsscll = 0, fssclh = 0;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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int timeout = I2C_TIMEOUT;
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u32 scll = 0, sclh = 0;
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/* Only handle standard, fast and high speeds */
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if ((speed != OMAP_I2C_STANDARD) &&
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(speed != OMAP_I2C_FAST_MODE) &&
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(speed != OMAP_I2C_HIGH_SPEED)) {
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printf("Error : I2C unsupported speed %d\n", speed);
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return;
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}
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psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
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psc -= 1;
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if (psc < I2C_PSC_MIN) {
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printf("Error : I2C unsupported prescalar %d\n", psc);
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return;
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}
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if (speed == OMAP_I2C_HIGH_SPEED) {
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if (speed >= OMAP_I2C_HIGH_SPEED) {
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/* High speed */
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psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
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psc -= 1;
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if (psc < I2C_PSC_MIN) {
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printf("Error : I2C unsupported prescaler %d\n", psc);
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return -1;
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}
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/* For first phase of HS mode */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
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(2 * OMAP_I2C_FAST_MODE);
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fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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fssclh = fsscll;
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fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
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fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing first phase clock\n");
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return;
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return -1;
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}
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/* For second phase of HS mode */
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@ -100,7 +127,7 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing second phase clock\n");
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return;
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return -1;
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}
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scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
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@ -108,20 +135,29 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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} else {
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/* Standard and fast speed */
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fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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fsscll -= I2C_FASTSPEED_SCLL_TRIM;
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fssclh -= I2C_FASTSPEED_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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psc = omap24_i2c_findpsc(&scll, &sclh, speed);
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if (0 > psc) {
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puts("Error : I2C initializing clock\n");
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return;
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return -1;
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}
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scll = (unsigned int)fsscll;
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sclh = (unsigned int)fssclh;
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}
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adap->speed = speed;
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adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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writew(I2C_CON_EN, &i2c_base->con);
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writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
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return 0;
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}
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static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct i2c *i2c_base = omap24_get_base(adap);
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int timeout = I2C_TIMEOUT;
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if (readw(&i2c_base->con) & I2C_CON_EN) {
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writew(0, &i2c_base->con);
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udelay(50000);
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@ -139,14 +175,14 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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udelay(1000);
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}
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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if (0 != omap24_i2c_setspeed(adap, speed)) {
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printf("ERROR: failed to setup I2C bus-speed!\n");
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return;
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}
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/* own address */
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writew(slaveadd, &i2c_base->oa);
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writew(I2C_CON_EN, &i2c_base->con);
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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/*
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* Have to enable interrupts for OMAP2/3, these IPs don't have
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@ -165,7 +201,8 @@ static void flush_fifo(struct i2c_adapter *adap)
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struct i2c *i2c_base = omap24_get_base(adap);
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u16 stat;
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/* note: if you try and read data when its not there or ready
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/*
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* note: if you try and read data when its not there or ready
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* you get a bus error
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*/
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while (1) {
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@ -220,8 +257,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
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/* Check for ACK (!NAK) */
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if (!(status & I2C_STAT_NACK)) {
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res = 0; /* Device found */
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udelay(I2C_WAIT); /* Required by AM335X in SPL */
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res = 0; /* Device found */
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udelay(adap->waitdelay);/* Required by AM335X in SPL */
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/* Abort transfer (force idle state) */
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writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
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udelay(1000);
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@ -307,7 +344,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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if (status == 0 || (status & I2C_STAT_NACK)) {
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i2c_error = 1;
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printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
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status);
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@ -351,7 +388,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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if (status == 0 || (status & I2C_STAT_NACK)) {
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i2c_error = 1;
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goto rd_exit;
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}
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@ -379,6 +416,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int i;
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u16 status;
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int i2c_error = 0;
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int timeout = I2C_TIMEOUT;
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if (alen < 0) {
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puts("I2C write: addr len < 0\n");
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@ -428,7 +466,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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adap->hwadapnr, status);
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goto wr_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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if (status == 0 || (status & I2C_STAT_NACK)) {
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i2c_error = 1;
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printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
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status);
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@ -448,7 +486,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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/* Address phase is over, now write data */
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for (i = 0; i < len; i++) {
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status = wait_for_event(adap);
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if (status == 0 || status & I2C_STAT_NACK) {
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if (status == 0 || (status & I2C_STAT_NACK)) {
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i2c_error = 1;
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printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
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status);
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@ -464,6 +502,15 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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goto wr_exit;
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}
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}
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/*
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* poll ARDY bit for making sure that last byte really has been
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* transferred on the bus.
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*/
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do {
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status = wait_for_event(adap);
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} while (!(status & I2C_STAT_ARDY) && timeout--);
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if (timeout <= 0)
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printf("i2c_write: timed out writig last byte!\n");
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wr_exit:
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flush_fifo(adap);
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@ -490,7 +537,7 @@ static int wait_for_bb(struct i2c_adapter *adap)
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I2C_STAT_BB) && timeout--) {
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#endif
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writew(stat, &i2c_base->stat);
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udelay(I2C_WAIT);
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udelay(adap->waitdelay);
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}
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if (timeout <= 0) {
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@ -513,7 +560,7 @@ static u16 wait_for_event(struct i2c_adapter *adap)
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int timeout = I2C_TIMEOUT;
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do {
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udelay(I2C_WAIT);
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udelay(adap->waitdelay);
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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status = readw(&i2c_base->stat);
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#else
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@ -580,12 +627,12 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap)
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#endif
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U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
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omap24_i2c_read, omap24_i2c_write, NULL,
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omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
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CONFIG_SYS_OMAP24_I2C_SPEED,
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CONFIG_SYS_OMAP24_I2C_SLAVE,
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0)
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U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
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omap24_i2c_read, omap24_i2c_write, NULL,
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omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
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CONFIG_SYS_OMAP24_I2C_SPEED1,
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CONFIG_SYS_OMAP24_I2C_SLAVE1,
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1)
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@ -68,6 +68,7 @@ struct i2c_adapter {
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uint (*set_bus_speed)(struct i2c_adapter *adap,
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uint speed);
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int speed;
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int waitdelay;
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int slaveaddr;
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int init_done;
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int hwadapnr;
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