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ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -135,6 +135,7 @@
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L2: cache-controller@f8f02000 {
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L2: cache-controller@f8f02000 {
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compatible = "arm,pl310-cache";
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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reg = <0xF8F02000 0x1000>;
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interrupts = <0 2 4>;
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arm,data-latency = <3 2 2>;
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arm,data-latency = <3 2 2>;
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arm,tag-latency = <2 2 2>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-unified;
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