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ARM: zynq: DT: Add missing interrupt for L2 pl310

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Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2015-07-22 11:26:08 +02:00
parent b4e9eaf71f
commit d50cb3d64b
1 changed files with 1 additions and 0 deletions
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arch/arm/dts/zynq-7000.dtsi
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@ -135,6 +135,7 @@
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;