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rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
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432
arch/arm/include/asm/arch-rockchip/cru_px30.h
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432
arch/arm/include/asm/arch-rockchip/cru_px30.h
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@ -0,0 +1,432 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_CRU_PX30_H
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#define _ASM_ARCH_CRU_PX30_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1200 * MHz)
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#define NPLL_HZ (1188 * MHz)
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#define ACLK_BUS_HZ (200 * MHz)
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#define HCLK_BUS_HZ (150 * MHz)
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#define PCLK_BUS_HZ (100 * MHz)
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#define ACLK_PERI_HZ (200 * MHz)
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#define HCLK_PERI_HZ (150 * MHz)
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#define PCLK_PMU_HZ (100 * MHz)
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/* PX30 pll id */
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enum px30_pll_id {
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APLL,
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DPLL,
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CPLL,
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NPLL,
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GPLL,
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PLL_COUNT,
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};
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struct px30_clk_priv {
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struct px30_cru *cru;
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ulong gpll_hz;
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};
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struct px30_pmuclk_priv {
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struct px30_pmucru *pmucru;
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ulong gpll_hz;
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};
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struct px30_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct px30_cru {
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struct px30_pll pll[4];
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unsigned int reserved1[8];
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unsigned int mode;
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unsigned int misc;
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unsigned int reserved2[2];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved3[7];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[60];
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unsigned int reserved6[4];
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unsigned int clkgate_con[18];
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unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[12];
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unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
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unsigned int autocs_con[8];
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};
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check_member(px30_cru, autocs_con[7], 0x41c);
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struct px30_pmucru {
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struct px30_pll pll;
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unsigned int pmu_mode;
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unsigned int reserved1[7];
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unsigned int pmu_clksel_con[6];
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unsigned int reserved2[10];
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unsigned int pmu_clkgate_con[2];
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unsigned int reserved3[14];
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unsigned int pmu_autocs_con[2];
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};
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check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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struct cpu_rate_table {
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unsigned long rate;
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unsigned int aclk_div;
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unsigned int pclk_div;
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};
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_PDSEL_SHIFT = 15,
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PLL_PD1_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* PLLCON2 */
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PLL_FOUT4PHASEPD_SHIFT = 27,
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PLL_FOUTVCOPD_SHIFT = 26,
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PLL_FOUTPOSTDIVPD_SHIFT = 25,
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PLL_DACPD_SHIFT = 24,
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PLL_FRAC_DIV = 0xffffff,
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/* CRU_MODE */
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PLLMUX_FROM_XIN24M = 0,
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PLLMUX_FROM_PLL,
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PLLMUX_FROM_RTC32K,
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USBPHY480M_MODE_SHIFT = 8,
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USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
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NPLL_MODE_SHIFT = 6,
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NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
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CPLL_MODE_SHIFT = 2,
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CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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/* CRU_CLK_SEL0_CON */
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CORE_ACLK_DIV_SHIFT = 12,
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CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL3_CON */
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ACLK_VO_PLL_SHIFT = 6,
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ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT,
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ACLK_VO_SEL_GPLL = 0,
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ACLK_VO_SEL_CPLL,
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ACLK_VO_SEL_NPLL,
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ACLK_VO_DIV_SHIFT = 0,
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ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT,
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/* CRU_CLK_SEL5_CON */
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DCLK_VOPB_SEL_SHIFT = 14,
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DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT,
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DCLK_VOPB_SEL_DIVOUT = 0,
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DCLK_VOPB_SEL_FRACOUT,
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DCLK_VOPB_SEL_24M,
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DCLK_VOPB_PLL_SEL_SHIFT = 11,
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DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
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DCLK_VOPB_PLL_SEL_CPLL = 0,
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DCLK_VOPB_PLL_SEL_NPLL,
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DCLK_VOPB_DIV_SHIFT = 0,
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DCLK_VOPB_DIV_MASK = 0xff,
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/* CRU_CLK_SEL8_CON */
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DCLK_VOPL_SEL_SHIFT = 14,
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DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT,
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DCLK_VOPL_SEL_DIVOUT = 0,
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DCLK_VOPL_SEL_FRACOUT,
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DCLK_VOPL_SEL_24M,
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DCLK_VOPL_PLL_SEL_SHIFT = 11,
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DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
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DCLK_VOPL_PLL_SEL_NPLL = 0,
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DCLK_VOPL_PLL_SEL_CPLL,
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DCLK_VOPL_DIV_SHIFT = 0,
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DCLK_VOPL_DIV_MASK = 0xff,
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/* CRU_CLK_SEL14_CON */
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PERI_PLL_SEL_SHIFT = 15,
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PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_GPLL = 0,
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PERI_PLL_CPLL,
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLKSEL15_CON */
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NANDC_CLK_SEL_SHIFT = 15,
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NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT,
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NANDC_CLK_SEL_NANDC = 0,
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NANDC_CLK_SEL_NANDC_DIV50,
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NANDC_DIV50_SHIFT = 8,
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NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT,
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NANDC_PLL_SHIFT = 6,
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NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT,
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NANDC_SEL_GPLL = 0,
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NANDC_SEL_CPLL,
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NANDC_SEL_NPLL,
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NANDC_DIV_SHIFT = 0,
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NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT,
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/* CRU_CLKSEL20_CON */
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EMMC_PLL_SHIFT = 14,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_GPLL = 0,
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EMMC_SEL_CPLL,
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EMMC_SEL_NPLL,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL21_CON */
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EMMC_CLK_SEL_SHIFT = 15,
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EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
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EMMC_CLK_SEL_EMMC = 0,
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EMMC_CLK_SEL_EMMC_DIV50,
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EMMC_DIV50_SHIFT = 0,
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EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL22_CON */
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GMAC_PLL_SEL_SHIFT = 14,
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GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT,
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GMAC_PLL_SEL_GPLL = 0,
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GMAC_PLL_SEL_CPLL,
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GMAC_PLL_SEL_NPLL,
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CLK_GMAC_DIV_SHIFT = 8,
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CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT,
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SFC_PLL_SEL_SHIFT = 7,
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SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
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SFC_DIV_CON_SHIFT = 0,
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SFC_DIV_CON_MASK = 0x7f,
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/* CRU_CLK_SEL23_CON */
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BUS_PLL_SEL_SHIFT = 15,
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BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT,
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BUS_PLL_SEL_GPLL = 0,
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BUS_PLL_SEL_CPLL,
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BUS_ACLK_DIV_SHIFT = 8,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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RMII_CLK_SEL_SHIFT = 7,
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RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT,
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RMII_CLK_SEL_10M = 0,
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RMII_CLK_SEL_100M,
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RMII_EXTCLK_SEL_SHIFT = 6,
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RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
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RMII_EXTCLK_SEL_INT = 0,
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RMII_EXTCLK_SEL_EXT,
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PCLK_GMAC_DIV_SHIFT = 0,
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PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT,
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/* CRU_CLK_SEL24_CON */
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BUS_PCLK_DIV_SHIFT = 8,
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BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 0,
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BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
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/* CRU_CLK_SEL25_CON */
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CRYPTO_APK_SEL_SHIFT = 14,
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CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
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CRYPTO_PLL_SEL_GPLL = 0,
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CRYPTO_PLL_SEL_CPLL,
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CRYPTO_PLL_SEL_NPLL = 0,
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CRYPTO_APK_DIV_SHIFT = 8,
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CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
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CRYPTO_PLL_SEL_SHIFT = 6,
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CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CRU_CLK_SEL30_CON */
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CLK_I2S1_DIV_CON_MASK = 0x7f,
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CLK_I2S1_PLL_SEL_MASK = 0X1 << 8,
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CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8,
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CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8,
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CLK_I2S1_SEL_MASK = 0x3 << 10,
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CLK_I2S1_SEL_I2S1 = 0x0 << 10,
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CLK_I2S1_SEL_FRAC = 0x1 << 10,
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CLK_I2S1_SEL_MCLK_IN = 0x2 << 10,
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CLK_I2S1_SEL_OSC = 0x3 << 10,
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CLK_I2S1_OUT_SEL_MASK = 0x1 << 15,
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CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15,
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CLK_I2S1_OUT_SEL_OSC = 0x1 << 15,
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/* CRU_CLK_SEL31_CON */
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CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16,
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CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL34_CON */
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UART1_PLL_SEL_SHIFT = 14,
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UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
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UART1_PLL_SEL_GPLL = 0,
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UART1_PLL_SEL_24M,
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UART1_PLL_SEL_480M,
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UART1_PLL_SEL_NPLL,
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UART1_DIV_CON_SHIFT = 0,
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UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT,
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/* CRU_CLK_SEL35_CON */
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UART1_CLK_SEL_SHIFT = 14,
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UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT,
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UART1_CLK_SEL_UART1 = 0,
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UART1_CLK_SEL_UART1_NP5,
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UART1_CLK_SEL_UART1_FRAC,
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UART1_DIVNP5_SHIFT = 0,
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UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT,
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/* CRU_CLK_SEL37_CON */
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UART2_PLL_SEL_SHIFT = 14,
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UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
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UART2_PLL_SEL_GPLL = 0,
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UART2_PLL_SEL_24M,
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UART2_PLL_SEL_480M,
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UART2_PLL_SEL_NPLL,
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UART2_DIV_CON_SHIFT = 0,
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UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT,
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/* CRU_CLK_SEL38_CON */
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UART2_CLK_SEL_SHIFT = 14,
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UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT,
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UART2_CLK_SEL_UART2 = 0,
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UART2_CLK_SEL_UART2_NP5,
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UART2_CLK_SEL_UART2_FRAC,
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UART2_DIVNP5_SHIFT = 0,
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UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
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/* CRU_CLK_SEL46_CON */
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UART5_PLL_SEL_SHIFT = 14,
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UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
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UART5_PLL_SEL_GPLL = 0,
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UART5_PLL_SEL_24M,
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UART5_PLL_SEL_480M,
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UART5_PLL_SEL_NPLL,
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UART5_DIV_CON_SHIFT = 0,
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UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT,
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/* CRU_CLK_SEL47_CON */
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UART5_CLK_SEL_SHIFT = 14,
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UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
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UART5_CLK_SEL_UART5 = 0,
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UART5_CLK_SEL_UART5_NP5,
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UART5_CLK_SEL_UART5_FRAC,
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UART5_DIVNP5_SHIFT = 0,
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UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT,
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/* CRU_CLK_SEL49_CON */
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CLK_I2C_PLL_SEL_GPLL = 0,
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CLK_I2C_PLL_SEL_24M,
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CLK_I2C_DIV_CON_MASK = 0x7f,
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CLK_I2C_PLL_SEL_MASK = 1,
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CLK_I2C1_PLL_SEL_SHIFT = 15,
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CLK_I2C1_DIV_CON_SHIFT = 8,
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CLK_I2C0_PLL_SEL_SHIFT = 7,
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CLK_I2C0_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL50_CON */
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CLK_I2C3_PLL_SEL_SHIFT = 15,
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CLK_I2C3_DIV_CON_SHIFT = 8,
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CLK_I2C2_PLL_SEL_SHIFT = 7,
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CLK_I2C2_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL52_CON */
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CLK_PWM_PLL_SEL_GPLL = 0,
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CLK_PWM_PLL_SEL_24M,
|
||||
CLK_PWM_DIV_CON_MASK = 0x7f,
|
||||
CLK_PWM_PLL_SEL_MASK = 1,
|
||||
CLK_PWM1_PLL_SEL_SHIFT = 15,
|
||||
CLK_PWM1_DIV_CON_SHIFT = 8,
|
||||
CLK_PWM0_PLL_SEL_SHIFT = 7,
|
||||
CLK_PWM0_DIV_CON_SHIFT = 0,
|
||||
|
||||
/* CRU_CLK_SEL53_CON */
|
||||
CLK_SPI_PLL_SEL_GPLL = 0,
|
||||
CLK_SPI_PLL_SEL_24M,
|
||||
CLK_SPI_DIV_CON_MASK = 0x7f,
|
||||
CLK_SPI_PLL_SEL_MASK = 1,
|
||||
CLK_SPI1_PLL_SEL_SHIFT = 15,
|
||||
CLK_SPI1_DIV_CON_SHIFT = 8,
|
||||
CLK_SPI0_PLL_SEL_SHIFT = 7,
|
||||
CLK_SPI0_DIV_CON_SHIFT = 0,
|
||||
|
||||
/* CRU_CLK_SEL55_CON */
|
||||
CLK_SARADC_DIV_CON_SHIFT = 0,
|
||||
CLK_SARADC_DIV_CON_MASK = 0x7ff,
|
||||
|
||||
/* CRU_CLK_GATE10_CON */
|
||||
CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9,
|
||||
CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9,
|
||||
CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9,
|
||||
|
||||
/* CRU_PMU_MODE */
|
||||
GPLL_MODE_SHIFT = 0,
|
||||
GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
|
||||
|
||||
/* CRU_PMU_CLK_SEL0_CON */
|
||||
CLK_PMU_PCLK_DIV_SHIFT = 0,
|
||||
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
|
||||
};
|
||||
#endif
|
@ -3,6 +3,7 @@
|
||||
# Copyright (c) 2017 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ROCKCHIP_PX30) += clk_px30.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
|
||||
|
1630
drivers/clk/rockchip/clk_px30.c
Normal file
1630
drivers/clk/rockchip/clk_px30.c
Normal file
File diff suppressed because it is too large
Load Diff
389
include/dt-bindings/clock/px30-cru.h
Normal file
389
include/dt-bindings/clock/px30-cru.h
Normal file
@ -0,0 +1,389 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_NPLL 4
|
||||
#define APLL_BOOST_H 5
|
||||
#define APLL_BOOST_L 6
|
||||
#define ARMCLK 7
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define USB480M 14
|
||||
#define SCLK_PDM 15
|
||||
#define SCLK_I2S0_TX 16
|
||||
#define SCLK_I2S0_TX_OUT 17
|
||||
#define SCLK_I2S0_RX 18
|
||||
#define SCLK_I2S0_RX_OUT 19
|
||||
#define SCLK_I2S1 20
|
||||
#define SCLK_I2S1_OUT 21
|
||||
#define SCLK_I2S2 22
|
||||
#define SCLK_I2S2_OUT 23
|
||||
#define SCLK_UART1 24
|
||||
#define SCLK_UART2 25
|
||||
#define SCLK_UART3 26
|
||||
#define SCLK_UART4 27
|
||||
#define SCLK_UART5 28
|
||||
#define SCLK_I2C0 29
|
||||
#define SCLK_I2C1 30
|
||||
#define SCLK_I2C2 31
|
||||
#define SCLK_I2C3 32
|
||||
#define SCLK_I2C4 33
|
||||
#define SCLK_PWM0 34
|
||||
#define SCLK_PWM1 35
|
||||
#define SCLK_SPI0 36
|
||||
#define SCLK_SPI1 37
|
||||
#define SCLK_TIMER0 38
|
||||
#define SCLK_TIMER1 39
|
||||
#define SCLK_TIMER2 40
|
||||
#define SCLK_TIMER3 41
|
||||
#define SCLK_TIMER4 42
|
||||
#define SCLK_TIMER5 43
|
||||
#define SCLK_TSADC 44
|
||||
#define SCLK_SARADC 45
|
||||
#define SCLK_OTP 46
|
||||
#define SCLK_OTP_USR 47
|
||||
#define SCLK_CRYPTO 48
|
||||
#define SCLK_CRYPTO_APK 49
|
||||
#define SCLK_DDRC 50
|
||||
#define SCLK_ISP 51
|
||||
#define SCLK_CIF_OUT 52
|
||||
#define SCLK_RGA_CORE 53
|
||||
#define SCLK_VOPB_PWM 54
|
||||
#define SCLK_NANDC 55
|
||||
#define SCLK_SDIO 56
|
||||
#define SCLK_EMMC 57
|
||||
#define SCLK_SFC 58
|
||||
#define SCLK_SDMMC 59
|
||||
#define SCLK_OTG_ADP 60
|
||||
#define SCLK_GMAC_SRC 61
|
||||
#define SCLK_GMAC 62
|
||||
#define SCLK_GMAC_RX_TX 63
|
||||
#define SCLK_MAC_REF 64
|
||||
#define SCLK_MAC_REFOUT 65
|
||||
#define SCLK_MAC_OUT 66
|
||||
#define SCLK_SDMMC_DRV 67
|
||||
#define SCLK_SDMMC_SAMPLE 68
|
||||
#define SCLK_SDIO_DRV 69
|
||||
#define SCLK_SDIO_SAMPLE 70
|
||||
#define SCLK_EMMC_DRV 71
|
||||
#define SCLK_EMMC_SAMPLE 72
|
||||
#define SCLK_GPU 73
|
||||
#define SCLK_PVTM 74
|
||||
#define SCLK_CORE_VPU 75
|
||||
#define SCLK_GMAC_RMII 76
|
||||
#define SCLK_UART2_SRC 77
|
||||
#define SCLK_NANDC_DIV 78
|
||||
#define SCLK_NANDC_DIV50 79
|
||||
#define SCLK_SDIO_DIV 80
|
||||
#define SCLK_SDIO_DIV50 81
|
||||
#define SCLK_EMMC_DIV 82
|
||||
#define SCLK_EMMC_DIV50 83
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOPB 150
|
||||
#define DCLK_VOPL 151
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_GPU 170
|
||||
#define ACLK_BUS_PRE 171
|
||||
#define ACLK_CRYPTO 172
|
||||
#define ACLK_VI_PRE 173
|
||||
#define ACLK_VO_PRE 174
|
||||
#define ACLK_VPU 175
|
||||
#define ACLK_PERI_PRE 176
|
||||
#define ACLK_GMAC 178
|
||||
#define ACLK_CIF 179
|
||||
#define ACLK_ISP 180
|
||||
#define ACLK_VOPB 181
|
||||
#define ACLK_VOPL 182
|
||||
#define ACLK_RGA 183
|
||||
#define ACLK_GIC 184
|
||||
#define ACLK_DCF 186
|
||||
#define ACLK_DMAC 187
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_BUS_PRE 240
|
||||
#define HCLK_CRYPTO 241
|
||||
#define HCLK_VI_PRE 242
|
||||
#define HCLK_VO_PRE 243
|
||||
#define HCLK_VPU 244
|
||||
#define HCLK_PERI_PRE 245
|
||||
#define HCLK_MMC_NAND 246
|
||||
#define HCLK_SDMMC 247
|
||||
#define HCLK_USB 248
|
||||
#define HCLK_CIF 249
|
||||
#define HCLK_ISP 250
|
||||
#define HCLK_VOPB 251
|
||||
#define HCLK_VOPL 252
|
||||
#define HCLK_RGA 253
|
||||
#define HCLK_NANDC 254
|
||||
#define HCLK_SDIO 255
|
||||
#define HCLK_EMMC 256
|
||||
#define HCLK_SFC 257
|
||||
#define HCLK_OTG 258
|
||||
#define HCLK_HOST 259
|
||||
#define HCLK_HOST_ARB 260
|
||||
#define HCLK_PDM 261
|
||||
#define HCLK_I2S0 262
|
||||
#define HCLK_I2S1 263
|
||||
#define HCLK_I2S2 264
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_BUS_PRE 320
|
||||
#define PCLK_DDR 321
|
||||
#define PCLK_VO_PRE 322
|
||||
#define PCLK_GMAC 323
|
||||
#define PCLK_MIPI_DSI 324
|
||||
#define PCLK_MIPIDSIPHY 325
|
||||
#define PCLK_MIPICSIPHY 326
|
||||
#define PCLK_USB_GRF 327
|
||||
#define PCLK_DCF 328
|
||||
#define PCLK_UART1 329
|
||||
#define PCLK_UART2 330
|
||||
#define PCLK_UART3 331
|
||||
#define PCLK_UART4 332
|
||||
#define PCLK_UART5 333
|
||||
#define PCLK_I2C0 334
|
||||
#define PCLK_I2C1 335
|
||||
#define PCLK_I2C2 336
|
||||
#define PCLK_I2C3 337
|
||||
#define PCLK_I2C4 338
|
||||
#define PCLK_PWM0 339
|
||||
#define PCLK_PWM1 340
|
||||
#define PCLK_SPI0 341
|
||||
#define PCLK_SPI1 342
|
||||
#define PCLK_SARADC 343
|
||||
#define PCLK_TSADC 344
|
||||
#define PCLK_TIMER 345
|
||||
#define PCLK_OTP_NS 346
|
||||
#define PCLK_WDT_NS 347
|
||||
#define PCLK_GPIO1 348
|
||||
#define PCLK_GPIO2 349
|
||||
#define PCLK_GPIO3 350
|
||||
#define PCLK_ISP 351
|
||||
#define PCLK_CIF 352
|
||||
#define PCLK_OTP_PHY 353
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
|
||||
|
||||
/* pmu-clocks indices */
|
||||
|
||||
#define PLL_GPLL 1
|
||||
|
||||
#define SCLK_RTC32K_PMU 4
|
||||
#define SCLK_WIFI_PMU 5
|
||||
#define SCLK_UART0_PMU 6
|
||||
#define SCLK_PVTM_PMU 7
|
||||
#define PCLK_PMU_PRE 8
|
||||
#define SCLK_REF24M_PMU 9
|
||||
#define SCLK_USBPHY_REF 10
|
||||
#define SCLK_MIPIDSIPHY_REF 11
|
||||
|
||||
#define XIN24M_DIV 12
|
||||
|
||||
#define PCLK_GPIO0_PMU 20
|
||||
#define PCLK_UART0_PMU 21
|
||||
|
||||
#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_CORE_NOC 13
|
||||
#define SRST_STRC_A 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_DAP 16
|
||||
#define SRST_CORE_PVTM 17
|
||||
#define SRST_GPU 18
|
||||
#define SRST_GPU_NIU 19
|
||||
#define SRST_UPCTL2 20
|
||||
#define SRST_UPCTL2_A 21
|
||||
#define SRST_UPCTL2_P 22
|
||||
#define SRST_MSCH 23
|
||||
#define SRST_MSCH_P 24
|
||||
#define SRST_DDRMON_P 25
|
||||
#define SRST_DDRSTDBY_P 26
|
||||
#define SRST_DDRSTDBY 27
|
||||
#define SRST_DDRGRF_p 28
|
||||
#define SRST_AXI_SPLIT_A 29
|
||||
#define SRST_AXI_CMD_A 30
|
||||
#define SRST_AXI_CMD_P 31
|
||||
|
||||
#define SRST_DDRPHY 32
|
||||
#define SRST_DDRPHYDIV 33
|
||||
#define SRST_DDRPHY_P 34
|
||||
#define SRST_VPU_A 36
|
||||
#define SRST_VPU_NIU_A 37
|
||||
#define SRST_VPU_H 38
|
||||
#define SRST_VPU_NIU_H 39
|
||||
#define SRST_VI_NIU_A 40
|
||||
#define SRST_VI_NIU_H 41
|
||||
#define SRST_ISP_H 42
|
||||
#define SRST_ISP 43
|
||||
#define SRST_CIF_A 44
|
||||
#define SRST_CIF_H 45
|
||||
#define SRST_CIF_PCLKIN 46
|
||||
#define SRST_MIPICSIPHY_P 47
|
||||
|
||||
#define SRST_VO_NIU_A 48
|
||||
#define SRST_VO_NIU_H 49
|
||||
#define SRST_VO_NIU_P 50
|
||||
#define SRST_VOPB_A 51
|
||||
#define SRST_VOPB_H 52
|
||||
#define SRST_VOPB 53
|
||||
#define SRST_PWM_VOPB 54
|
||||
#define SRST_VOPL_A 55
|
||||
#define SRST_VOPL_H 56
|
||||
#define SRST_VOPL 57
|
||||
#define SRST_RGA_A 58
|
||||
#define SRST_RGA_H 59
|
||||
#define SRST_RGA 60
|
||||
#define SRST_MIPIDSI_HOST_P 61
|
||||
#define SRST_MIPIDSIPHY_P 62
|
||||
#define SRST_VPU_CORE 63
|
||||
|
||||
#define SRST_PERI_NIU_A 64
|
||||
#define SRST_USB_NIU_H 65
|
||||
#define SRST_USB2OTG_H 66
|
||||
#define SRST_USB2OTG 67
|
||||
#define SRST_USB2OTG_ADP 68
|
||||
#define SRST_USB2HOST_H 69
|
||||
#define SRST_USB2HOST_ARB_H 70
|
||||
#define SRST_USB2HOST_AUX_H 71
|
||||
#define SRST_USB2HOST_EHCI 72
|
||||
#define SRST_USB2HOST 73
|
||||
#define SRST_USBPHYPOR 74
|
||||
#define SRST_USBPHY_OTG_PORT 75
|
||||
#define SRST_USBPHY_HOST_PORT 76
|
||||
#define SRST_USBPHY_GRF 77
|
||||
#define SRST_CPU_BOOST_P 78
|
||||
#define SRST_CPU_BOOST 79
|
||||
|
||||
#define SRST_MMC_NAND_NIU_H 80
|
||||
#define SRST_SDIO_H 81
|
||||
#define SRST_EMMC_H 82
|
||||
#define SRST_SFC_H 83
|
||||
#define SRST_SFC 84
|
||||
#define SRST_SDCARD_NIU_H 85
|
||||
#define SRST_SDMMC_H 86
|
||||
#define SRST_NANDC_H 89
|
||||
#define SRST_NANDC 90
|
||||
#define SRST_GMAC_NIU_A 92
|
||||
#define SRST_GMAC_NIU_P 93
|
||||
#define SRST_GMAC_A 94
|
||||
|
||||
#define SRST_PMU_NIU_P 96
|
||||
#define SRST_PMU_SGRF_P 97
|
||||
#define SRST_PMU_GRF_P 98
|
||||
#define SRST_PMU 99
|
||||
#define SRST_PMU_MEM_P 100
|
||||
#define SRST_PMU_GPIO0_P 101
|
||||
#define SRST_PMU_UART0_P 102
|
||||
#define SRST_PMU_CRU_P 103
|
||||
#define SRST_PMU_PVTM 104
|
||||
#define SRST_PMU_UART 105
|
||||
#define SRST_PMU_NIU_H 106
|
||||
#define SRST_PMU_DDR_FAIL_SAVE 107
|
||||
#define SRST_PMU_CORE_PERF_A 108
|
||||
#define SRST_PMU_CORE_GRF_P 109
|
||||
#define SRST_PMU_GPU_PERF_A 110
|
||||
#define SRST_PMU_GPU_GRF_P 111
|
||||
|
||||
#define SRST_CRYPTO_NIU_A 112
|
||||
#define SRST_CRYPTO_NIU_H 113
|
||||
#define SRST_CRYPTO_A 114
|
||||
#define SRST_CRYPTO_H 115
|
||||
#define SRST_CRYPTO 116
|
||||
#define SRST_CRYPTO_APK 117
|
||||
#define SRST_BUS_NIU_H 120
|
||||
#define SRST_USB_NIU_P 121
|
||||
#define SRST_BUS_TOP_NIU_P 122
|
||||
#define SRST_INTMEM_A 123
|
||||
#define SRST_GIC_A 124
|
||||
#define SRST_ROM_H 126
|
||||
#define SRST_DCF_A 127
|
||||
|
||||
#define SRST_DCF_P 128
|
||||
#define SRST_PDM_H 129
|
||||
#define SRST_PDM 130
|
||||
#define SRST_I2S0_H 131
|
||||
#define SRST_I2S0_TX 132
|
||||
#define SRST_I2S1_H 133
|
||||
#define SRST_I2S1 134
|
||||
#define SRST_I2S2_H 135
|
||||
#define SRST_I2S2 136
|
||||
#define SRST_UART1_P 137
|
||||
#define SRST_UART1 138
|
||||
#define SRST_UART2_P 139
|
||||
#define SRST_UART2 140
|
||||
#define SRST_UART3_P 141
|
||||
#define SRST_UART3 142
|
||||
#define SRST_UART4_P 143
|
||||
|
||||
#define SRST_UART4 144
|
||||
#define SRST_UART5_P 145
|
||||
#define SRST_UART5 146
|
||||
#define SRST_I2C0_P 147
|
||||
#define SRST_I2C0 148
|
||||
#define SRST_I2C1_P 149
|
||||
#define SRST_I2C1 150
|
||||
#define SRST_I2C2_P 151
|
||||
#define SRST_I2C2 152
|
||||
#define SRST_I2C3_P 153
|
||||
#define SRST_I2C3 154
|
||||
#define SRST_PWM0_P 157
|
||||
#define SRST_PWM0 158
|
||||
#define SRST_PWM1_P 159
|
||||
|
||||
#define SRST_PWM1 160
|
||||
#define SRST_SPI0_P 161
|
||||
#define SRST_SPI0 162
|
||||
#define SRST_SPI1_P 163
|
||||
#define SRST_SPI1 164
|
||||
#define SRST_SARADC_P 165
|
||||
#define SRST_SARADC 166
|
||||
#define SRST_TSADC_P 167
|
||||
#define SRST_TSADC 168
|
||||
#define SRST_TIMER_P 169
|
||||
#define SRST_TIMER0 170
|
||||
#define SRST_TIMER1 171
|
||||
#define SRST_TIMER2 172
|
||||
#define SRST_TIMER3 173
|
||||
#define SRST_TIMER4 174
|
||||
#define SRST_TIMER5 175
|
||||
|
||||
#define SRST_OTP_NS_P 176
|
||||
#define SRST_OTP_NS_SBPI 177
|
||||
#define SRST_OTP_NS_USR 178
|
||||
#define SRST_OTP_PHY_P 179
|
||||
#define SRST_OTP_PHY 180
|
||||
#define SRST_WDT_NS_P 181
|
||||
#define SRST_GPIO1_P 182
|
||||
#define SRST_GPIO2_P 183
|
||||
#define SRST_GPIO3_P 184
|
||||
#define SRST_SGRF_P 185
|
||||
#define SRST_GRF_P 186
|
||||
#define SRST_I2S0_RX 191
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user