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am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
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318f27c98f
commit
d4898ea896
@ -46,6 +46,8 @@ void config_sdram(const struct emif_regs *regs)
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{
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{
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
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if (regs->zq_config)
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writel(regs->zq_config, &emif_reg->emif_zq_config);
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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}
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}
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@ -87,6 +87,38 @@ static const struct emif_regs ddr2_emif_reg_data = {
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.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
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.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
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};
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};
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = DDR3_RD_DQS,
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.datawdsratio0 = DDR3_WR_DQS,
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.datafwsratio0 = DDR3_PHY_FIFO_WE,
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.datawrsratio0 = DDR3_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = DDR3_RATIO,
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.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd0iclkout = DDR3_INVERT_CLKOUT,
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.cmd1csratio = DDR3_RATIO,
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.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd1iclkout = DDR3_INVERT_CLKOUT,
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.cmd2csratio = DDR3_RATIO,
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.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd2iclkout = DDR3_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = DDR3_EMIF_SDCFG,
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.ref_ctrl = DDR3_EMIF_SDREF,
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.sdram_tim1 = DDR3_EMIF_TIM1,
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.sdram_tim2 = DDR3_EMIF_TIM2,
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.sdram_tim3 = DDR3_EMIF_TIM3,
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.zq_config = DDR3_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
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};
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static void config_vtp(void)
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static void config_vtp(void)
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{
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{
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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@ -115,6 +147,15 @@ void config_ddr(short ddr_type)
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ddr_data = &ddr2_data;
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ddr_data = &ddr2_data;
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ioctrl_val = DDR2_IOCTRL_VALUE;
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ioctrl_val = DDR2_IOCTRL_VALUE;
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emif_regs = &ddr2_emif_reg_data;
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emif_regs = &ddr2_emif_reg_data;
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} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
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ddr_pll = 303;
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cmd_ctrl_data = &ddr3_cmd_ctrl_data;
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ddr_data = &ddr3_data;
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ioctrl_val = DDR3_IOCTRL_VALUE;
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emif_regs = &ddr3_emif_reg_data;
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} else {
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puts("Unknown memory type");
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hang();
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}
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}
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enable_emif_clocks();
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enable_emif_clocks();
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@ -47,6 +47,23 @@
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#define DDR2_PHY_RANK0_DELAY 0x1
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#define DDR2_PHY_RANK0_DELAY 0x1
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#define DDR2_IOCTRL_VALUE 0x18B
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#define DDR2_IOCTRL_VALUE 0x18B
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/* Micron MT41J128M16JT-125 */
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#define DDR3_EMIF_READ_LATENCY 0x06
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#define DDR3_EMIF_TIM1 0x0888A39B
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#define DDR3_EMIF_TIM2 0x26337FDA
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#define DDR3_EMIF_TIM3 0x501F830F
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#define DDR3_EMIF_SDCFG 0x61C04AB2
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#define DDR3_EMIF_SDREF 0x0000093B
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#define DDR3_ZQ_CFG 0x50074BE4
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#define DDR3_DLL_LOCK_DIFF 0x1
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#define DDR3_RATIO 0x40
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#define DDR3_INVERT_CLKOUT 0x1
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#define DDR3_RD_DQS 0x3B
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#define DDR3_WR_DQS 0x85
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#define DDR3_PHY_WR_DATA 0xC1
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#define DDR3_PHY_FIFO_WE 0x100
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#define DDR3_IOCTRL_VALUE 0x18B
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/**
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/**
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* Configure SDRAM
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* Configure SDRAM
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*/
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*/
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