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https://github.com/brain-hackers/u-boot-brain
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x86: fsp: Adjust calculations for MTRR range and DRAM top
At present the top of available DRAM is the same as the top of the range of the low-memory MTRR. In fact, U-Boot is allowed to use memory up until the start of the FSP reserved memory. Use that value for low_end, since it makes more memory available. Keep the same calculation as before for mtrr_top, i.e. the top of reserved memory. A side-effect of this change is that the E820 tables have a single entry that extends from the bottom of the memory used by U-Boot to the bottom of the FSP reserved memory. This includes the bloblist, if ACPI tables are placed there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -41,8 +41,10 @@ int fsp_scan_for_ram_size(void)
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int dram_init_banksize(void)
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int dram_init_banksize(void)
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{
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{
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efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
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const struct hob_header *hdr;
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const struct hob_header *hdr;
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struct hob_res_desc *res_desc;
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struct hob_res_desc *res_desc;
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phys_addr_t mtrr_top;
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phys_addr_t low_end;
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phys_addr_t low_end;
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uint bank;
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uint bank;
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@ -54,35 +56,42 @@ int dram_init_banksize(void)
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return 0;
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return 0;
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}
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}
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low_end = 0;
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low_end = 0; /* top of low memory usable by U-Boot */
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mtrr_top = 0; /* top of low memory (even if reserved) */
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for (bank = 1, hdr = gd->arch.hob_list;
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for (bank = 1, hdr = gd->arch.hob_list;
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bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
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bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
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hdr = get_next_hob(hdr)) {
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hdr = get_next_hob(hdr)) {
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if (hdr->type != HOB_TYPE_RES_DESC)
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if (hdr->type != HOB_TYPE_RES_DESC)
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continue;
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continue;
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res_desc = (struct hob_res_desc *)hdr;
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res_desc = (struct hob_res_desc *)hdr;
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if (!guidcmp(&res_desc->owner, &fsp))
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low_end = res_desc->phys_start;
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if (res_desc->type != RES_SYS_MEM &&
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if (res_desc->type != RES_SYS_MEM &&
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res_desc->type != RES_MEM_RESERVED)
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res_desc->type != RES_MEM_RESERVED)
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continue;
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continue;
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if (res_desc->phys_start < (1ULL << 32)) {
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if (res_desc->phys_start < (1ULL << 32)) {
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low_end = max(low_end,
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mtrr_top = max(mtrr_top,
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res_desc->phys_start + res_desc->len);
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res_desc->phys_start + res_desc->len);
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continue;
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} else {
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gd->bd->bi_dram[bank].start = res_desc->phys_start;
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gd->bd->bi_dram[bank].size = res_desc->len;
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mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
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res_desc->len);
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log_debug("ram %llx %llx\n",
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gd->bd->bi_dram[bank].start,
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gd->bd->bi_dram[bank].size);
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}
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}
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gd->bd->bi_dram[bank].start = res_desc->phys_start;
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gd->bd->bi_dram[bank].size = res_desc->len;
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mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
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res_desc->len);
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log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
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gd->bd->bi_dram[bank].size);
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}
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}
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/* Add the memory below 4GB */
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/* Add the memory below 4GB */
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = low_end;
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gd->bd->bi_dram[0].size = low_end;
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
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/*
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* Set up an MTRR to the top of low, reserved memory. This is necessary
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* for graphics to run at full speed in U-Boot.
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*/
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
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return 0;
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return 0;
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}
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}
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@ -156,7 +165,7 @@ unsigned int install_e820_map(unsigned int max_entries,
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#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
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#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
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int handoff_arch_save(struct spl_handoff *ho)
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int handoff_arch_save(struct spl_handoff *ho)
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{
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{
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ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
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ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
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ho->arch.hob_list = gd->arch.hob_list;
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ho->arch.hob_list = gd->arch.hob_list;
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return 0;
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return 0;
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