mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 17:10:42 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
commit
d459516188
2
MAKEALL
2
MAKEALL
@ -320,7 +320,7 @@ LIST_8260=" \
|
|||||||
|
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||||||
LIST_83xx=" \
|
LIST_83xx=" \
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||||||
MPC8313ERDB_33 \
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MPC8313ERDB_33 \
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||||||
MPC8313ERDB_66 \
|
MPC8313ERDB_NAND_66 \
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||||||
MPC8315ERDB \
|
MPC8315ERDB \
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||||||
MPC8323ERDB \
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MPC8323ERDB \
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||||||
MPC832XEMDS \
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MPC832XEMDS \
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||||||
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3
Makefile
3
Makefile
@ -2083,6 +2083,9 @@ MPC8313ERDB_NAND_66_config: unconfig
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|||||||
echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
|
echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
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||||||
fi ;
|
fi ;
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||||||
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
|
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
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||||||
|
@if [ "$(findstring _NAND_,$@)" ] ; then \
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||||||
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echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
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||||||
|
fi ;
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||||||
|
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||||||
MPC8315ERDB_config: unconfig
|
MPC8315ERDB_config: unconfig
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||||||
@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
|
@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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||||||
|
@ -167,6 +167,10 @@ void cpu_init_f (volatile immap_t * im)
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gd->reset_status = im->reset.rsr;
|
gd->reset_status = im->reset.rsr;
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im->reset.rsr = ~(RSR_RES);
|
im->reset.rsr = ~(RSR_RES);
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|
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|
/* AER - Arbiter Event Register - store status */
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|
gd->arbiter_event_attributes = im->arbiter.aeatr;
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|
gd->arbiter_event_address = im->arbiter.aeadr;
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||||||
|
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||||||
/*
|
/*
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||||||
* RMR - Reset Mode Register
|
* RMR - Reset Mode Register
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||||||
* contains checkstop reset enable (4.6.1.4)
|
* contains checkstop reset enable (4.6.1.4)
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@ -283,12 +287,12 @@ void cpu_init_f (volatile immap_t * im)
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im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
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im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
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#endif
|
#endif
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||||||
#ifdef CFG_GPIO1_PRELIM
|
#ifdef CFG_GPIO1_PRELIM
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im->gpio[0].dir = CFG_GPIO1_DIR;
|
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||||||
im->gpio[0].dat = CFG_GPIO1_DAT;
|
im->gpio[0].dat = CFG_GPIO1_DAT;
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|
im->gpio[0].dir = CFG_GPIO1_DIR;
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||||||
#endif
|
#endif
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||||||
#ifdef CFG_GPIO2_PRELIM
|
#ifdef CFG_GPIO2_PRELIM
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||||||
im->gpio[1].dir = CFG_GPIO2_DIR;
|
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||||||
im->gpio[1].dat = CFG_GPIO2_DAT;
|
im->gpio[1].dat = CFG_GPIO2_DAT;
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|
im->gpio[1].dir = CFG_GPIO2_DIR;
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||||||
#endif
|
#endif
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||||||
}
|
}
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|
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||||||
@ -302,6 +306,130 @@ int cpu_init_r (void)
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return 0;
|
return 0;
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||||||
}
|
}
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||||||
|
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||||||
|
/*
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|
* Print out the bus arbiter event
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|
*/
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|
#if defined(CONFIG_DISPLAY_AER_FULL)
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|
static int print_83xx_arb_event(int force)
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|
{
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|
static char* event[] = {
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||||||
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"Address Time Out",
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||||||
|
"Data Time Out",
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|
"Address Only Transfer Type",
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||||||
|
"External Control Word Transfer Type",
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||||||
|
"Reserved Transfer Type",
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||||||
|
"Transfer Error",
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||||||
|
"reserved",
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||||||
|
"reserved"
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||||||
|
};
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||||||
|
static char* master[] = {
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"e300 Core Data Transaction",
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|
"reserved",
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||||||
|
"e300 Core Instruction Fetch",
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|
"reserved",
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||||||
|
"TSEC1",
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||||||
|
"TSEC2",
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|
"USB MPH",
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||||||
|
"USB DR",
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||||||
|
"Encryption Core",
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||||||
|
"I2C Boot Sequencer",
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||||||
|
"JTAG",
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||||||
|
"reserved",
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||||||
|
"eSDHC",
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||||||
|
"PCI1",
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||||||
|
"PCI2",
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||||||
|
"DMA",
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||||||
|
"QUICC Engine 00",
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||||||
|
"QUICC Engine 01",
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||||||
|
"QUICC Engine 10",
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||||||
|
"QUICC Engine 11",
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||||||
|
"reserved",
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||||||
|
"reserved",
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||||||
|
"reserved",
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||||||
|
"reserved",
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||||||
|
"SATA1",
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||||||
|
"SATA2",
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||||||
|
"SATA3",
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||||||
|
"SATA4",
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||||||
|
"reserved",
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||||||
|
"PCI Express 1",
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||||||
|
"PCI Express 2",
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||||||
|
"TDM-DMAC"
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||||||
|
};
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||||||
|
static char *transfer[] = {
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||||||
|
"Address-only, Clean Block",
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||||||
|
"Address-only, lwarx reservation set",
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||||||
|
"Single-beat or Burst write",
|
||||||
|
"reserved",
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||||||
|
"Address-only, Flush Block",
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||||||
|
"reserved",
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||||||
|
"Burst write",
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||||||
|
"reserved",
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"Address-only, sync",
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"Address-only, tlbsync",
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|
"Single-beat or Burst read",
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|
"Single-beat or Burst read",
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"Address-only, Kill Block",
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"Address-only, icbi",
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||||||
|
"Burst read",
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||||||
|
"reserved",
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||||||
|
"Address-only, eieio",
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||||||
|
"reserved",
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||||||
|
"Single-beat write",
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||||||
|
"reserved",
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||||||
|
"ecowx - Illegal single-beat write",
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||||||
|
"reserved",
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||||||
|
"reserved",
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||||||
|
"reserved",
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||||||
|
"Address-only, TLB Invalidate",
|
||||||
|
"reserved",
|
||||||
|
"Single-beat or Burst read",
|
||||||
|
"reserved",
|
||||||
|
"eciwx - Illegal single-beat read",
|
||||||
|
"reserved",
|
||||||
|
"Burst read",
|
||||||
|
"reserved"
|
||||||
|
};
|
||||||
|
|
||||||
|
int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
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||||||
|
>> AEATR_EVENT_SHIFT;
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||||||
|
int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
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||||||
|
>> AEATR_MSTR_ID_SHIFT;
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||||||
|
int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
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||||||
|
>> AEATR_TBST_SHIFT;
|
||||||
|
int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
|
||||||
|
>> AEATR_TSIZE_SHIFT;
|
||||||
|
int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
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||||||
|
>> AEATR_TTYPE_SHIFT;
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||||||
|
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||||||
|
if (!force && !gd->arbiter_event_address)
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||||||
|
return 0;
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||||||
|
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||||||
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puts("Arbiter Event Status:\n");
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||||||
|
printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
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||||||
|
printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
|
||||||
|
printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
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||||||
|
printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
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||||||
|
tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
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||||||
|
printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
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||||||
|
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||||||
|
return gd->arbiter_event_address;
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||||||
|
}
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||||||
|
|
||||||
|
#elif defined(CONFIG_DISPLAY_AER_BRIEF)
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||||||
|
|
||||||
|
static int print_83xx_arb_event(int force)
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||||||
|
{
|
||||||
|
if (!force && !gd->arbiter_event_address)
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||||||
|
return 0;
|
||||||
|
|
||||||
|
printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
|
||||||
|
gd->arbiter_event_attributes, gd->arbiter_event_address);
|
||||||
|
|
||||||
|
return gd->arbiter_event_address;
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_DISPLAY_AER_xxxx */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Figure out the cause of the reset
|
* Figure out the cause of the reset
|
||||||
*/
|
*/
|
||||||
@ -334,6 +462,12 @@ int prt_83xx_rsr(void)
|
|||||||
printf("%s%s", sep, bits[i].desc);
|
printf("%s%s", sep, bits[i].desc);
|
||||||
sep = ", ";
|
sep = ", ";
|
||||||
}
|
}
|
||||||
puts("\n\n");
|
puts("\n");
|
||||||
|
|
||||||
|
#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
|
||||||
|
print_83xx_arb_event(rsr & RSR_BMRS);
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||||||
|
#endif
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -208,7 +208,7 @@ in_flash:
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|||||||
bl enable_addr_trans
|
bl enable_addr_trans
|
||||||
sync
|
sync
|
||||||
|
|
||||||
/* enable and invalidate the data cache */
|
/* enable the data cache */
|
||||||
bl dcache_enable
|
bl dcache_enable
|
||||||
sync
|
sync
|
||||||
#ifdef CFG_INIT_RAM_LOCK
|
#ifdef CFG_INIT_RAM_LOCK
|
||||||
@ -483,17 +483,29 @@ init_e300_core: /* time t 10 */
|
|||||||
1:
|
1:
|
||||||
#endif /* CONFIG_WATCHDOG */
|
#endif /* CONFIG_WATCHDOG */
|
||||||
|
|
||||||
|
#if defined(CONFIG_MASK_AER_AO)
|
||||||
|
/* Write the Arbiter Event Enable to mask Address Only traps. */
|
||||||
|
/* This prevents the dcbz instruction from being trapped when */
|
||||||
|
/* HID0_ABE Address Broadcast Enable is set and the MEMORY */
|
||||||
|
/* COHERENCY bit is set in the WIMG bits, which is often */
|
||||||
|
/* needed for PCI operation. */
|
||||||
|
lwz r4, 0x0808(r3)
|
||||||
|
rlwinm r0, r4, 0, ~AER_AO
|
||||||
|
stw r0, 0x0808(r3)
|
||||||
|
#endif /* CONFIG_MASK_AER_AO */
|
||||||
|
|
||||||
/* Initialize the Hardware Implementation-dependent Registers */
|
/* Initialize the Hardware Implementation-dependent Registers */
|
||||||
/* HID0 also contains cache control */
|
/* HID0 also contains cache control */
|
||||||
|
/* - force invalidation of data and instruction caches */
|
||||||
/*------------------------------------------------------*/
|
/*------------------------------------------------------*/
|
||||||
|
|
||||||
lis r3, CFG_HID0_INIT@h
|
lis r3, CFG_HID0_INIT@h
|
||||||
ori r3, r3, CFG_HID0_INIT@l
|
ori r3, r3, (CFG_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
|
||||||
SYNC
|
SYNC
|
||||||
mtspr HID0, r3
|
mtspr HID0, r3
|
||||||
|
|
||||||
lis r3, CFG_HID0_FINAL@h
|
lis r3, CFG_HID0_FINAL@h
|
||||||
ori r3, r3, CFG_HID0_FINAL@l
|
ori r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
|
||||||
SYNC
|
SYNC
|
||||||
mtspr HID0, r3
|
mtspr HID0, r3
|
||||||
|
|
||||||
@ -703,8 +715,7 @@ disable_addr_trans:
|
|||||||
icache_enable:
|
icache_enable:
|
||||||
mfspr r3, HID0
|
mfspr r3, HID0
|
||||||
ori r3, r3, HID0_ICE
|
ori r3, r3, HID0_ICE
|
||||||
lis r4, 0
|
li r4, HID0_ICFI|HID0_ILOCK
|
||||||
ori r4, r4, HID0_ILOCK
|
|
||||||
andc r3, r3, r4
|
andc r3, r3, r4
|
||||||
ori r4, r3, HID0_ICFI
|
ori r4, r3, HID0_ICFI
|
||||||
isync
|
isync
|
||||||
@ -717,13 +728,10 @@ icache_enable:
|
|||||||
icache_disable:
|
icache_disable:
|
||||||
mfspr r3, HID0
|
mfspr r3, HID0
|
||||||
lis r4, 0
|
lis r4, 0
|
||||||
ori r4, r4, HID0_ICE|HID0_ILOCK
|
ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
|
||||||
andc r3, r3, r4
|
andc r3, r3, r4
|
||||||
ori r4, r3, HID0_ICFI
|
|
||||||
isync
|
isync
|
||||||
mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
|
mtspr HID0, r3 /* clears invalidate, enable and lock */
|
||||||
isync
|
|
||||||
mtspr HID0, r3 /* clears invalidate */
|
|
||||||
blr
|
blr
|
||||||
|
|
||||||
.globl icache_status
|
.globl icache_status
|
||||||
@ -737,25 +745,24 @@ dcache_enable:
|
|||||||
mfspr r3, HID0
|
mfspr r3, HID0
|
||||||
li r5, HID0_DCFI|HID0_DLOCK
|
li r5, HID0_DCFI|HID0_DLOCK
|
||||||
andc r3, r3, r5
|
andc r3, r3, r5
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
ori r3, r3, HID0_DCE
|
ori r3, r3, HID0_DCE
|
||||||
ori r5, r3, HID0_DCFI
|
|
||||||
mtspr HID0, r5 /* enable + invalidate */
|
|
||||||
mtspr HID0, r3 /* enable */
|
|
||||||
sync
|
sync
|
||||||
|
mtspr HID0, r3 /* enable, no invalidate */
|
||||||
blr
|
blr
|
||||||
|
|
||||||
.globl dcache_disable
|
.globl dcache_disable
|
||||||
dcache_disable:
|
dcache_disable:
|
||||||
|
mflr r4
|
||||||
|
bl flush_dcache /* uses r3 and r5 */
|
||||||
mfspr r3, HID0
|
mfspr r3, HID0
|
||||||
lis r4, 0
|
li r5, HID0_DCE|HID0_DLOCK
|
||||||
ori r4, r4, HID0_DCE|HID0_DLOCK
|
andc r3, r3, r5
|
||||||
andc r3, r3, r4
|
ori r5, r3, HID0_DCFI
|
||||||
ori r4, r3, HID0_DCI
|
|
||||||
sync
|
sync
|
||||||
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
|
mtspr HID0, r5 /* sets invalidate, clears enable and lock */
|
||||||
sync
|
sync
|
||||||
mtspr HID0, r3 /* clears invalidate */
|
mtspr HID0, r3 /* clears invalidate */
|
||||||
|
mtlr r4
|
||||||
blr
|
blr
|
||||||
|
|
||||||
.globl dcache_status
|
.globl dcache_status
|
||||||
@ -764,6 +771,18 @@ dcache_status:
|
|||||||
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
|
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
|
||||||
blr
|
blr
|
||||||
|
|
||||||
|
.globl flush_dcache
|
||||||
|
flush_dcache:
|
||||||
|
lis r3, 0
|
||||||
|
lis r5, CFG_CACHELINE_SIZE
|
||||||
|
1: cmp 0, 1, r3, r5
|
||||||
|
bge 2f
|
||||||
|
lwz r5, 0(r3)
|
||||||
|
lis r5, CFG_CACHELINE_SIZE
|
||||||
|
addi r3, r3, 0x4
|
||||||
|
b 1b
|
||||||
|
2: blr
|
||||||
|
|
||||||
.globl get_pvr
|
.globl get_pvr
|
||||||
get_pvr:
|
get_pvr:
|
||||||
mfspr r3, PVR
|
mfspr r3, PVR
|
||||||
@ -1060,9 +1079,9 @@ lock_ram_in_cache:
|
|||||||
*/
|
*/
|
||||||
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
||||||
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
||||||
li r2, ((CFG_INIT_RAM_END & ~31) + \
|
li r4, ((CFG_INIT_RAM_END & ~31) + \
|
||||||
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
|
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
|
||||||
mtctr r2
|
mtctr r4
|
||||||
1:
|
1:
|
||||||
dcbz r0, r3
|
dcbz r0, r3
|
||||||
addi r3, r3, 32
|
addi r3, r3, 32
|
||||||
@ -1070,7 +1089,7 @@ lock_ram_in_cache:
|
|||||||
|
|
||||||
/* Lock the data cache */
|
/* Lock the data cache */
|
||||||
mfspr r0, HID0
|
mfspr r0, HID0
|
||||||
ori r0, r0, 0x1000
|
ori r0, r0, HID0_DLOCK
|
||||||
sync
|
sync
|
||||||
mtspr HID0, r0
|
mtspr HID0, r0
|
||||||
sync
|
sync
|
||||||
@ -1082,8 +1101,9 @@ unlock_ram_in_cache:
|
|||||||
/* invalidate the INIT_RAM section */
|
/* invalidate the INIT_RAM section */
|
||||||
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
||||||
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
||||||
li r2,512
|
li r4, ((CFG_INIT_RAM_END & ~31) + \
|
||||||
mtctr r2
|
(CFG_INIT_RAM_ADDR & 31) + 31) / 32
|
||||||
|
mtctr r4
|
||||||
1: icbi r0, r3
|
1: icbi r0, r3
|
||||||
dcbi r0, r3
|
dcbi r0, r3
|
||||||
addi r3, r3, 32
|
addi r3, r3, 32
|
||||||
@ -1096,9 +1116,10 @@ unlock_ram_in_cache:
|
|||||||
li r5, HID0_DLOCK|HID0_DCFI
|
li r5, HID0_DLOCK|HID0_DCFI
|
||||||
andc r3, r3, r5 /* no invalidate, unlock */
|
andc r3, r3, r5 /* no invalidate, unlock */
|
||||||
ori r5, r3, HID0_DCFI /* invalidate, unlock */
|
ori r5, r3, HID0_DCFI /* invalidate, unlock */
|
||||||
mtspr HID0, r5 /* invalidate, unlock */
|
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
sync
|
sync
|
||||||
|
mtspr HID0, r5 /* invalidate, unlock */
|
||||||
|
sync
|
||||||
|
mtspr HID0, r3 /* no invalidate, unlock */
|
||||||
blr
|
blr
|
||||||
#endif /* !CONFIG_NAND_SPL */
|
#endif /* !CONFIG_NAND_SPL */
|
||||||
#endif /* CFG_INIT_RAM_LOCK */
|
#endif /* CFG_INIT_RAM_LOCK */
|
||||||
|
@ -122,6 +122,10 @@ typedef struct global_data {
|
|||||||
phys_size_t ram_size; /* RAM size */
|
phys_size_t ram_size; /* RAM size */
|
||||||
unsigned long reloc_off; /* Relocation Offset */
|
unsigned long reloc_off; /* Relocation Offset */
|
||||||
unsigned long reset_status; /* reset status register at boot */
|
unsigned long reset_status; /* reset status register at boot */
|
||||||
|
#if defined(CONFIG_MPC83XX)
|
||||||
|
unsigned long arbiter_event_attributes;
|
||||||
|
unsigned long arbiter_event_address;
|
||||||
|
#endif
|
||||||
unsigned long env_addr; /* Address of Environment struct */
|
unsigned long env_addr; /* Address of Environment struct */
|
||||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||||
unsigned long have_console; /* serial_init() was called */
|
unsigned long have_console; /* serial_init() was called */
|
||||||
|
Loading…
Reference in New Issue
Block a user