ARM: imx: udoo_neo: Convert to ethernet DM
Convert the UDOO Neo to ethernet DM support. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peter Robinson
Tom Rini
parent
9db428904f
commit
d410dc8802
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@ -9,7 +9,6 @@
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*/
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#include <init.h>
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#include <net.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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@ -18,6 +17,7 @@
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <dm.h>
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#include <env.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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@ -28,8 +28,6 @@
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#include <linux/sizes.h>
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include <malloc.h>
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@ -216,21 +214,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const phy_control_pads[] = {
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/* 25MHz Ethernet PHY Clock */
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MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
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@ -257,7 +240,7 @@ static void setup_iomux_uart(void)
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static int setup_fec(int fec_id)
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static int setup_fec(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg;
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@ -275,46 +258,7 @@ static int setup_fec(int fec_id)
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reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
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writel(reg, &anatop->pll_enet);
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return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
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}
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int board_eth_init(struct bd_info *bis)
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{
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uint32_t base = IMX_FEC_BASE;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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int ret;
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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setup_fec(CONFIG_FEC_ENET_DEV);
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bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
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if (!bus)
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return -EINVAL;
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phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
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PHY_INTERFACE_MODE_RMII);
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if (!phydev) {
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free(bus);
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return -EINVAL;
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}
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ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
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if (ret) {
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free(bus);
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free(phydev);
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return ret;
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}
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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return enable_fec_anatop_clock(0, ENET_25MHZ);
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}
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int board_init(void)
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@ -374,6 +318,7 @@ static int get_board_value(void)
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_fec();
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return 0;
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}
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@ -37,6 +37,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_DM=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_USDHC=y
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@ -46,6 +48,7 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_MII=y
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CONFIG_RGMII=y
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CONFIG_MXC_UART=y
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CONFIG_IMX_THERMAL=y
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CONFIG_OF_LIBFDT=y
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@ -83,14 +83,4 @@
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#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
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#define PFUZE3000_I2C_BUS 0
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/* Network */
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_ENET_DEV 0
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC0"
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#endif /* __CONFIG_H */
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