mirror of
https://github.com/brain-hackers/u-boot-brain
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ppc: Remove MPC837XEMDS board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
a99dab1d33
commit
d3cfc474b7
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@ -70,13 +70,6 @@ config TARGET_MPC8349EMDS_SDRAM
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select SYS_FSL_DDR_BE
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select SYS_FSL_HAS_DDR2
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config TARGET_MPC837XEMDS
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bool "Support MPC837XEMDS"
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select ARCH_MPC837X
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select BOARD_EARLY_INIT_F
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imply CMD_SATA
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imply FSL_SATA
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config TARGET_MPC837XERDB
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bool "Support MPC837XERDB"
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select ARCH_MPC837X
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@ -315,7 +308,6 @@ source "board/freescale/mpc8315erdb/Kconfig"
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source "board/freescale/mpc8323erdb/Kconfig"
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source "board/freescale/mpc832xemds/Kconfig"
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source "board/freescale/mpc8349emds/Kconfig"
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source "board/freescale/mpc837xemds/Kconfig"
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source "board/freescale/mpc837xerdb/Kconfig"
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source "board/ids/ids8313/Kconfig"
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source "board/keymile/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MPC837XEMDS
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config SYS_BOARD
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default "mpc837xemds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC837XEMDS"
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endif
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@ -1,8 +0,0 @@
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MPC837XEMDS BOARD
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#M: Dave Liu <daveliu@freescale.com>
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S: Orphan (since 2018-05)
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F: board/freescale/mpc837xemds/
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F: include/configs/MPC837XEMDS.h
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F: configs/MPC837XEMDS_defconfig
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F: configs/MPC837XEMDS_SLAVE_defconfig
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F: configs/MPC837XEMDS_HOST_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc837xemds.o
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obj-$(CONFIG_PCI) += pci.o
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@ -1,104 +0,0 @@
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Freescale MPC837xEMDS Board
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-----------------------------------------
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1. Board Switches and Jumpers
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1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
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For some reason, the HW designers describe the switch settings
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in terms of 0 and 1, and then map that to physical switches where
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the label "On" refers to logic 0 and "Off" is logic 1.
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Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
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bits may contribute to signals that are numbered based at 0,
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and some of those signals may be high-bit-number-0 too. Heed
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well the names and labels and do not get confused.
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"Off" == 1
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"On" == 0
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SW4[8] is the bit labeled 8 on Switch 4.
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SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
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SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
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and bits labeled 8 is set as "Off".
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1.1 For the MPC837xEMDS Processor Board
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First, make sure the board default setting is consistent with the
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document shipped with your board. Then apply the following setting:
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SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
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SW4[1-8]= 0000_0110 (core PLL setting)
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SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
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SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
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SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
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J3 2-3, TSEC1 LVDD1 with 2.5V
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J6 2-3, TSEC2 LVDD2 with 2.5V
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J9 2-3, CLKIN from osc on board
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J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
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J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
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mounted, HRCW load from BCSR.
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on board Oscillator: 66M
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2. Memory Map
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2.1. The memory map should look pretty much like this:
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
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0xc000_0000 0xdfff_ffff Empty 512M
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0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
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0xe010_0000 0xe02f_ffff Empty 2M
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0xe030_0000 0xe03f_ffff PCI IO 1M
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0xe040_0000 0xe05f_ffff Empty 2M
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0xe060_0000 0xe060_7fff NAND Flash 32K
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0xf400_0000 0xf7ff_ffff Empty 64M
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0xf800_0000 0xf800_7fff BCSR on CS1 32K
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0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC837XEMDS.h
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CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
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CONFIG_MPC837x MPC837x specific
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CONFIG_MPC837XEMDS MPC837XEMDS board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC837XEMDS_config
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make
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5. Downloading and Flashing Images
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5.0 Download over serial line using Kermit:
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loadb
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[Drop to kermit:
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^\c
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send <u-boot-bin-image>
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c
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]
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Or via tftp:
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tftp 40000 u-boot.bin
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5.1 Reflash U-Boot Image using U-Boot
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tftp 40000 u-boot.bin
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protect off fe000000 fe1fffff
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erase fe000000 fe1fffff
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cp.b 40000 fe000000 xxxx
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You have to supply the correct byte count with 'xxxx' from the TFTP result log.
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6. Notes
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1) The console baudrate for MPC837XEMDS is 115200bps.
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@ -1,354 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <init.h>
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#include <net.h>
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#include <asm/bitops.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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#include <spd_sdram.h>
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#include <tsec.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include <fsl_mdio.h>
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#include <phy.h>
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#include "pci.h"
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#include "../common/pq-mds-pib.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[0x9] &= ~0x04;
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/* Clear all of the interrupt of BCSR */
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bcsr[0xe] = 0xff;
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(struct bd_info *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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if (!hwconfig("esdhc"))
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return 0;
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/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
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bcsr[0xc] |= 0x4c;
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/* Set proper bits in SICR to allow SD signals through */
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clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
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clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
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SICRH_GPIO2_E_SD | SICRH_SPI_SD);
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
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int board_eth_init(struct bd_info *bd)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[2];
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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int num = 0;
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/* New line after Net: */
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printf("\n");
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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printf(CONFIG_TSEC1_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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printf(CONFIG_TSEC2_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bd, &mdio_info);
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return tsec_eth_init(bd, tsec_info, num);
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}
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static void __ft_tsec_fixup(void *blob, struct bd_info *bd, const char *alias,
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int phy_addr)
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{
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const u32 *ph;
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int off;
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int err;
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off = fdt_path_offset(blob, alias);
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if (off < 0) {
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printf("WARNING: could not find %s alias: %s.\n", alias,
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fdt_strerror(off));
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return;
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}
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err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
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if (err) {
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printf("WARNING: could not set phy-connection-type for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
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if (!ph) {
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printf("WARNING: could not get phy-handle for %s.\n",
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alias);
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return;
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}
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off = fdt_node_offset_by_phandle(blob, *ph);
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if (off < 0) {
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printf("WARNING: could not get phy node for %s: %s\n", alias,
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fdt_strerror(off));
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return;
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}
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phy_addr = cpu_to_fdt32(phy_addr);
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err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
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if (err < 0) {
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printf("WARNING: could not set phy node's reg for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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}
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static void ft_tsec_fixup(void *blob, struct bd_info *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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#ifdef CONFIG_TSEC1
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
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#endif
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#ifdef CONFIG_TSEC2
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
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#endif
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}
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#else
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static inline void ft_tsec_fixup(void *blob, struct bd_info *bd) {}
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#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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#if (CONFIG_SYS_DDR_SIZE != 512)
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#warning Currenly any ddr size other than 512 is not supported
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#endif
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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udelay(1000);
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|
||||
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
|
||||
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
|
||||
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
|
||||
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
|
||||
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
|
||||
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
||||
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
|
||||
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
|
||||
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
|
||||
__asm__ __volatile__("sync");
|
||||
udelay(1000);
|
||||
|
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
|
||||
udelay(2000);
|
||||
return CONFIG_SYS_DDR_SIZE;
|
||||
}
|
||||
#endif /*!CONFIG_SYS_SPD_EEPROM */
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Freescale MPC837xEMDS\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
int board_pci_host_broken(void)
|
||||
{
|
||||
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
|
||||
const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
|
||||
|
||||
/* It's always OK in case of external arbiter. */
|
||||
if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
|
||||
return 0;
|
||||
|
||||
if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ft_pci_fixup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
const char *status = "broken (no arbiter)";
|
||||
int off;
|
||||
int err;
|
||||
|
||||
off = fdt_path_offset(blob, "pci0");
|
||||
if (off < 0) {
|
||||
printf("WARNING: could not find pci0 alias: %s.\n",
|
||||
fdt_strerror(off));
|
||||
return;
|
||||
}
|
||||
|
||||
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
|
||||
if (err) {
|
||||
printf("WARNING: could not set status for pci0: %s.\n",
|
||||
fdt_strerror(err));
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
ft_tsec_fixup(blob, bd);
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
fdt_fixup_esdhc(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
if (board_pci_host_broken())
|
||||
ft_pci_fixup(blob, bd);
|
||||
ft_pcie_fixup(blob, bd);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
|
|
@ -1,149 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <pci.h>
|
||||
#include <i2c.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_i2c.h>
|
||||
#include <asm/fsl_mpc83xx_serdes.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI_MEM_BASE,
|
||||
phys_start: CONFIG_SYS_PCI_MEM_PHYS,
|
||||
size: CONFIG_SYS_PCI_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI_MMIO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
|
||||
size: CONFIG_SYS_PCI_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
{
|
||||
bus_start: CONFIG_SYS_PCI_IO_BASE,
|
||||
phys_start: CONFIG_SYS_PCI_IO_PHYS,
|
||||
size: CONFIG_SYS_PCI_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
}
|
||||
};
|
||||
|
||||
static struct pci_region pcie_regions_0[] = {
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
|
||||
.flags = PCI_REGION_MEM,
|
||||
},
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
.size = CONFIG_SYS_PCIE1_IO_SIZE,
|
||||
.flags = PCI_REGION_IO,
|
||||
},
|
||||
};
|
||||
|
||||
static struct pci_region pcie_regions_1[] = {
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
|
||||
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
|
||||
.flags = PCI_REGION_MEM,
|
||||
},
|
||||
{
|
||||
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
|
||||
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
|
||||
.size = CONFIG_SYS_PCIE2_IO_SIZE,
|
||||
.flags = PCI_REGION_IO,
|
||||
},
|
||||
};
|
||||
|
||||
static int is_pex_x2(void)
|
||||
{
|
||||
const char *pex_x2 = env_get("pex_x2");
|
||||
|
||||
if (pex_x2 && !strcmp(pex_x2, "yes"))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile sysconf83xx_t *sysconf = &immr->sysconf;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
volatile law83xx_t *pcie_law = sysconf->pcielaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
|
||||
u32 spridr = in_be32(&immr->sysconf.spridr);
|
||||
int pex2 = is_pex_x2();
|
||||
|
||||
if (board_pci_host_broken())
|
||||
goto skip_pci;
|
||||
|
||||
/* Enable all 5 PCI_CLK_OUTPUTS */
|
||||
clk->occr |= 0xf8000000;
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
||||
|
||||
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
||||
|
||||
udelay(2000);
|
||||
|
||||
mpc83xx_pci_init(1, reg);
|
||||
skip_pci:
|
||||
/* There is no PEX in MPC8379 parts. */
|
||||
if (PARTID_NO_E(spridr) == SPR_8379)
|
||||
return;
|
||||
|
||||
if (pex2)
|
||||
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
|
||||
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
|
||||
else
|
||||
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
|
||||
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
|
||||
|
||||
/* Configure the clock for PCIE controller */
|
||||
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
|
||||
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
|
||||
|
||||
/* Deassert the resets in the control register */
|
||||
out_be32(&sysconf->pecr1, 0xE0008000);
|
||||
if (!pex2)
|
||||
out_be32(&sysconf->pecr2, 0xE0008000);
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Express Local Access Windows */
|
||||
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
|
||||
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
|
||||
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
|
||||
|
||||
mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
|
||||
}
|
||||
|
||||
void ft_pcie_fixup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
const char *status = "disabled (PCIE1 is x2)";
|
||||
|
||||
if (!is_pex_x2())
|
||||
return;
|
||||
|
||||
do_fixup_by_path(blob, "pci2", "status", status,
|
||||
strlen(status) + 1, 1);
|
||||
}
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#ifndef __BOARD_MPC837XEMDS_PCI_H
|
||||
#define __BOARD_MPC837XEMDS_PCI_H
|
||||
|
||||
extern void ft_pcie_fixup(void *blob, struct bd_info *bd);
|
||||
|
||||
#endif /* __BOARD_MPC837XEMDS_PCI_H */
|
||||
|
|
@ -1,190 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_MPC837XEMDS=y
|
||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
||||
CONFIG_SYSTEM_PLL_FACTOR_6_1=y
|
||||
CONFIG_CORE_PLL_RATIO_15_1=y
|
||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
||||
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
||||
CONFIG_TSEC1_MODE_RGMII=y
|
||||
CONFIG_TSEC2_MODE_RGMII=y
|
||||
CONFIG_LDP_PIN_MUX_STATE_0=y
|
||||
CONFIG_BAT0=y
|
||||
CONFIG_BAT0_NAME="SDRAM_LOWER"
|
||||
CONFIG_BAT0_BASE=0x00000000
|
||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT0_ACCESS_RW=y
|
||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_USER_MODE_VALID=y
|
||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT1=y
|
||||
CONFIG_BAT1_NAME="SDRAM_UPPER"
|
||||
CONFIG_BAT1_BASE=0x10000000
|
||||
CONFIG_BAT1_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT1_ACCESS_RW=y
|
||||
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_USER_MODE_VALID=y
|
||||
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT2=y
|
||||
CONFIG_BAT2_NAME="IMMR"
|
||||
CONFIG_BAT2_BASE=0xE0000000
|
||||
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
||||
CONFIG_BAT2_ACCESS_RW=y
|
||||
CONFIG_BAT2_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT2_ICACHE_GUARDED=y
|
||||
CONFIG_BAT2_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT2_DCACHE_GUARDED=y
|
||||
CONFIG_BAT2_USER_MODE_VALID=y
|
||||
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT3=y
|
||||
CONFIG_BAT3_NAME="BCSR"
|
||||
CONFIG_BAT3_BASE=0xF8000000
|
||||
CONFIG_BAT3_ACCESS_RW=y
|
||||
CONFIG_BAT3_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT3_ICACHE_GUARDED=y
|
||||
CONFIG_BAT3_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT3_DCACHE_GUARDED=y
|
||||
CONFIG_BAT3_USER_MODE_VALID=y
|
||||
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT4=y
|
||||
CONFIG_BAT4_NAME="FLASH"
|
||||
CONFIG_BAT4_BASE=0xFE000000
|
||||
CONFIG_BAT4_LENGTH_32_MBYTES=y
|
||||
CONFIG_BAT4_ACCESS_RW=y
|
||||
CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT4_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT4_DCACHE_GUARDED=y
|
||||
CONFIG_BAT4_USER_MODE_VALID=y
|
||||
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT5=y
|
||||
CONFIG_BAT5_NAME="STACK_IN_DCACHE"
|
||||
CONFIG_BAT5_BASE=0xE6000000
|
||||
CONFIG_BAT5_ACCESS_RW=y
|
||||
CONFIG_BAT5_USER_MODE_VALID=y
|
||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT6=y
|
||||
CONFIG_BAT6_NAME="PCI_MEM"
|
||||
CONFIG_BAT6_BASE=0x80000000
|
||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT6_ACCESS_RW=y
|
||||
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT6_USER_MODE_VALID=y
|
||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT7=y
|
||||
CONFIG_BAT7_NAME="PCI_MMIO"
|
||||
CONFIG_BAT7_BASE=0x90000000
|
||||
CONFIG_BAT7_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT7_ACCESS_RW=y
|
||||
CONFIG_BAT7_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT7_ICACHE_GUARDED=y
|
||||
CONFIG_BAT7_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT7_DCACHE_GUARDED=y
|
||||
CONFIG_BAT7_USER_MODE_VALID=y
|
||||
CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_LBLAW0=y
|
||||
CONFIG_LBLAW0_BASE=0xFE000000
|
||||
CONFIG_LBLAW0_NAME="FLASH"
|
||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
||||
CONFIG_LBLAW1=y
|
||||
CONFIG_LBLAW1_BASE=0xF8000000
|
||||
CONFIG_LBLAW1_NAME="BCSR"
|
||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
||||
CONFIG_LBLAW3=y
|
||||
CONFIG_LBLAW3_BASE=0xE0600000
|
||||
CONFIG_LBLAW3_NAME="NAND"
|
||||
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
|
||||
CONFIG_ELBC_BR0_OR0=y
|
||||
CONFIG_BR0_OR0_NAME="FLASH"
|
||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
||||
CONFIG_OR0_AM_32_MBYTES=y
|
||||
CONFIG_OR0_XAM_SET=y
|
||||
CONFIG_OR0_SCY_15=y
|
||||
CONFIG_OR0_CSNT_EARLIER=y
|
||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
||||
CONFIG_OR0_XACS_EXTENDED=y
|
||||
CONFIG_OR0_TRLX_RELAXED=y
|
||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
||||
CONFIG_OR0_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR1_OR1=y
|
||||
CONFIG_BR1_OR1_NAME="BCSR"
|
||||
CONFIG_BR1_OR1_BASE=0xF8000000
|
||||
CONFIG_OR1_XAM_SET=y
|
||||
CONFIG_OR1_SCY_15=y
|
||||
CONFIG_OR1_CSNT_EARLIER=y
|
||||
CONFIG_OR1_XACS_EXTENDED=y
|
||||
CONFIG_OR1_TRLX_RELAXED=y
|
||||
CONFIG_OR1_EHTR_8_CYCLE=y
|
||||
CONFIG_OR1_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR3_OR3=y
|
||||
CONFIG_BR3_OR3_NAME="NAND"
|
||||
CONFIG_BR3_OR3_BASE=0xE0600000
|
||||
CONFIG_BR3_ERRORCHECKING_BOTH=y
|
||||
CONFIG_BR3_MACHINE_FCM=y
|
||||
CONFIG_OR3_BCTLD_NOT_ASSERTED=y
|
||||
CONFIG_OR3_SCY_1=y
|
||||
CONFIG_OR3_CST_ONE_CLOCK=y
|
||||
CONFIG_OR3_CHT_TWO_CLOCK=y
|
||||
CONFIG_OR3_RST_ONE_CLOCK=y
|
||||
CONFIG_OR3_TRLX_RELAXED=y
|
||||
CONFIG_OR3_EHTR_8_CYCLE=y
|
||||
CONFIG_HID0_FINAL_EMCP=y
|
||||
CONFIG_HID0_FINAL_ICE=y
|
||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_SPCR_TSECEP_3=y
|
||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_CLKDIV_8=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=6
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xFE080000
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_TARGET_MPC837XEMDS=y
|
||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
||||
CONFIG_SYSTEM_PLL_FACTOR_6_1=y
|
||||
CONFIG_CORE_PLL_RATIO_15_1=y
|
||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
||||
CONFIG_TSEC1_MODE_RGMII=y
|
||||
CONFIG_TSEC2_MODE_RGMII=y
|
||||
CONFIG_LDP_PIN_MUX_STATE_0=y
|
||||
CONFIG_BAT0=y
|
||||
CONFIG_BAT0_NAME="SDRAM_LOWER"
|
||||
CONFIG_BAT0_BASE=0x00000000
|
||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT0_ACCESS_RW=y
|
||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_USER_MODE_VALID=y
|
||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT1=y
|
||||
CONFIG_BAT1_NAME="SDRAM_UPPER"
|
||||
CONFIG_BAT1_BASE=0x10000000
|
||||
CONFIG_BAT1_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT1_ACCESS_RW=y
|
||||
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_USER_MODE_VALID=y
|
||||
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT2=y
|
||||
CONFIG_BAT2_NAME="IMMR"
|
||||
CONFIG_BAT2_BASE=0xE0000000
|
||||
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
||||
CONFIG_BAT2_ACCESS_RW=y
|
||||
CONFIG_BAT2_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT2_ICACHE_GUARDED=y
|
||||
CONFIG_BAT2_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT2_DCACHE_GUARDED=y
|
||||
CONFIG_BAT2_USER_MODE_VALID=y
|
||||
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT3=y
|
||||
CONFIG_BAT3_NAME="BCSR"
|
||||
CONFIG_BAT3_BASE=0xF8000000
|
||||
CONFIG_BAT3_ACCESS_RW=y
|
||||
CONFIG_BAT3_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT3_ICACHE_GUARDED=y
|
||||
CONFIG_BAT3_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT3_DCACHE_GUARDED=y
|
||||
CONFIG_BAT3_USER_MODE_VALID=y
|
||||
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_LBLAW0=y
|
||||
CONFIG_LBLAW0_BASE=0xFE000000
|
||||
CONFIG_LBLAW0_NAME="FLASH"
|
||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
||||
CONFIG_LBLAW1=y
|
||||
CONFIG_LBLAW1_BASE=0xF8000000
|
||||
CONFIG_LBLAW1_NAME="BCSR"
|
||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
||||
CONFIG_LBLAW3=y
|
||||
CONFIG_LBLAW3_BASE=0xE0600000
|
||||
CONFIG_LBLAW3_NAME="NAND"
|
||||
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
|
||||
CONFIG_ELBC_BR0_OR0=y
|
||||
CONFIG_BR0_OR0_NAME="FLASH"
|
||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
||||
CONFIG_OR0_AM_32_MBYTES=y
|
||||
CONFIG_OR0_XAM_SET=y
|
||||
CONFIG_OR0_SCY_15=y
|
||||
CONFIG_OR0_CSNT_EARLIER=y
|
||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
||||
CONFIG_OR0_XACS_EXTENDED=y
|
||||
CONFIG_OR0_TRLX_RELAXED=y
|
||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
||||
CONFIG_OR0_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR1_OR1=y
|
||||
CONFIG_BR1_OR1_NAME="BCSR"
|
||||
CONFIG_BR1_OR1_BASE=0xF8000000
|
||||
CONFIG_OR1_XAM_SET=y
|
||||
CONFIG_OR1_SCY_15=y
|
||||
CONFIG_OR1_CSNT_EARLIER=y
|
||||
CONFIG_OR1_XACS_EXTENDED=y
|
||||
CONFIG_OR1_TRLX_RELAXED=y
|
||||
CONFIG_OR1_EHTR_8_CYCLE=y
|
||||
CONFIG_OR1_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR3_OR3=y
|
||||
CONFIG_BR3_OR3_NAME="NAND"
|
||||
CONFIG_BR3_OR3_BASE=0xE0600000
|
||||
CONFIG_BR3_ERRORCHECKING_BOTH=y
|
||||
CONFIG_BR3_MACHINE_FCM=y
|
||||
CONFIG_OR3_BCTLD_NOT_ASSERTED=y
|
||||
CONFIG_OR3_SCY_1=y
|
||||
CONFIG_OR3_CST_ONE_CLOCK=y
|
||||
CONFIG_OR3_CHT_TWO_CLOCK=y
|
||||
CONFIG_OR3_RST_ONE_CLOCK=y
|
||||
CONFIG_OR3_TRLX_RELAXED=y
|
||||
CONFIG_OR3_EHTR_8_CYCLE=y
|
||||
CONFIG_HID0_FINAL_EMCP=y
|
||||
CONFIG_HID0_FINAL_ICE=y
|
||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_SPCR_TSECEP_3=y
|
||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_CLKDIV_8=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
|
||||
CONFIG_BOOTDELAY=6
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xFE080000
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SYS_CLK_FREQ=66000000
|
||||
CONFIG_MPC83xx=y
|
||||
CONFIG_HIGH_BATS=y
|
||||
CONFIG_TARGET_MPC837XEMDS=y
|
||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
||||
CONFIG_SYSTEM_PLL_FACTOR_6_1=y
|
||||
CONFIG_CORE_PLL_RATIO_15_1=y
|
||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
||||
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
||||
CONFIG_TSEC1_MODE_RGMII=y
|
||||
CONFIG_TSEC2_MODE_RGMII=y
|
||||
CONFIG_LDP_PIN_MUX_STATE_0=y
|
||||
CONFIG_BAT0=y
|
||||
CONFIG_BAT0_NAME="SDRAM_LOWER"
|
||||
CONFIG_BAT0_BASE=0x00000000
|
||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT0_ACCESS_RW=y
|
||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT0_USER_MODE_VALID=y
|
||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT1=y
|
||||
CONFIG_BAT1_NAME="SDRAM_UPPER"
|
||||
CONFIG_BAT1_BASE=0x10000000
|
||||
CONFIG_BAT1_LENGTH_256_MBYTES=y
|
||||
CONFIG_BAT1_ACCESS_RW=y
|
||||
CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT1_USER_MODE_VALID=y
|
||||
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT2=y
|
||||
CONFIG_BAT2_NAME="IMMR"
|
||||
CONFIG_BAT2_BASE=0xE0000000
|
||||
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
||||
CONFIG_BAT2_ACCESS_RW=y
|
||||
CONFIG_BAT2_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT2_ICACHE_GUARDED=y
|
||||
CONFIG_BAT2_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT2_DCACHE_GUARDED=y
|
||||
CONFIG_BAT2_USER_MODE_VALID=y
|
||||
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT3=y
|
||||
CONFIG_BAT3_NAME="BCSR"
|
||||
CONFIG_BAT3_BASE=0xF8000000
|
||||
CONFIG_BAT3_ACCESS_RW=y
|
||||
CONFIG_BAT3_ICACHE_INHIBITED=y
|
||||
CONFIG_BAT3_ICACHE_GUARDED=y
|
||||
CONFIG_BAT3_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT3_DCACHE_GUARDED=y
|
||||
CONFIG_BAT3_USER_MODE_VALID=y
|
||||
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT4=y
|
||||
CONFIG_BAT4_NAME="FLASH"
|
||||
CONFIG_BAT4_BASE=0xFE000000
|
||||
CONFIG_BAT4_LENGTH_32_MBYTES=y
|
||||
CONFIG_BAT4_ACCESS_RW=y
|
||||
CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
|
||||
CONFIG_BAT4_DCACHE_INHIBITED=y
|
||||
CONFIG_BAT4_DCACHE_GUARDED=y
|
||||
CONFIG_BAT4_USER_MODE_VALID=y
|
||||
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_BAT5=y
|
||||
CONFIG_BAT5_NAME="STACK_IN_DCACHE"
|
||||
CONFIG_BAT5_BASE=0xE6000000
|
||||
CONFIG_BAT5_ACCESS_RW=y
|
||||
CONFIG_BAT5_USER_MODE_VALID=y
|
||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
||||
CONFIG_LBLAW0=y
|
||||
CONFIG_LBLAW0_BASE=0xFE000000
|
||||
CONFIG_LBLAW0_NAME="FLASH"
|
||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
||||
CONFIG_LBLAW1=y
|
||||
CONFIG_LBLAW1_BASE=0xF8000000
|
||||
CONFIG_LBLAW1_NAME="BCSR"
|
||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
||||
CONFIG_LBLAW3=y
|
||||
CONFIG_LBLAW3_BASE=0xE0600000
|
||||
CONFIG_LBLAW3_NAME="NAND"
|
||||
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
|
||||
CONFIG_ELBC_BR0_OR0=y
|
||||
CONFIG_BR0_OR0_NAME="FLASH"
|
||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
||||
CONFIG_OR0_AM_32_MBYTES=y
|
||||
CONFIG_OR0_XAM_SET=y
|
||||
CONFIG_OR0_SCY_15=y
|
||||
CONFIG_OR0_CSNT_EARLIER=y
|
||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
||||
CONFIG_OR0_XACS_EXTENDED=y
|
||||
CONFIG_OR0_TRLX_RELAXED=y
|
||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
||||
CONFIG_OR0_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR1_OR1=y
|
||||
CONFIG_BR1_OR1_NAME="BCSR"
|
||||
CONFIG_BR1_OR1_BASE=0xF8000000
|
||||
CONFIG_OR1_XAM_SET=y
|
||||
CONFIG_OR1_SCY_15=y
|
||||
CONFIG_OR1_CSNT_EARLIER=y
|
||||
CONFIG_OR1_XACS_EXTENDED=y
|
||||
CONFIG_OR1_TRLX_RELAXED=y
|
||||
CONFIG_OR1_EHTR_8_CYCLE=y
|
||||
CONFIG_OR1_EAD_EXTRA=y
|
||||
CONFIG_ELBC_BR3_OR3=y
|
||||
CONFIG_BR3_OR3_NAME="NAND"
|
||||
CONFIG_BR3_OR3_BASE=0xE0600000
|
||||
CONFIG_BR3_ERRORCHECKING_BOTH=y
|
||||
CONFIG_BR3_MACHINE_FCM=y
|
||||
CONFIG_OR3_BCTLD_NOT_ASSERTED=y
|
||||
CONFIG_OR3_SCY_1=y
|
||||
CONFIG_OR3_CST_ONE_CLOCK=y
|
||||
CONFIG_OR3_CHT_TWO_CLOCK=y
|
||||
CONFIG_OR3_RST_ONE_CLOCK=y
|
||||
CONFIG_OR3_TRLX_RELAXED=y
|
||||
CONFIG_OR3_EHTR_8_CYCLE=y
|
||||
CONFIG_HID0_FINAL_EMCP=y
|
||||
CONFIG_HID0_FINAL_ICE=y
|
||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_SPCR_TSECEP_3=y
|
||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_CLKDIV_8=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=6
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_ADDR=0xFE080000
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,370 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
|
||||
/*
|
||||
* IP blocks clock configuration
|
||||
*/
|
||||
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
|
||||
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
|
||||
#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CONFIG_SYS_SICRH 0x00000000
|
||||
#define CONFIG_SYS_SICRL 0x00000000
|
||||
|
||||
/*
|
||||
* Output Buffer Impedance
|
||||
*/
|
||||
#define CONFIG_SYS_OBIR 0x31100000
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_83XX_DDR_USES_CS0
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN)
|
||||
/* 0x80080001 */ /* ODT 150ohm on SoC */
|
||||
|
||||
#undef CONFIG_DDR_ECC /* support DDR ECC function */
|
||||
#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
|
||||
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
|
||||
#else
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
* WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
|
||||
* consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
|
||||
| CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
|
||||
| CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
|
||||
| CSCONFIG_ROW_BIT_14 \
|
||||
| CSCONFIG_COL_BIT_10)
|
||||
/* 0x80010202 */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00620802 */
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (13 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (3 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x3935d322 */
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
|
||||
| (6 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
|
||||
/* 0x131088c8 */
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x03E00100 */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
|
||||
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x1432 << SDRAM_MODE_SD_SHIFT))
|
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */
|
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
|
||||
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/*
|
||||
* BCSR on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_BCSR 0xF8000000
|
||||
/* Access window base at BCSR base */
|
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000
|
||||
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
|
||||
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
|
||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
|
||||
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
|
||||
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
|
||||
#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
|
||||
|
||||
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
|
||||
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#ifndef __ASSEMBLY__
|
||||
extern int board_pci_host_broken(void);
|
||||
#endif
|
||||
#define CONFIG_PCIE
|
||||
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
|
||||
|
||||
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 3
|
||||
#define TSEC1_PHY_ADDR_SGMII 8
|
||||
#define TSEC2_PHY_ADDR_SGMII 4
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
/* SERDES */
|
||||
#define CONFIG_FSL_SERDES
|
||||
#define CONFIG_FSL_SERDES1 0xe3000
|
||||
#define CONFIG_FSL_SERDES2 0xe3100
|
||||
|
||||
/*
|
||||
* SATA
|
||||
*/
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1_OFFSET 0x18000
|
||||
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
#define CONFIG_SATA2
|
||||
#define CONFIG_SYS_SATA2_OFFSET 0x19000
|
||||
#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
|
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
||||
|
||||
#ifdef CONFIG_FSL_SATA
|
||||
#define CONFIG_LBA48
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC_PIN_MUX
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=780000\0" \
|
||||
"fdtfile=mpc8379_mds.dtb\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
||||
"$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user