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ColdFire: Fix M5253EVB dram bring up issue
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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parent
855efd04e4
commit
d361307e73
@ -36,8 +36,6 @@ int checkboard(void)
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phys_size_t initdram(int board_type)
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{
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int i;
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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@ -50,21 +48,27 @@ phys_size_t initdram(int board_type)
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
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asm("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x00003224);
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mbar_writeLong(MCFSIM_DACR0, 0x00002320);
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asm("nop");
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/* Initialize DMR0 */
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dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
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mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
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asm("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
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mbar_writeLong(MCFSIM_DACR0, 0x00002328);
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asm("nop");
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/* Write to this block to initiate precharge */
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*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
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asm("nop");
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/* Set RE bit in DACR */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x8000);
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asm("nop");
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/* Wait for at least 8 auto refresh cycles to occur */
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udelay(500);
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@ -72,6 +76,7 @@ phys_size_t initdram(int board_type)
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x0040);
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asm("nop");
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*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
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}
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