mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
6f69bbc8f3
commit
d2d432760d
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@ -20,7 +20,7 @@
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* Jun Gu, Artesyn Technology, jung@artesyncp.com
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* Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
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*
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* (C) Copyright 2005
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -42,6 +42,11 @@
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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@ -246,25 +251,6 @@
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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#endif
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const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
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{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF},
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{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000},
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{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555},
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{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA},
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{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A},
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{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5},
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{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA},
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{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55}
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};
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/* bank_parms is used to sort the bank sizes by descending order */
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struct bank_param {
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unsigned long cr;
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@ -278,46 +264,37 @@ extern unsigned char cfg_simulate_spd_eeprom[128];
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#endif
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void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
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unsigned char spd_read(uchar chip, uint addr);
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static unsigned char spd_read(uchar chip, uint addr);
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static void get_spd_info(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void check_mem_type(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void check_volt_type(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void program_cfg0(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void program_cfg1(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void program_rtr(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void program_tr0(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static void program_tr1(void);
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void get_spd_info(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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#ifdef CONFIG_DDR_ECC
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static void program_ecc(unsigned long num_bytes);
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#endif
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void check_mem_type
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(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void check_volt_type
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(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void program_cfg0(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void program_cfg1(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void program_rtr (unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void program_tr0 (unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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void program_tr1 (void);
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void program_ecc (unsigned long num_bytes);
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unsigned
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long program_bxcr(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks);
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static unsigned long program_bxcr(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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/*
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* This function is reading data from the DIMM module EEPROM over the SPD bus
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@ -328,7 +305,6 @@ long program_bxcr(unsigned long* dimm_populated,
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* BUG: Don't handle ECC memory
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* BUG: A few values in the TR register is currently hardcoded
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*/
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long int spd_sdram(void) {
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unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
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unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
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@ -421,9 +397,8 @@ long int spd_sdram(void) {
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*/
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while (1) {
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mfsdram(mem_mcsts, mcsts);
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if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
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if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
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break;
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}
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}
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/*
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@ -431,14 +406,17 @@ long int spd_sdram(void) {
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*/
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program_tr1();
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#ifdef CONFIG_DDR_ECC
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/*
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* if ECC is enabled, initialize parity bits
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* If ecc is enabled, initialize the parity bits.
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*/
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program_ecc(total_size);
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#endif
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return total_size;
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}
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unsigned char spd_read(uchar chip, uint addr)
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static unsigned char spd_read(uchar chip, uint addr)
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{
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unsigned char data[2];
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@ -460,9 +438,9 @@ unsigned char spd_read(uchar chip, uint addr)
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return 0;
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}
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void get_spd_info(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void get_spd_info(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned long dimm_found;
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@ -480,14 +458,10 @@ void get_spd_info(unsigned long* dimm_populated,
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if ((num_of_bytes != 0) && (total_size != 0)) {
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dimm_populated[dimm_num] = TRUE;
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dimm_found = TRUE;
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#if 0
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printf("DIMM slot %lu: populated\n", dimm_num);
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#endif
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debug("DIMM slot %lu: populated\n", dimm_num);
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} else {
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dimm_populated[dimm_num] = FALSE;
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#if 0
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printf("DIMM slot %lu: Not populated\n", dimm_num);
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#endif
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debug("DIMM slot %lu: Not populated\n", dimm_num);
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}
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}
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@ -497,9 +471,9 @@ void get_spd_info(unsigned long* dimm_populated,
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}
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}
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void check_mem_type(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void check_mem_type(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned char dimm_type;
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@ -509,9 +483,7 @@ void check_mem_type(unsigned long* dimm_populated,
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dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
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switch (dimm_type) {
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case 7:
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#if 0
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printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
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#endif
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debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
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break;
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default:
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printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
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@ -525,10 +497,9 @@ void check_mem_type(unsigned long* dimm_populated,
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}
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}
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void check_volt_type(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void check_volt_type(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned long voltage_type;
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@ -541,18 +512,16 @@ void check_volt_type(unsigned long* dimm_populated,
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dimm_num);
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hang();
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} else {
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#if 0
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printf("DIMM %lu voltage level supported.\n", dimm_num);
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#endif
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debug("DIMM %lu voltage level supported.\n", dimm_num);
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}
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break;
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}
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}
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}
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void program_cfg0(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void program_cfg0(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned long cfg0;
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@ -640,9 +609,9 @@ void program_cfg0(unsigned long* dimm_populated,
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mtsdram(mem_cfg0, cfg0);
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}
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void program_cfg1(unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void program_cfg1(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long cfg1;
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mfsdram(mem_cfg1, cfg1);
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@ -658,9 +627,9 @@ void program_cfg1(unsigned long* dimm_populated,
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mtsdram(mem_cfg1, cfg1);
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}
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void program_rtr (unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void program_rtr(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned long bus_period_x_10;
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@ -676,7 +645,6 @@ void program_rtr (unsigned long* dimm_populated,
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get_sys_info(&sys_info);
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bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
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for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
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if (dimm_populated[dimm_num] == TRUE) {
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refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
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@ -719,9 +687,9 @@ void program_rtr (unsigned long* dimm_populated,
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mtsdram(mem_rtr, sdram_rtr);
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}
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void program_tr0 (unsigned long* dimm_populated,
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unsigned char* iic0_dimm_addr,
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unsigned long num_dimm_banks)
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static void program_tr0(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks)
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{
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unsigned long dimm_num;
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unsigned long tr0;
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@ -1001,13 +969,73 @@ void program_tr0 (unsigned long* dimm_populated,
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break;
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}
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#if 0
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printf("tr0: %x\n", tr0);
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#endif
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debug("tr0: %x\n", tr0);
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mtsdram(mem_tr0, tr0);
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}
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void program_tr1 (void)
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static int short_mem_test(void)
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{
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unsigned long i, j;
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unsigned long bxcr_num;
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unsigned long *membase;
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const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
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{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
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{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
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{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
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{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
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{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
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{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
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{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
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{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
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for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
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mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
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if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
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/* Bank is enabled */
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membase = (unsigned long*)
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(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
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/*
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* Run the short memory test
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*/
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for (i = 0; i < NUMMEMTESTS; i++) {
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for (j = 0; j < NUMMEMWORDS; j++) {
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membase[j] = test[i][j];
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ppcDcbf((unsigned long)&(membase[j]));
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}
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for (j = 0; j < NUMMEMWORDS; j++) {
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if (membase[j] != test[i][j]) {
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ppcDcbf((unsigned long)&(membase[j]));
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return 0;
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}
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ppcDcbf((unsigned long)&(membase[j]));
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}
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if (j < NUMMEMWORDS)
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return 0;
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}
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/*
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* see if the rdclt value passed
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*/
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if (i < NUMMEMTESTS)
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return 0;
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}
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}
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return 1;
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}
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static void program_tr1(void)
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{
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unsigned long tr0;
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unsigned long tr1;
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@ -1015,8 +1043,7 @@ void program_tr1 (void)
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unsigned long ecc_temp;
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unsigned long dlycal;
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unsigned long dly_val;
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unsigned long i, j, k;
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unsigned long bxcr_num;
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unsigned long k;
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unsigned long max_pass_length;
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unsigned long current_pass_length;
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unsigned long current_fail_length;
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@ -1029,7 +1056,6 @@ void program_tr1 (void)
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unsigned char window_found;
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unsigned char fail_found;
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unsigned char pass_found;
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unsigned long * membase;
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PPC440_SYS_INFO sys_info;
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/*
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@ -1079,55 +1105,16 @@ void program_tr1 (void)
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window_found = FALSE;
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fail_found = FALSE;
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pass_found = FALSE;
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#ifdef DEBUG
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printf("Starting memory test ");
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#endif
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debug("Starting memory test ");
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for (k = 0; k < NUMHALFCYCLES; k++) {
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for (rdclt = 0; rdclt < dly_val; rdclt++) {
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for (rdclt = 0; rdclt < dly_val; rdclt++) {
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/*
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* Set the timing reg for the test.
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*/
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mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
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for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
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mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
|
||||
if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
|
||||
/* Bank is enabled */
|
||||
membase = (unsigned long*)
|
||||
(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
|
||||
|
||||
/*
|
||||
* Run the short memory test
|
||||
*/
|
||||
for (i = 0; i < NUMMEMTESTS; i++) {
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
membase[j] = test[i][j];
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
if (membase[j] != test[i][j]) {
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
break;
|
||||
}
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
if (j < NUMMEMWORDS) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* see if the rdclt value passed
|
||||
*/
|
||||
if (i < NUMMEMTESTS) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (bxcr_num == MAXBXCR) {
|
||||
if (short_mem_test()) {
|
||||
if (fail_found == TRUE) {
|
||||
pass_found = TRUE;
|
||||
if (current_pass_length == 0) {
|
||||
|
|
@ -1157,9 +1144,8 @@ void program_tr1 (void)
|
|||
}
|
||||
}
|
||||
}
|
||||
#ifdef DEBUG
|
||||
printf(".");
|
||||
#endif
|
||||
debug(".");
|
||||
|
||||
if (window_found == TRUE) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -1167,9 +1153,7 @@ void program_tr1 (void)
|
|||
tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
|
||||
rdclt_offset += dly_val;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
printf("\n");
|
||||
#endif
|
||||
debug("\n");
|
||||
|
||||
/*
|
||||
* make sure we find the window
|
||||
|
|
@ -1218,18 +1202,17 @@ void program_tr1 (void)
|
|||
}
|
||||
tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
|
||||
|
||||
#if 0
|
||||
printf("tr1: %x\n", tr1);
|
||||
#endif
|
||||
debug("tr1: %x\n", tr1);
|
||||
|
||||
/*
|
||||
* program SDRAM Timing Register 1 TR1
|
||||
*/
|
||||
mtsdram(mem_tr1, tr1);
|
||||
}
|
||||
|
||||
unsigned long program_bxcr(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static unsigned long program_bxcr(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long bank_base_addr;
|
||||
|
|
@ -1262,8 +1245,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
#ifdef CONFIG_BAMBOO
|
||||
/*
|
||||
* This next section is hardware dependent and must be programmed
|
||||
* to match the hardware. For bammboo, the following holds...
|
||||
* 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
|
||||
* to match the hardware. For bamboo, the following holds...
|
||||
* 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
|
||||
* 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
|
||||
* 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
|
||||
* 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
|
||||
|
|
@ -1273,10 +1256,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
ctrl_bank_num[1] = 1;
|
||||
ctrl_bank_num[2] = 3;
|
||||
#else
|
||||
/*
|
||||
* Ocotea, Ebony and the other IBM/AMCC eval boards have
|
||||
* 2 DIMM slots with each max 2 banks
|
||||
*/
|
||||
ctrl_bank_num[0] = 0;
|
||||
ctrl_bank_num[1] = 1;
|
||||
ctrl_bank_num[2] = 2;
|
||||
ctrl_bank_num[3] = 3;
|
||||
ctrl_bank_num[1] = 2;
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -1290,6 +1275,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
|
||||
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
|
||||
bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
|
||||
debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
|
||||
num_row_addr, num_col_addr, num_banks);
|
||||
|
||||
/*
|
||||
* Set the SDRAM0_BxCR regs
|
||||
|
|
@ -1354,9 +1341,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
cr |= SDRAM_BXCR_SDBE;
|
||||
|
||||
for (i = 0; i < num_banks; i++) {
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].bank_size_bytes =
|
||||
(4 * 1024 * 1024) * bank_size_id;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].cr = cr;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
|
||||
(4 << 20) * bank_size_id;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
|
||||
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
|
||||
dimm_num, i, ctrl_bank_num[dimm_num]+i,
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1400,13 +1390,15 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
bank_parms[sorted_bank_num[bx_cr_num]].cr;
|
||||
mtdcr(memcfgd, temp);
|
||||
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
|
||||
debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
|
||||
}
|
||||
}
|
||||
|
||||
return(bank_base_addr);
|
||||
}
|
||||
|
||||
void program_ecc (unsigned long num_bytes)
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void program_ecc(unsigned long num_bytes)
|
||||
{
|
||||
unsigned long bank_base_addr;
|
||||
unsigned long current_address;
|
||||
|
|
@ -1425,14 +1417,12 @@ void program_ecc (unsigned long num_bytes)
|
|||
bank_base_addr = CFG_SDRAM_BASE;
|
||||
|
||||
if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
|
||||
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
|
||||
SDRAM_CFG0_MCHK_GEN);
|
||||
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
|
||||
|
||||
if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
|
||||
if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
|
||||
address_increment = 4;
|
||||
} else {
|
||||
else
|
||||
address_increment = 8;
|
||||
}
|
||||
|
||||
current_address = (unsigned long)(bank_base_addr);
|
||||
end_address = (unsigned long)(bank_base_addr) + num_bytes;
|
||||
|
|
@ -1446,4 +1436,5 @@ void program_ecc (unsigned long num_bytes)
|
|||
SDRAM_CFG0_MCHK_CHK);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_DDR_ECC */
|
||||
#endif /* CONFIG_SPD_EEPROM */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user