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powerpc: Enable device tree support for P1010RDB

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Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Hou Zhiqiang 2020-05-01 19:06:26 +08:00 committed by Priyanka Jain
parent a45fa9e800
commit d2d019b7c3
25 changed files with 223 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/dts/Makefile
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@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb

17
arch/powerpc/dts/p1010rdb-pa.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"

17
arch/powerpc/dts/p1010rdb-pa_36b.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"

17
arch/powerpc/dts/p1010rdb-pb.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"

17
arch/powerpc/dts/p1010rdb-pb_36b.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"

22
arch/powerpc/dts/p1010rdb_32b.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
};
pci0: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
};

22
arch/powerpc/dts/p1010rdb_36b.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};

46
arch/powerpc/dts/p1010si-post.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2020 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1010-immr", "simple-bus";
bus-frequency = <0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
};
/* controller at 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* controller at 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

27
arch/powerpc/dts/p1010si-pre.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2020 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1010";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1010@0 {
device_type = "cpu";
reg = <0x0>;
};
};
};

3
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@ -76,6 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

4
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -57,6 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -70,6 +72,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -72,6 +74,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PA_NAND_defconfig
View File

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@ -75,6 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

4
configs/P1010RDB-PA_NOR_defconfig
View File

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -56,6 +59,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -69,6 +71,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -71,6 +73,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@ -76,6 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

4
configs/P1010RDB-PB_36BIT_NOR_defconfig
View File

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -57,6 +60,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -70,6 +72,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -72,6 +74,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_NAND_defconfig
View File

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@ -75,6 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

4
configs/P1010RDB-PB_NOR_defconfig
View File

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -56,6 +59,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -69,6 +71,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

3
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -71,6 +73,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y