board: ti: k2g: Add support for K2G ICE with 1GHz Silicon

Add board detection support for K2G ICE with FlagChip 1GHz silicon.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2020-12-17 22:58:07 +05:30
parent 9c789fec10
commit d2aa5727a5
6 changed files with 19 additions and 6 deletions

View File

@ -48,11 +48,11 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE); CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF) #if defined(CONFIG_TI_AEMIF)
if (!board_is_k2g_ice()) if (!(board_is_k2g_ice() || board_is_k2g_i1()))
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#endif #endif
if (!board_is_k2g_ice()) { if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
if (ddr3_size) if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
else else

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@ -25,6 +25,10 @@ static inline int board_is_k2g_ice(void)
{ {
return board_ti_is("66AK2GIC"); return board_ti_is("66AK2GIC");
} }
static inline int board_is_k2g_i1(void)
{
return board_ti_is("66AK2GI1");
}
#else #else
static inline int board_is_k2g_gp(void) static inline int board_is_k2g_gp(void)
{ {
@ -34,6 +38,10 @@ static inline int board_is_k2g_ice(void)
{ {
return false; return false;
} }
static inline int board_is_k2g_i1(void)
{
return false;
}
#endif #endif
void spl_init_keystone_plls(void); void spl_init_keystone_plls(void);

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@ -248,7 +248,8 @@ int board_fit_config_name_match(const char *name)
else if (!strcmp(name, "keystone-k2g-evm") && else if (!strcmp(name, "keystone-k2g-evm") &&
(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1"))) (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
return 0; return 0;
else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC")) else if (!strcmp(name, "keystone-k2g-ice") &&
(board_ti_is("66AK2GIC") || board_is_k2g_i1()))
return 0; return 0;
else else
return -1; return -1;
@ -322,7 +323,7 @@ int embedded_dtb_select(void)
BIT(9)); BIT(9));
setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
BIT(9)); BIT(9));
} else if (board_is_k2g_ice()) { } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
/* GBE Phy workaround. For Phy to latch the input /* GBE Phy workaround. For Phy to latch the input
* configuration, a GPIO reset is asserted at the * configuration, a GPIO reset is asserted at the
* Phy reset pin to latch configuration correctly after SoC * Phy reset pin to latch configuration correctly after SoC
@ -364,6 +365,8 @@ int board_late_init(void)
env_set("board_name", "66AK2GG1\0"); env_set("board_name", "66AK2GG1\0");
else if (board_is_k2g_ice()) else if (board_is_k2g_ice())
env_set("board_name", "66AK2GIC\0"); env_set("board_name", "66AK2GIC\0");
else if (board_is_k2g_i1())
env_set("board_name", "66AK2GI1\0");
#endif #endif
return 0; return 0;
} }

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@ -174,7 +174,7 @@ u32 ddr3_init(void)
} else if (board_is_k2g_gp()) { } else if (board_is_k2g_gp()) {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
} else if (board_is_k2g_ice()) { } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
} }

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@ -377,7 +377,7 @@ void k2g_mux_config(void)
configure_pin_mux(k2g_generic_pin_cfg); configure_pin_mux(k2g_generic_pin_cfg);
} else if (board_is_k2g_gp() || board_is_k2g_g1()) { } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
configure_pin_mux(k2g_evm_pin_cfg); configure_pin_mux(k2g_evm_pin_cfg);
} else if (board_is_k2g_ice()) { } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
configure_pin_mux(k2g_ice_evm_pin_cfg); configure_pin_mux(k2g_ice_evm_pin_cfg);
} else { } else {
puts("Unknown board, cannot configure pinmux."); puts("Unknown board, cannot configure pinmux.");

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@ -35,6 +35,8 @@
"setenv name_fdt keystone-k2g-evm.dtb; " \ "setenv name_fdt keystone-k2g-evm.dtb; " \
"else if test $board_name = 66AK2GIC; then " \ "else if test $board_name = 66AK2GIC; then " \
"setenv name_fdt keystone-k2g-ice.dtb; " \ "setenv name_fdt keystone-k2g-ice.dtb; " \
"else if test $board_name = 66AK2GI1; then " \
"setenv name_fdt keystone-k2g-ice.dtb; " \
"else if test $name_fdt = undefined; then " \ "else if test $name_fdt = undefined; then " \
"echo WARNING: Could not determine device tree to use;"\ "echo WARNING: Could not determine device tree to use;"\
"fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \