From 0b80f212824f632f1acb0d74fd932c05a0262fc3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 12:18:44 +0200 Subject: [PATCH 01/10] usb: r8a66597: Remove CONFIG_SUPERH_ON_CHIP_R8A66597 Remove CONFIG_SUPERH_ON_CHIP_R8A66597 macro, which is unused. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 14 -------------- drivers/usb/host/r8a66597.h | 12 ++---------- 2 files changed, 2 insertions(+), 24 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 3c263e51c1..8cca09f6d8 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -61,17 +61,6 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) u16 tmp; int i = 0; -#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) - do { - r8a66597_write(r8a66597, SCKE, SYSCFG0); - tmp = r8a66597_read(r8a66597, SYSCFG0); - if (i++ > 1000) { - printf("register access fail.\n"); - return -1; - } - } while ((tmp & SCKE) != SCKE); - r8a66597_write(r8a66597, 0x04, 0x02); -#else do { r8a66597_write(r8a66597, USBE, SYSCFG0); tmp = r8a66597_read(r8a66597, SYSCFG0); @@ -108,7 +97,6 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) mdelay(1); r8a66597_bset(r8a66597, SUSPM, SUSPMODE0); #endif /* CONFIG_RZA_USB */ -#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */ return 0; } @@ -118,11 +106,9 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597) #if !defined(CONFIG_RZA_USB) r8a66597_bclr(r8a66597, SCKE, SYSCFG0); udelay(1); -#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597) r8a66597_bclr(r8a66597, PLLC, SYSCFG0); r8a66597_bclr(r8a66597, XCKE, SYSCFG0); r8a66597_bclr(r8a66597, USBE, SYSCFG0); -#endif #else r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0); diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index ffdb39e8bb..4859e26355 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -178,15 +178,11 @@ #define REW 0x4000 /* b14: Buffer rewind */ #define DCLRM 0x2000 /* b13: DMA buffer clear mode */ #define DREQE 0x1000 /* b12: DREQ output enable */ -#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) -#define MBW 0x0800 -#else #if !defined(CONFIG_RZA_USB) #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */ #else #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ #endif -#endif #define MBW_8 0x0000 /* 8bit */ #define MBW_16 0x0400 /* 16bit */ #define MBW_32 0x0800 /* 32bit */ @@ -398,11 +394,7 @@ #define R8A66597_MAX_NUM_PIPE 10 #define R8A66597_BUF_BSIZE 8 #define R8A66597_MAX_DEVICE 10 -#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) -#define R8A66597_MAX_ROOT_HUB 1 -#else #define R8A66597_MAX_ROOT_HUB 2 -#endif #define R8A66597_MAX_SAMPLING 5 #define R8A66597_RH_POLL_TIME 10 @@ -435,7 +427,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, int len) { int i; -#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB) +#if defined(CONFIG_RZA_USB) unsigned long fifoaddr = r8a66597->reg + offset; unsigned long count; unsigned long *p = buf; @@ -469,7 +461,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, { int i; unsigned long fifoaddr = r8a66597->reg + offset; -#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB) +#if defined(CONFIG_RZA_USB) unsigned long count; unsigned char *pb; unsigned long *p = buf; From 3ff134b7f1c06f8482ef8ab296d5a89743d219db Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 12:21:08 +0200 Subject: [PATCH 02/10] usb: r8a66597: Make CONFIG_RZA_USB default No other platforms use this r8a66597 controller but RZ/A1, make RZ/A1 support the default and drop all the other SoC support to remove ifdeffery. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 35 ----------------------------- drivers/usb/host/r8a66597.h | 39 --------------------------------- 2 files changed, 74 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 8cca09f6d8..d144b57a61 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -70,20 +70,6 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) } } while ((tmp & USBE) != USBE); r8a66597_bclr(r8a66597, USBE, SYSCFG0); -#if !defined(CONFIG_RZA_USB) - r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0); - - i = 0; - r8a66597_bset(r8a66597, XCKE, SYSCFG0); - do { - udelay(1000); - tmp = r8a66597_read(r8a66597, SYSCFG0); - if (i++ > 500) { - printf("register access fail.\n"); - return -1; - } - } while ((tmp & SCKE) != SCKE); -#else /* * RZ/A Only: * Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0 @@ -96,28 +82,18 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) setbits(le16, R8A66597_BASE0, UPLLE); mdelay(1); r8a66597_bset(r8a66597, SUSPM, SUSPMODE0); -#endif /* CONFIG_RZA_USB */ return 0; } static void r8a66597_clock_disable(struct r8a66597 *r8a66597) { -#if !defined(CONFIG_RZA_USB) - r8a66597_bclr(r8a66597, SCKE, SYSCFG0); - udelay(1); - r8a66597_bclr(r8a66597, PLLC, SYSCFG0); - r8a66597_bclr(r8a66597, XCKE, SYSCFG0); - r8a66597_bclr(r8a66597, USBE, SYSCFG0); -#else r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0); clrbits(le16, R8A66597_BASE0, UPLLE); mdelay(1); r8a66597_bclr(r8a66597, USBE, SYSCFG0); mdelay(1); - -#endif } static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port) @@ -127,10 +103,6 @@ static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port) val = port ? DRPD : DCFM | DRPD; r8a66597_bset(r8a66597, val, get_syscfg_reg(port)); r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port)); - -#if !defined(CONFIG_RZA_USB) - r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port)); -#endif } static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port) @@ -160,9 +132,6 @@ static int enable_controller(struct r8a66597 *r8a66597) if (ret < 0) return ret; -#if !defined(CONFIG_RZA_USB) - r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG); -#endif r8a66597_bset(r8a66597, USBE, SYSCFG0); r8a66597_bset(r8a66597, INTL, SOFCFG); @@ -280,16 +249,13 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev, unsigned long setup_addr = USBREQ; u16 intsts1; int timeout = 3000; -#if defined(CONFIG_RZA_USB) u16 dcpctr; -#endif u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum; r8a66597_write(r8a66597, make_devsel(devsel) | (8 << dev->maxpacketsize), DCPMAXP); r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1); -#if defined(CONFIG_RZA_USB) dcpctr = r8a66597_read(r8a66597, DCPCTR); if ((dcpctr & PID) == PID_BUF) { if (readw_poll_timeout(r8a66597->reg + DCPCTR, dcpctr, @@ -298,7 +264,6 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev, return -ETIMEDOUT; } } -#endif for (i = 0; i < 4; i++) { r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr); diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 4859e26355..1e370cdd6c 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -89,27 +89,14 @@ #define SUSPMODE0 0x102 /* RZ/A only */ /* System Configuration Control Register */ -#if !defined(CONFIG_RZA_USB) -#define XTAL 0xC000 /* b15-14: Crystal selection */ -#define XTAL48 0x8000 /* 48MHz */ -#define XTAL24 0x4000 /* 24MHz */ -#define XTAL12 0x0000 /* 12MHz */ -#define XCKE 0x2000 /* b13: External clock enable */ -#define PLLC 0x0800 /* b11: PLL control */ -#define SCKE 0x0400 /* b10: USB clock enable */ -#define PCSDIS 0x0200 /* b9: not CS wakeup */ -#define LPSME 0x0100 /* b8: Low power sleep mode */ -#endif #define HSE 0x0080 /* b7: Hi-speed enable */ #define DCFM 0x0040 /* b6: Controller function select */ #define DRPD 0x0020 /* b5: D+/- pull down control */ #define DPRPU 0x0010 /* b4: D+ pull up control */ -#if defined(CONFIG_RZA_USB) #define XTAL 0x0004 /* b2: Crystal selection */ #define XTAL12 0x0004 /* 12MHz */ #define XTAL48 0x0000 /* 48MHz */ #define UPLLE 0x0002 /* b1: internal PLL control */ -#endif #define USBE 0x0001 /* b0: USB module operation enable */ /* System Configuration Status Register */ @@ -178,11 +165,7 @@ #define REW 0x4000 /* b14: Buffer rewind */ #define DCLRM 0x2000 /* b13: DMA buffer clear mode */ #define DREQE 0x1000 /* b12: DREQ output enable */ -#if !defined(CONFIG_RZA_USB) -#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */ -#else #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ -#endif #define MBW_8 0x0000 /* 8bit */ #define MBW_16 0x0400 /* 16bit */ #define MBW_32 0x0800 /* 32bit */ @@ -427,7 +410,6 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, int len) { int i; -#if defined(CONFIG_RZA_USB) unsigned long fifoaddr = r8a66597->reg + offset; unsigned long count; unsigned long *p = buf; @@ -440,13 +422,6 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, unsigned long tmp = inl(fifoaddr); memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); } -#else - unsigned short *p = buf; - - len = (len + 1) / 2; - for (i = 0; i < len; i++) - p[i] = inw(r8a66597->reg + offset); -#endif } static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, @@ -461,7 +436,6 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, { int i; unsigned long fifoaddr = r8a66597->reg + offset; -#if defined(CONFIG_RZA_USB) unsigned long count; unsigned char *pb; unsigned long *p = buf; @@ -479,19 +453,6 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, outb(pb[i], fifoaddr + 3 - i); } } -#else - int odd = len & 0x0001; - unsigned short *p = buf; - - len = len / 2; - for (i = 0; i < len; i++) - outw(p[i], fifoaddr); - - if (odd) { - unsigned char *pb = (unsigned char *)(buf + len); - outb(*pb, fifoaddr); - } -#endif } static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, From 4c9a135715ad80ec10a9e642d35e3bbf1535fe56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 13:20:12 +0200 Subject: [PATCH 03/10] usb: r8a66597: Replace IO accessors Replace in{bwl}()/out{bwl}() IO accessors with read{bwl}()/write{bwl}(), to make the driver compile both on SH and ARM. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 1e370cdd6c..7ad14ddfd2 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -402,7 +402,7 @@ struct r8a66597 { static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) { - return inw(r8a66597->reg + offset); + return readw(r8a66597->reg + offset); } static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, @@ -416,10 +416,10 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, count = len / 4; for (i = 0; i < count; i++) - p[i] = inl(r8a66597->reg + offset); + p[i] = readl(r8a66597->reg + offset); if (len & 0x00000003) { - unsigned long tmp = inl(fifoaddr); + unsigned long tmp = readl(fifoaddr); memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); } } @@ -427,7 +427,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, unsigned long offset) { - outw(val, r8a66597->reg + offset); + writew(val, r8a66597->reg + offset); } static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, @@ -442,15 +442,15 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, count = len / 4; for (i = 0; i < count; i++) - outl(p[i], fifoaddr); + writel(p[i], fifoaddr); if (len & 0x00000003) { pb = (unsigned char *)buf + count * 4; for (i = 0; i < (len & 0x00000003); i++) { if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) - outb(pb[i], fifoaddr + i); + writeb(pb[i], fifoaddr + i); else - outb(pb[i], fifoaddr + 3 - i); + writeb(pb[i], fifoaddr + 3 - i); } } } From 81644e01c02967edd3da7eb6c776478a34fa7370 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 13:23:11 +0200 Subject: [PATCH 04/10] usb: r8a66597: Remove BE support While the USB controller can work both in LE and BE modes, there is no user for the BE mode, so drop it. If there ever is a user for it, it can be easily re-added back. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index d144b57a61..2b9f8a150a 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -139,9 +139,9 @@ static int enable_controller(struct r8a66597 *r8a66597) for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) r8a66597_write(r8a66597, 0, get_intenb_reg(port)); - r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, CFIFOSEL); - r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D0FIFOSEL); - r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D1FIFOSEL); + r8a66597_bclr(r8a66597, BIGEND, CFIFOSEL); + r8a66597_bclr(r8a66597, BIGEND, D0FIFOSEL); + r8a66597_bclr(r8a66597, BIGEND, D1FIFOSEL); r8a66597_bset(r8a66597, TRNENSEL, SOFCFG); for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) From 1eb381af9acbec7ec4d5c2a48ebbcf56ef6f97ed Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 12:34:38 +0200 Subject: [PATCH 05/10] usb: r8a66597: Replace R8A66597_BASE0 Replace R8A66597_BASE0 with proper SYSCFG0 accesses, no functional change. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 2b9f8a150a..28d0c0fcde 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -76,10 +76,10 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) * and USB1, so we must always set the USB0 register */ #if (CONFIG_R8A66597_XTAL == 1) - setbits(le16, R8A66597_BASE0, XTAL); + r8a66597_bset(r8a66597, XTAL, SYSCFG0); #endif mdelay(1); - setbits(le16, R8A66597_BASE0, UPLLE); + r8a66597_bset(r8a66597, UPLLE, SYSCFG0); mdelay(1); r8a66597_bset(r8a66597, SUSPM, SUSPMODE0); @@ -90,7 +90,7 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597) { r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0); - clrbits(le16, R8A66597_BASE0, UPLLE); + r8a66597_bclr(r8a66597, UPLLE, SYSCFG0); mdelay(1); r8a66597_bclr(r8a66597, USBE, SYSCFG0); mdelay(1); From 7f3858f90d01cca631d7c6b40301618af060acd7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 12:34:38 +0200 Subject: [PATCH 06/10] usb: r8a66597: Convert to USB DM Convert the R8A66597 USB driver to DM and add support for DT probing. Drop support for legacy non-DM and non-DT probing, since there are no platform using that. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 195 ++++++++++++++++++++------------ 1 file changed, 125 insertions(+), 70 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 28d0c0fcde..b5a93e29f3 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -19,29 +20,49 @@ #define R8A66597_DPRINT(...) #endif -static struct r8a66597 gr8a66597; +static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) +{ + struct udevice *parent = udev->dev->parent; + + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. + * + * If dev is an usb-bus, then we are called from usb_scan_device() for + * an usb-device plugged directly into the root port, return NULL. + */ + if (device_get_uclass_id(udev->dev) == UCLASS_USB) + return NULL; + + /* + * If these 2 are not the same we are being called from + * usb_scan_device() and udev itself is the parent. + */ + if (dev_get_parent_priv(udev->dev) != udev) + return udev; + + /* We are being called normally, use the parent pointer */ + if (device_get_uclass_id(parent) == UCLASS_USB_HUB) + return dev_get_parent_priv(parent); + + return NULL; +} static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport) { - int i; + struct usb_device *parent = usb_dev_get_parent(dev); *hub_devnum = 0; *hubport = 0; /* check a device connected to root_hub */ - if ((dev->parent && dev->parent->devnum == 1) || + if ((parent && parent->devnum == 1) || (dev->devnum == 1)) return; - for (i = 0; i < USB_MAXCHILDREN; i++) { - if (dev->parent->children[i] == dev) { - *hub_devnum = (u8)dev->parent->devnum; - *hubport = i; - return; - } - } - - printf("get_hub_data error.\n"); + *hub_devnum = (u8)parent->devnum; + *hubport = parent->portnr - 1; } static void set_devadd(struct r8a66597 *r8a66597, u8 r8a66597_address, @@ -538,10 +559,11 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597) #include -static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) +static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev, + unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *cmd) { - struct r8a66597 *r8a66597 = &gr8a66597; + struct r8a66597 *r8a66597 = dev_get_priv(udev); int leni = transfer_len; int len = 0; int stat = 0; @@ -609,7 +631,7 @@ static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, } break; case RH_SET_ADDRESS: - gr8a66597.rh_devnum = wValue; + r8a66597->rh_devnum = wValue; break; case RH_GET_DESCRIPTOR: switch ((wValue & 0xff00) >> 8) { @@ -705,50 +727,21 @@ static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, return stat; } -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) +static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device *dev, + unsigned long pipe, void *buffer, int length, + struct devrequest *setup) { - struct r8a66597 *r8a66597 = &gr8a66597; - int ret = 0; - - R8A66597_DPRINT("%s\n", __func__); - R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n", - pipe, buffer, transfer_len, dev->devnum); - - set_devadd(r8a66597, dev->devnum, dev, 0); - - pipe_buffer_setting(r8a66597, dev, pipe); - - dev->act_len = 0; - while (dev->act_len < transfer_len && ret == 0) { - if (ctrlc()) - return -1; - - if (usb_pipein(pipe)) - ret = receive_bulk_packet(r8a66597, dev, pipe, buffer, - transfer_len); - else - ret = send_bulk_packet(r8a66597, dev, pipe, buffer, - transfer_len); - } - - if (ret == 0) - dev->status = 0; - - return ret; -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *setup) -{ - struct r8a66597 *r8a66597 = &gr8a66597; + struct r8a66597 *r8a66597 = dev_get_priv(udev); u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum; + debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, + udev->name, dev, dev->dev->name, dev->portnr); + R8A66597_DPRINT("%s\n", __func__); if (usb_pipedevice(pipe) == r8a66597->rh_devnum) - return r8a66597_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); + return r8a66597_submit_rh_msg(udev, dev, pipe, buffer, + length, setup); R8A66597_DPRINT("%s: setup\n", __func__); set_devadd(r8a66597, r8a66597_address, dev, 0); @@ -761,7 +754,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, dev->act_len = 0; if (usb_pipein(pipe)) if (receive_control_packet(r8a66597, dev, buffer, - transfer_len) < 0) + length) < 0) return -1; if (send_status_packet(r8a66597, pipe) < 0) @@ -772,40 +765,102 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, return 0; } -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) +static int r8a66597_submit_bulk_msg(struct udevice *udev, struct usb_device *dev, + unsigned long pipe, void *buffer, int length) { - /* no implement */ + struct r8a66597 *r8a66597 = dev_get_priv(udev); + int ret = 0; + + debug("%s: dev='%s', udev=%p\n", __func__, udev->name, dev); + R8A66597_DPRINT("%s\n", __func__); + R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n", + pipe, buffer, length, dev->devnum); + + set_devadd(r8a66597, dev->devnum, dev, 0); + + pipe_buffer_setting(r8a66597, dev, pipe); + + dev->act_len = 0; + while (dev->act_len < length && ret == 0) { + if (ctrlc()) + return -1; + + if (usb_pipein(pipe)) + ret = receive_bulk_packet(r8a66597, dev, pipe, buffer, + length); + else + ret = send_bulk_packet(r8a66597, dev, pipe, buffer, + length); + } + + if (ret == 0) + dev->status = 0; + + return ret; +} + +static int r8a66597_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct r8a66597 *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->reg = addr; + return 0; } -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) +static int r8a66597_usb_probe(struct udevice *dev) { - struct r8a66597 *r8a66597 = &gr8a66597; + struct r8a66597 *priv = dev_get_priv(dev); + struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); - R8A66597_DPRINT("%s\n", __func__); + bus_priv->desc_before_addr = true; - memset(r8a66597, 0, sizeof(*r8a66597)); - r8a66597->reg = CONFIG_R8A66597_BASE_ADDR; - - disable_controller(r8a66597); + disable_controller(priv); mdelay(100); - enable_controller(r8a66597); - r8a66597_port_power(r8a66597, 0 , 1); + enable_controller(priv); + r8a66597_port_power(priv, 0 , 1); /* check usb device */ - check_usb_device_connecting(r8a66597); + check_usb_device_connecting(priv); mdelay(50); return 0; } -int usb_lowlevel_stop(int index) +static int r8a66597_usb_remove(struct udevice *dev) { - disable_controller(&gr8a66597); + struct r8a66597 *priv = dev_get_priv(dev); + + disable_controller(priv); return 0; } + +struct dm_usb_ops r8a66597_usb_ops = { + .control = r8a66597_submit_control_msg, + .bulk = r8a66597_submit_bulk_msg, +}; + +static const struct udevice_id r8a66597_usb_ids[] = { + { .compatible = "renesas,rza1-usbhs" }, + { } +}; + +U_BOOT_DRIVER(usb_r8a66597) = { + .name = "r8a66597_usb", + .id = UCLASS_USB, + .of_match = r8a66597_usb_ids, + .ofdata_to_platdata = r8a66597_usb_ofdata_to_platdata, + .probe = r8a66597_usb_probe, + .remove = r8a66597_usb_remove, + .ops = &r8a66597_usb_ops, + .priv_auto_alloc_size = sizeof(struct r8a66597), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; From a3d65651d9dd1b65722c21bf739d1e9978320a47 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 13:23:43 +0200 Subject: [PATCH 07/10] usb: r8a66597: Add Kconfig entry Add missing Kconfig entry for the R8A66597 driver. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 42046c8062..30c6b69be8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -300,3 +300,12 @@ config USB_DWC2_BUFFER_SIZE because larger transactions could be split in smaller ones. endif # USB_DWC2 + +config USB_R8A66597_HCD + bool "Renesas R8A66597 USB Core support" + depends on OF_CONTROL + depends on DM_USB + select USB_HOST + ---help--- + This enables support for the on-chip Renesas R8A66597 USB 2.0 + controller, present in various RZ and SH SoCs. From 8b5483015496100b3f5a790a58cc3019815654e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 13:44:10 +0200 Subject: [PATCH 08/10] usb: r8a66597: Checkpatch cleanup Fix remaining checkpatch complaints in the driver. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 63 ++--- drivers/usb/host/r8a66597.h | 473 ++++++++++++++++---------------- 2 files changed, 268 insertions(+), 268 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index b5a93e29f3..8b60ab2c6d 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -58,7 +58,7 @@ static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport) /* check a device connected to root_hub */ if ((parent && parent->devnum == 1) || - (dev->devnum == 1)) + dev->devnum == 1) return; *hub_devnum = (u8)parent->devnum; @@ -66,7 +66,7 @@ static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport) } static void set_devadd(struct r8a66597 *r8a66597, u8 r8a66597_address, - struct usb_device *dev, int port) + struct usb_device *dev, int port) { u16 val, usbspd, upphub, hubport; unsigned long devadd_reg = get_devadd_addr(r8a66597_address); @@ -321,7 +321,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev, R8A66597_DPRINT("%s\n", __func__); r8a66597_mdfy(r8a66597, MBW | BULK_OUT_PIPENUM, - MBW | CURPIPE, CFIFOSEL); + MBW | CURPIPE, CFIFOSEL); r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, BULK_OUT_PIPENUM); tmp = r8a66597_read(r8a66597, CFIFOCTR); if ((tmp & FRDY) == 0) { @@ -345,7 +345,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev, dev->act_len += size; r8a66597_mdfy(r8a66597, PID_BUF, PID, - get_pipectr_addr(BULK_OUT_PIPENUM)); + get_pipectr_addr(BULK_OUT_PIPENUM)); while (!(r8a66597_read(r8a66597, BEMPSTS) & (1 << BULK_OUT_PIPENUM))) if (ctrlc()) @@ -354,7 +354,7 @@ static int send_bulk_packet(struct r8a66597 *r8a66597, struct usb_device *dev, if (dev->act_len >= transfer_len) r8a66597_mdfy(r8a66597, PID_NAK, PID, - get_pipectr_addr(BULK_OUT_PIPENUM)); + get_pipectr_addr(BULK_OUT_PIPENUM)); return 0; } @@ -375,17 +375,17 @@ static int receive_bulk_packet(struct r8a66597 *r8a66597, /* prepare */ if (dev->act_len == 0) { r8a66597_mdfy(r8a66597, PID_NAK, PID, - get_pipectr_addr(pipenum)); + get_pipectr_addr(pipenum)); r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS); r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum)); r8a66597_write(r8a66597, - (transfer_len + maxpacket - 1) / maxpacket, + (transfer_len + maxpacket - 1) / maxpacket, get_pipetrn_addr(pipenum)); r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum)); r8a66597_mdfy(r8a66597, PID_BUF, PID, - get_pipectr_addr(pipenum)); + get_pipectr_addr(pipenum)); } r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL); @@ -462,7 +462,7 @@ static int receive_control_packet(struct r8a66597 *r8a66597, } static int send_status_packet(struct r8a66597 *r8a66597, - unsigned long pipe) + unsigned long pipe) { r8a66597_bset(r8a66597, SQSET, DCPCTR); r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR); @@ -553,9 +553,7 @@ static int check_usb_device_connecting(struct r8a66597 *r8a66597) return -1; /* fail */ } -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ +/* Virtual Root Hub */ #include @@ -637,34 +635,34 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev, switch ((wValue & 0xff00) >> 8) { case (0x01): /* device descriptor */ len = min_t(unsigned int, - leni, + leni, min_t(unsigned int, - sizeof(root_hub_dev_des), + sizeof(root_hub_dev_des), wLength)); memcpy(buffer, root_hub_dev_des, len); break; case (0x02): /* configuration descriptor */ len = min_t(unsigned int, - leni, + leni, min_t(unsigned int, - sizeof(root_hub_config_des), + sizeof(root_hub_config_des), wLength)); memcpy(buffer, root_hub_config_des, len); break; case (0x03): /* string descriptors */ if (wValue == 0x0300) { len = min_t(unsigned int, - leni, + leni, min_t(unsigned int, - sizeof(root_hub_str_index0), + sizeof(root_hub_str_index0), wLength)); memcpy(buffer, root_hub_str_index0, len); } if (wValue == 0x0301) { len = min_t(unsigned int, - leni, + leni, min_t(unsigned int, - sizeof(root_hub_str_index1), + sizeof(root_hub_str_index1), wLength)); memcpy(buffer, root_hub_str_index1, len); } @@ -697,7 +695,8 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev, } else { data[0] += 2; data[8] = (temp & RH_B_DR) >> 8; - data[10] = data[9] = 0xff; + data[9] = 0xff; + data[10] = 0xff; } len = min_t(unsigned int, leni, @@ -707,7 +706,7 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev, } case RH_GET_CONFIGURATION: - *(__u8 *) buffer = 0x01; + *(__u8 *)buffer = 0x01; len = 1; break; case RH_SET_CONFIGURATION: @@ -727,9 +726,10 @@ static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev, return stat; } -static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device *dev, - unsigned long pipe, void *buffer, int length, - struct devrequest *setup) +static int r8a66597_submit_control_msg(struct udevice *udev, + struct usb_device *dev, + unsigned long pipe, void *buffer, + int length, struct devrequest *setup) { struct r8a66597 *r8a66597 = dev_get_priv(udev); u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ? @@ -754,7 +754,7 @@ static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device * dev->act_len = 0; if (usb_pipein(pipe)) if (receive_control_packet(r8a66597, dev, buffer, - length) < 0) + length) < 0) return -1; if (send_status_packet(r8a66597, pipe) < 0) @@ -765,8 +765,9 @@ static int r8a66597_submit_control_msg(struct udevice *udev, struct usb_device * return 0; } -static int r8a66597_submit_bulk_msg(struct udevice *udev, struct usb_device *dev, - unsigned long pipe, void *buffer, int length) +static int r8a66597_submit_bulk_msg(struct udevice *udev, + struct usb_device *dev, unsigned long pipe, + void *buffer, int length) { struct r8a66597 *r8a66597 = dev_get_priv(udev); int ret = 0; @@ -788,10 +789,10 @@ static int r8a66597_submit_bulk_msg(struct udevice *udev, struct usb_device *dev if (usb_pipein(pipe)) ret = receive_bulk_packet(r8a66597, dev, pipe, buffer, - length); + length); else ret = send_bulk_packet(r8a66597, dev, pipe, buffer, - length); + length); } if (ret == 0) @@ -824,7 +825,7 @@ static int r8a66597_usb_probe(struct udevice *dev) mdelay(100); enable_controller(priv); - r8a66597_port_power(priv, 0 , 1); + r8a66597_port_power(priv, 0, 1); /* check usb device */ check_usb_device_connecting(priv); diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 7ad14ddfd2..3077bc7999 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -72,9 +72,9 @@ #define PIPE3TRE 0x98 #define PIPE3TRN 0x9A #define PIPE4TRE 0x9C -#define PIPE4TRN 0x9E -#define PIPE5TRE 0xA0 -#define PIPE5TRN 0xA2 +#define PIPE4TRN 0x9E +#define PIPE5TRE 0xA0 +#define PIPE5TRN 0xA2 #define DEVADD0 0xD0 #define DEVADD1 0xD2 #define DEVADD2 0xD4 @@ -89,290 +89,290 @@ #define SUSPMODE0 0x102 /* RZ/A only */ /* System Configuration Control Register */ -#define HSE 0x0080 /* b7: Hi-speed enable */ -#define DCFM 0x0040 /* b6: Controller function select */ -#define DRPD 0x0020 /* b5: D+/- pull down control */ -#define DPRPU 0x0010 /* b4: D+ pull up control */ -#define XTAL 0x0004 /* b2: Crystal selection */ -#define XTAL12 0x0004 /* 12MHz */ -#define XTAL48 0x0000 /* 48MHz */ -#define UPLLE 0x0002 /* b1: internal PLL control */ -#define USBE 0x0001 /* b0: USB module operation enable */ +#define HSE 0x0080 /* b7: Hi-speed enable */ +#define DCFM 0x0040 /* b6: Controller function select */ +#define DRPD 0x0020 /* b5: D+/- pull down control */ +#define DPRPU 0x0010 /* b4: D+ pull up control */ +#define XTAL 0x0004 /* b2: Crystal selection */ +#define XTAL12 0x0004 /* 12MHz */ +#define XTAL48 0x0000 /* 48MHz */ +#define UPLLE 0x0002 /* b1: internal PLL control */ +#define USBE 0x0001 /* b0: USB module operation enable */ /* System Configuration Status Register */ -#define OVCBIT 0x8000 /* b15-14: Over-current bit */ -#define OVCMON 0xC000 /* b15-14: Over-current monitor */ -#define SOFEA 0x0020 /* b5: SOF monitor */ -#define IDMON 0x0004 /* b3: ID-pin monitor */ -#define LNST 0x0003 /* b1-0: D+, D- line status */ -#define SE1 0x0003 /* SE1 */ -#define FS_KSTS 0x0002 /* Full-Speed K State */ -#define FS_JSTS 0x0001 /* Full-Speed J State */ -#define LS_JSTS 0x0002 /* Low-Speed J State */ -#define LS_KSTS 0x0001 /* Low-Speed K State */ -#define SE0 0x0000 /* SE0 */ +#define OVCBIT 0x8000 /* b15-14: Over-current bit */ +#define OVCMON 0xC000 /* b15-14: Over-current monitor */ +#define SOFEA 0x0020 /* b5: SOF monitor */ +#define IDMON 0x0004 /* b3: ID-pin monitor */ +#define LNST 0x0003 /* b1-0: D+, D- line status */ +#define SE1 0x0003 /* SE1 */ +#define FS_KSTS 0x0002 /* Full-Speed K State */ +#define FS_JSTS 0x0001 /* Full-Speed J State */ +#define LS_JSTS 0x0002 /* Low-Speed J State */ +#define LS_KSTS 0x0001 /* Low-Speed K State */ +#define SE0 0x0000 /* SE0 */ /* Device State Control Register */ -#define EXTLP0 0x0400 /* b10: External port */ -#define VBOUT 0x0200 /* b9: VBUS output */ -#define WKUP 0x0100 /* b8: Remote wakeup */ -#define RWUPE 0x0080 /* b7: Remote wakeup sense */ -#define USBRST 0x0040 /* b6: USB reset enable */ -#define RESUME 0x0020 /* b5: Resume enable */ -#define UACT 0x0010 /* b4: USB bus enable */ -#define RHST 0x0007 /* b1-0: Reset handshake status */ -#define HSPROC 0x0004 /* HS handshake is processing */ -#define HSMODE 0x0003 /* Hi-Speed mode */ -#define FSMODE 0x0002 /* Full-Speed mode */ -#define LSMODE 0x0001 /* Low-Speed mode */ -#define UNDECID 0x0000 /* Undecided */ +#define EXTLP0 0x0400 /* b10: External port */ +#define VBOUT 0x0200 /* b9: VBUS output */ +#define WKUP 0x0100 /* b8: Remote wakeup */ +#define RWUPE 0x0080 /* b7: Remote wakeup sense */ +#define USBRST 0x0040 /* b6: USB reset enable */ +#define RESUME 0x0020 /* b5: Resume enable */ +#define UACT 0x0010 /* b4: USB bus enable */ +#define RHST 0x0007 /* b1-0: Reset handshake status */ +#define HSPROC 0x0004 /* HS handshake is processing */ +#define HSMODE 0x0003 /* Hi-Speed mode */ +#define FSMODE 0x0002 /* Full-Speed mode */ +#define LSMODE 0x0001 /* Low-Speed mode */ +#define UNDECID 0x0000 /* Undecided */ /* Test Mode Register */ -#define UTST 0x000F /* b3-0: Test select */ -#define H_TST_PACKET 0x000C /* HOST TEST Packet */ -#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ -#define H_TST_K 0x000A /* HOST TEST K */ -#define H_TST_J 0x0009 /* HOST TEST J */ -#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ -#define P_TST_PACKET 0x0004 /* PERI TEST Packet */ -#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ -#define P_TST_K 0x0002 /* PERI TEST K */ -#define P_TST_J 0x0001 /* PERI TEST J */ -#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ +#define UTST 0x000F /* b3-0: Test select */ +#define H_TST_PACKET 0x000C /* HOST TEST Packet */ +#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ +#define H_TST_K 0x000A /* HOST TEST K */ +#define H_TST_J 0x0009 /* HOST TEST J */ +#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ +#define P_TST_PACKET 0x0004 /* PERI TEST Packet */ +#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ +#define P_TST_K 0x0002 /* PERI TEST K */ +#define P_TST_J 0x0001 /* PERI TEST J */ +#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ /* Data Pin Configuration Register */ -#define LDRV 0x8000 /* b15: Drive Current Adjust */ -#define VIF1 0x0000 /* VIF = 1.8V */ -#define VIF3 0x8000 /* VIF = 3.3V */ -#define INTA 0x0001 /* b1: USB INT-pin active */ +#define LDRV 0x8000 /* b15: Drive Current Adjust */ +#define VIF1 0x0000 /* VIF = 1.8V */ +#define VIF3 0x8000 /* VIF = 3.3V */ +#define INTA 0x0001 /* b1: USB INT-pin active */ /* DMAx Pin Configuration Register */ -#define DREQA 0x4000 /* b14: Dreq active select */ -#define BURST 0x2000 /* b13: Burst mode */ -#define DACKA 0x0400 /* b10: Dack active select */ -#define DFORM 0x0380 /* b9-7: DMA mode select */ -#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ -#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ -#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ -#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ -#define DENDA 0x0040 /* b6: Dend active select */ -#define PKTM 0x0020 /* b5: Packet mode */ -#define DENDE 0x0010 /* b4: Dend enable */ -#define OBUS 0x0004 /* b2: OUTbus mode */ +#define DREQA 0x4000 /* b14: Dreq active select */ +#define BURST 0x2000 /* b13: Burst mode */ +#define DACKA 0x0400 /* b10: Dack active select */ +#define DFORM 0x0380 /* b9-7: DMA mode select */ +#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ +#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ +#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ +#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ +#define DENDA 0x0040 /* b6: Dend active select */ +#define PKTM 0x0020 /* b5: Packet mode */ +#define DENDE 0x0010 /* b4: Dend enable */ +#define OBUS 0x0004 /* b2: OUTbus mode */ /* CFIFO/DxFIFO Port Select Register */ -#define RCNT 0x8000 /* b15: Read count mode */ -#define REW 0x4000 /* b14: Buffer rewind */ -#define DCLRM 0x2000 /* b13: DMA buffer clear mode */ -#define DREQE 0x1000 /* b12: DREQ output enable */ -#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ -#define MBW_8 0x0000 /* 8bit */ -#define MBW_16 0x0400 /* 16bit */ -#define MBW_32 0x0800 /* 32bit */ -#define BIGEND 0x0100 /* b8: Big endian mode */ -#define BYTE_LITTLE 0x0000 /* little dendian */ -#define BYTE_BIG 0x0100 /* big endifan */ -#define ISEL 0x0020 /* b5: DCP FIFO port direction select */ -#define CURPIPE 0x000F /* b2-0: PIPE select */ +#define RCNT 0x8000 /* b15: Read count mode */ +#define REW 0x4000 /* b14: Buffer rewind */ +#define DCLRM 0x2000 /* b13: DMA buffer clear mode */ +#define DREQE 0x1000 /* b12: DREQ output enable */ +#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ +#define MBW_8 0x0000 /* 8bit */ +#define MBW_16 0x0400 /* 16bit */ +#define MBW_32 0x0800 /* 32bit */ +#define BIGEND 0x0100 /* b8: Big endian mode */ +#define BYTE_LITTLE 0x0000 /* little dendian */ +#define BYTE_BIG 0x0100 /* big endifan */ +#define ISEL 0x0020 /* b5: DCP FIFO port direction select */ +#define CURPIPE 0x000F /* b2-0: PIPE select */ /* CFIFO/DxFIFO Port Control Register */ -#define BVAL 0x8000 /* b15: Buffer valid flag */ -#define BCLR 0x4000 /* b14: Buffer clear */ -#define FRDY 0x2000 /* b13: FIFO ready */ -#define DTLN 0x0FFF /* b11-0: FIFO received data length */ +#define BVAL 0x8000 /* b15: Buffer valid flag */ +#define BCLR 0x4000 /* b14: Buffer clear */ +#define FRDY 0x2000 /* b13: FIFO ready */ +#define DTLN 0x0FFF /* b11-0: FIFO received data length */ /* Interrupt Enable Register 0 */ -#define VBSE 0x8000 /* b15: VBUS interrupt */ -#define RSME 0x4000 /* b14: Resume interrupt */ -#define SOFE 0x2000 /* b13: Frame update interrupt */ -#define DVSE 0x1000 /* b12: Device state transition interrupt */ -#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ -#define BEMPE 0x0400 /* b10: Buffer empty interrupt */ -#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ -#define BRDYE 0x0100 /* b8: Buffer ready interrupt */ +#define VBSE 0x8000 /* b15: VBUS interrupt */ +#define RSME 0x4000 /* b14: Resume interrupt */ +#define SOFE 0x2000 /* b13: Frame update interrupt */ +#define DVSE 0x1000 /* b12: Device state transition interrupt */ +#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ +#define BEMPE 0x0400 /* b10: Buffer empty interrupt */ +#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ +#define BRDYE 0x0100 /* b8: Buffer ready interrupt */ /* Interrupt Enable Register 1 */ -#define OVRCRE 0x8000 /* b15: Over-current interrupt */ -#define BCHGE 0x4000 /* b14: USB us chenge interrupt */ -#define DTCHE 0x1000 /* b12: Detach sense interrupt */ -#define ATTCHE 0x0800 /* b11: Attach sense interrupt */ -#define EOFERRE 0x0040 /* b6: EOF error interrupt */ -#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ -#define SACKE 0x0010 /* b4: SETUP ACK interrupt */ +#define OVRCRE 0x8000 /* b15: Over-current interrupt */ +#define BCHGE 0x4000 /* b14: USB us chenge interrupt */ +#define DTCHE 0x1000 /* b12: Detach sense interrupt */ +#define ATTCHE 0x0800 /* b11: Attach sense interrupt */ +#define EOFERRE 0x0040 /* b6: EOF error interrupt */ +#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ +#define SACKE 0x0010 /* b4: SETUP ACK interrupt */ /* BRDY Interrupt Enable/Status Register */ -#define BRDY9 0x0200 /* b9: PIPE9 */ -#define BRDY8 0x0100 /* b8: PIPE8 */ -#define BRDY7 0x0080 /* b7: PIPE7 */ -#define BRDY6 0x0040 /* b6: PIPE6 */ -#define BRDY5 0x0020 /* b5: PIPE5 */ -#define BRDY4 0x0010 /* b4: PIPE4 */ -#define BRDY3 0x0008 /* b3: PIPE3 */ -#define BRDY2 0x0004 /* b2: PIPE2 */ -#define BRDY1 0x0002 /* b1: PIPE1 */ -#define BRDY0 0x0001 /* b1: PIPE0 */ +#define BRDY9 0x0200 /* b9: PIPE9 */ +#define BRDY8 0x0100 /* b8: PIPE8 */ +#define BRDY7 0x0080 /* b7: PIPE7 */ +#define BRDY6 0x0040 /* b6: PIPE6 */ +#define BRDY5 0x0020 /* b5: PIPE5 */ +#define BRDY4 0x0010 /* b4: PIPE4 */ +#define BRDY3 0x0008 /* b3: PIPE3 */ +#define BRDY2 0x0004 /* b2: PIPE2 */ +#define BRDY1 0x0002 /* b1: PIPE1 */ +#define BRDY0 0x0001 /* b1: PIPE0 */ /* NRDY Interrupt Enable/Status Register */ -#define NRDY9 0x0200 /* b9: PIPE9 */ -#define NRDY8 0x0100 /* b8: PIPE8 */ -#define NRDY7 0x0080 /* b7: PIPE7 */ -#define NRDY6 0x0040 /* b6: PIPE6 */ -#define NRDY5 0x0020 /* b5: PIPE5 */ -#define NRDY4 0x0010 /* b4: PIPE4 */ -#define NRDY3 0x0008 /* b3: PIPE3 */ -#define NRDY2 0x0004 /* b2: PIPE2 */ -#define NRDY1 0x0002 /* b1: PIPE1 */ -#define NRDY0 0x0001 /* b1: PIPE0 */ +#define NRDY9 0x0200 /* b9: PIPE9 */ +#define NRDY8 0x0100 /* b8: PIPE8 */ +#define NRDY7 0x0080 /* b7: PIPE7 */ +#define NRDY6 0x0040 /* b6: PIPE6 */ +#define NRDY5 0x0020 /* b5: PIPE5 */ +#define NRDY4 0x0010 /* b4: PIPE4 */ +#define NRDY3 0x0008 /* b3: PIPE3 */ +#define NRDY2 0x0004 /* b2: PIPE2 */ +#define NRDY1 0x0002 /* b1: PIPE1 */ +#define NRDY0 0x0001 /* b1: PIPE0 */ /* BEMP Interrupt Enable/Status Register */ -#define BEMP9 0x0200 /* b9: PIPE9 */ -#define BEMP8 0x0100 /* b8: PIPE8 */ -#define BEMP7 0x0080 /* b7: PIPE7 */ -#define BEMP6 0x0040 /* b6: PIPE6 */ -#define BEMP5 0x0020 /* b5: PIPE5 */ -#define BEMP4 0x0010 /* b4: PIPE4 */ -#define BEMP3 0x0008 /* b3: PIPE3 */ -#define BEMP2 0x0004 /* b2: PIPE2 */ -#define BEMP1 0x0002 /* b1: PIPE1 */ -#define BEMP0 0x0001 /* b0: PIPE0 */ +#define BEMP9 0x0200 /* b9: PIPE9 */ +#define BEMP8 0x0100 /* b8: PIPE8 */ +#define BEMP7 0x0080 /* b7: PIPE7 */ +#define BEMP6 0x0040 /* b6: PIPE6 */ +#define BEMP5 0x0020 /* b5: PIPE5 */ +#define BEMP4 0x0010 /* b4: PIPE4 */ +#define BEMP3 0x0008 /* b3: PIPE3 */ +#define BEMP2 0x0004 /* b2: PIPE2 */ +#define BEMP1 0x0002 /* b1: PIPE1 */ +#define BEMP0 0x0001 /* b0: PIPE0 */ /* SOF Pin Configuration Register */ -#define TRNENSEL 0x0100 /* b8: Select transaction enable period */ -#define BRDYM 0x0040 /* b6: BRDY clear timing */ -#define INTL 0x0020 /* b5: Interrupt sense select */ -#define EDGESTS 0x0010 /* b4: */ -#define SOFMODE 0x000C /* b3-2: SOF pin select */ -#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ -#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ -#define SOF_DISABLE 0x0000 /* SOF OUT Disable */ +#define TRNENSEL 0x0100 /* b8: Select transaction enable period */ +#define BRDYM 0x0040 /* b6: BRDY clear timing */ +#define INTL 0x0020 /* b5: Interrupt sense select */ +#define EDGESTS 0x0010 /* b4: */ +#define SOFMODE 0x000C /* b3-2: SOF pin select */ +#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ +#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ +#define SOF_DISABLE 0x0000 /* SOF OUT Disable */ /* Interrupt Status Register 0 */ -#define VBINT 0x8000 /* b15: VBUS interrupt */ -#define RESM 0x4000 /* b14: Resume interrupt */ -#define SOFR 0x2000 /* b13: SOF frame update interrupt */ -#define DVST 0x1000 /* b12: Device state transition interrupt */ -#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ -#define BEMP 0x0400 /* b10: Buffer empty interrupt */ -#define NRDY 0x0200 /* b9: Buffer not ready interrupt */ -#define BRDY 0x0100 /* b8: Buffer ready interrupt */ -#define VBSTS 0x0080 /* b7: VBUS input port */ -#define DVSQ 0x0070 /* b6-4: Device state */ -#define DS_SPD_CNFG 0x0070 /* Suspend Configured */ -#define DS_SPD_ADDR 0x0060 /* Suspend Address */ -#define DS_SPD_DFLT 0x0050 /* Suspend Default */ -#define DS_SPD_POWR 0x0040 /* Suspend Powered */ -#define DS_SUSP 0x0040 /* Suspend */ -#define DS_CNFG 0x0030 /* Configured */ -#define DS_ADDS 0x0020 /* Address */ -#define DS_DFLT 0x0010 /* Default */ -#define DS_POWR 0x0000 /* Powered */ -#define DVSQS 0x0030 /* b5-4: Device state */ -#define VALID 0x0008 /* b3: Setup packet detected flag */ -#define CTSQ 0x0007 /* b2-0: Control transfer stage */ -#define CS_SQER 0x0006 /* Sequence error */ -#define CS_WRND 0x0005 /* Control write nodata status stage */ -#define CS_WRSS 0x0004 /* Control write status stage */ -#define CS_WRDS 0x0003 /* Control write data stage */ -#define CS_RDSS 0x0002 /* Control read status stage */ -#define CS_RDDS 0x0001 /* Control read data stage */ -#define CS_IDST 0x0000 /* Idle or setup stage */ +#define VBINT 0x8000 /* b15: VBUS interrupt */ +#define RESM 0x4000 /* b14: Resume interrupt */ +#define SOFR 0x2000 /* b13: SOF frame update interrupt */ +#define DVST 0x1000 /* b12: Device state transition interrupt */ +#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ +#define BEMP 0x0400 /* b10: Buffer empty interrupt */ +#define NRDY 0x0200 /* b9: Buffer not ready interrupt */ +#define BRDY 0x0100 /* b8: Buffer ready interrupt */ +#define VBSTS 0x0080 /* b7: VBUS input port */ +#define DVSQ 0x0070 /* b6-4: Device state */ +#define DS_SPD_CNFG 0x0070 /* Suspend Configured */ +#define DS_SPD_ADDR 0x0060 /* Suspend Address */ +#define DS_SPD_DFLT 0x0050 /* Suspend Default */ +#define DS_SPD_POWR 0x0040 /* Suspend Powered */ +#define DS_SUSP 0x0040 /* Suspend */ +#define DS_CNFG 0x0030 /* Configured */ +#define DS_ADDS 0x0020 /* Address */ +#define DS_DFLT 0x0010 /* Default */ +#define DS_POWR 0x0000 /* Powered */ +#define DVSQS 0x0030 /* b5-4: Device state */ +#define VALID 0x0008 /* b3: Setup packet detected flag */ +#define CTSQ 0x0007 /* b2-0: Control transfer stage */ +#define CS_SQER 0x0006 /* Sequence error */ +#define CS_WRND 0x0005 /* Control write nodata status stage */ +#define CS_WRSS 0x0004 /* Control write status stage */ +#define CS_WRDS 0x0003 /* Control write data stage */ +#define CS_RDSS 0x0002 /* Control read status stage */ +#define CS_RDDS 0x0001 /* Control read data stage */ +#define CS_IDST 0x0000 /* Idle or setup stage */ /* Interrupt Status Register 1 */ -#define OVRCR 0x8000 /* b15: Over-current interrupt */ -#define BCHG 0x4000 /* b14: USB bus chenge interrupt */ -#define DTCH 0x1000 /* b12: Detach sense interrupt */ -#define ATTCH 0x0800 /* b11: Attach sense interrupt */ -#define EOFERR 0x0040 /* b6: EOF-error interrupt */ -#define SIGN 0x0020 /* b5: Setup ignore interrupt */ -#define SACK 0x0010 /* b4: Setup acknowledge interrupt */ +#define OVRCR 0x8000 /* b15: Over-current interrupt */ +#define BCHG 0x4000 /* b14: USB bus chenge interrupt */ +#define DTCH 0x1000 /* b12: Detach sense interrupt */ +#define ATTCH 0x0800 /* b11: Attach sense interrupt */ +#define EOFERR 0x0040 /* b6: EOF-error interrupt */ +#define SIGN 0x0020 /* b5: Setup ignore interrupt */ +#define SACK 0x0010 /* b4: Setup acknowledge interrupt */ /* Frame Number Register */ -#define OVRN 0x8000 /* b15: Overrun error */ -#define CRCE 0x4000 /* b14: Received data error */ -#define FRNM 0x07FF /* b10-0: Frame number */ +#define OVRN 0x8000 /* b15: Overrun error */ +#define CRCE 0x4000 /* b14: Received data error */ +#define FRNM 0x07FF /* b10-0: Frame number */ /* Micro Frame Number Register */ -#define UFRNM 0x0007 /* b2-0: Micro frame number */ +#define UFRNM 0x0007 /* b2-0: Micro frame number */ /* Default Control Pipe Maxpacket Size Register */ /* Pipe Maxpacket Size Register */ -#define DEVSEL 0xF000 /* b15-14: Device address select */ -#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ +#define DEVSEL 0xF000 /* b15-14: Device address select */ +#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ /* Default Control Pipe Control Register */ -#define BSTS 0x8000 /* b15: Buffer status */ -#define SUREQ 0x4000 /* b14: Send USB request */ -#define CSCLR 0x2000 /* b13: complete-split status clear */ -#define CSSTS 0x1000 /* b12: complete-split status */ -#define SUREQCLR 0x0800 /* b11: stop setup request */ -#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ -#define SQSET 0x0080 /* b7: Sequence toggle bit set */ -#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ -#define PBUSY 0x0020 /* b5: pipe busy */ -#define PINGE 0x0010 /* b4: ping enable */ -#define CCPL 0x0004 /* b2: Enable control transfer complete */ -#define PID 0x0003 /* b1-0: Response PID */ -#define PID_STALL11 0x0003 /* STALL */ -#define PID_STALL 0x0002 /* STALL */ -#define PID_BUF 0x0001 /* BUF */ -#define PID_NAK 0x0000 /* NAK */ +#define BSTS 0x8000 /* b15: Buffer status */ +#define SUREQ 0x4000 /* b14: Send USB request */ +#define CSCLR 0x2000 /* b13: complete-split status clear */ +#define CSSTS 0x1000 /* b12: complete-split status */ +#define SUREQCLR 0x0800 /* b11: stop setup request */ +#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ +#define SQSET 0x0080 /* b7: Sequence toggle bit set */ +#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ +#define PBUSY 0x0020 /* b5: pipe busy */ +#define PINGE 0x0010 /* b4: ping enable */ +#define CCPL 0x0004 /* b2: Enable control transfer complete */ +#define PID 0x0003 /* b1-0: Response PID */ +#define PID_STALL11 0x0003 /* STALL */ +#define PID_STALL 0x0002 /* STALL */ +#define PID_BUF 0x0001 /* BUF */ +#define PID_NAK 0x0000 /* NAK */ /* Pipe Window Select Register */ -#define PIPENM 0x0007 /* b2-0: Pipe select */ +#define PIPENM 0x0007 /* b2-0: Pipe select */ /* Pipe Configuration Register */ -#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ -#define R8A66597_ISO 0xC000 /* Isochronous */ -#define R8A66597_INT 0x8000 /* Interrupt */ -#define R8A66597_BULK 0x4000 /* Bulk */ -#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ -#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ -#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ -#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ -#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ -#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ +#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ +#define R8A66597_ISO 0xC000 /* Isochronous */ +#define R8A66597_INT 0x8000 /* Interrupt */ +#define R8A66597_BULK 0x4000 /* Bulk */ +#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ +#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ +#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ +#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ +#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ +#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ /* Pipe Buffer Configuration Register */ -#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ -#define BUFNMB 0x007F /* b6-0: Pipe buffer number */ -#define PIPE0BUF 256 -#define PIPExBUF 64 +#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ +#define BUFNMB 0x007F /* b6-0: Pipe buffer number */ +#define PIPE0BUF 256 +#define PIPExBUF 64 /* Pipe Maxpacket Size Register */ -#define MXPS 0x07FF /* b10-0: Maxpacket size */ +#define MXPS 0x07FF /* b10-0: Maxpacket size */ /* Pipe Cycle Configuration Register */ -#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ -#define IITV 0x0007 /* b2-0: Isochronous interval */ +#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ +#define IITV 0x0007 /* b2-0: Isochronous interval */ /* Pipex Control Register */ -#define BSTS 0x8000 /* b15: Buffer status */ -#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ -#define CSCLR 0x2000 /* b13: complete-split status clear */ -#define CSSTS 0x1000 /* b12: complete-split status */ -#define ATREPM 0x0400 /* b10: Auto repeat mode */ -#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ -#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ -#define SQSET 0x0080 /* b7: Sequence toggle bit set */ -#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ -#define PBUSY 0x0020 /* b5: pipe busy */ -#define PID 0x0003 /* b1-0: Response PID */ +#define BSTS 0x8000 /* b15: Buffer status */ +#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ +#define CSCLR 0x2000 /* b13: complete-split status clear */ +#define CSSTS 0x1000 /* b12: complete-split status */ +#define ATREPM 0x0400 /* b10: Auto repeat mode */ +#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ +#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ +#define SQSET 0x0080 /* b7: Sequence toggle bit set */ +#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ +#define PBUSY 0x0020 /* b5: pipe busy */ +#define PID 0x0003 /* b1-0: Response PID */ /* PIPExTRE */ -#define TRENB 0x0200 /* b9: Transaction counter enable */ -#define TRCLR 0x0100 /* b8: Transaction counter clear */ +#define TRENB 0x0200 /* b9: Transaction counter enable */ +#define TRCLR 0x0100 /* b8: Transaction counter clear */ /* PIPExTRN */ -#define TRNCNT 0xFFFF /* b15-0: Transaction counter */ +#define TRNCNT 0xFFFF /* b15-0: Transaction counter */ /* DEVADDx */ -#define UPPHUB 0x7800 -#define HUBPORT 0x0700 -#define USBSPD 0x00C0 -#define RTPORT 0x0001 +#define UPPHUB 0x7800 +#define HUBPORT 0x0700 +#define USBSPD 0x00C0 +#define RTPORT 0x0001 /* Suspend Mode Register */ -#define SUSPM 0x4000 /* b14: Suspend */ +#define SUSPM 0x4000 /* b14: Suspend */ #define R8A66597_MAX_NUM_PIPE 10 #define R8A66597_BUF_BSIZE 8 @@ -387,9 +387,7 @@ #define BULK_OUT_PIPENUM 4 #define BULK_OUT_BUFNUM 40 -#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) -#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) -#define make_devsel(addr) (addr << 12) +#define make_devsel(addr) ((addr) << 12) struct r8a66597 { unsigned long reg; @@ -420,6 +418,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, if (len & 0x00000003) { unsigned long tmp = readl(fifoaddr); + memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); } } @@ -459,6 +458,7 @@ static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, u16 val, u16 pat, unsigned long offset) { u16 tmp; + tmp = r8a66597_read(r8a66597, offset); tmp = tmp & (~pat); tmp = tmp | val; @@ -523,7 +523,6 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) #define get_devadd_addr(address) (DEVADD0 + address * 2) - /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */ /* destination of request */ @@ -606,11 +605,11 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_PSM BIT(8) /* power switching mode */ +#define RH_A_NPS BIT(9) /* no power switching */ +#define RH_A_DT BIT(10) /* device type (mbz) */ +#define RH_A_OCPM BIT(11) /* over current protection mode */ +#define RH_A_NOCP BIT(12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ #endif /* __R8A66597_H__ */ From 769a9cd4bbd7ae9b8170b3dd6ba54b84fde59224 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Aug 2019 17:53:04 +0200 Subject: [PATCH 09/10] usb: r8a66597: Add optional DM VBUS regulator support Add DM regulator support for toggling VBUS, this is useful on boards which control the VBUS e.g. through GPIO. Signed-off-by: Marek Vasut Cc: Chris Brandt --- drivers/usb/host/r8a66597-hcd.c | 29 +++++++++++++++++++++++++++++ drivers/usb/host/r8a66597.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 8b60ab2c6d..a37696d83f 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "r8a66597.h" @@ -818,9 +819,27 @@ static int r8a66597_usb_probe(struct udevice *dev) { struct r8a66597 *priv = dev_get_priv(dev); struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); + int ret; bus_priv->desc_before_addr = true; + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret) { + dev_err(dev, + "can't get VBUS supply\n"); + return ret; + } + + ret = regulator_set_enable(priv->vbus_supply, true); + if (ret) { + dev_err(dev, + "can't enable VBUS supply\n"); + return ret; + } + } + disable_controller(priv); mdelay(100); @@ -838,9 +857,19 @@ static int r8a66597_usb_probe(struct udevice *dev) static int r8a66597_usb_remove(struct udevice *dev) { struct r8a66597 *priv = dev_get_priv(dev); + int ret; disable_controller(priv); + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + ret = regulator_set_enable(priv->vbus_supply, false); + if (ret) { + dev_err(dev, + "can't disable VBUS supply\n"); + return ret; + } + } + return 0; } diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 3077bc7999..b6110d6b3f 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h @@ -396,6 +396,7 @@ struct r8a66597 { unsigned short port_change; u16 speed; /* HSMODE or FSMODE or LSMODE */ unsigned char rh_devnum; + struct udevice *vbus_supply; }; static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) From be1e9dc0800a9d44514a0c640ded0bd70400ddc6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 11 Aug 2019 13:22:32 +0200 Subject: [PATCH 10/10] ARM: renesas: Enable R8A66597 USB host on GR Peach Enable USB host support on GR Peach board. To use USB host on GR Peach, it might be necessary to solder JP3 header onto the board first and then short it. Shorting JP3 is mandatory to let the U5 regulator to supply VBUS to the CN3 USB port. Signed-off-by: Marek Vasut Cc: Chris Brandt --- arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 14 ++++++++++++++ configs/grpeach_defconfig | 9 ++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts index 28247d19d7..30e35e47d6 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts @@ -37,6 +37,15 @@ }; }; + reg_usbhs0_vbus: regulator-usbhs0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbhs0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&port4 1 GPIO_ACTIVE_LOW>; + }; + + rpc: rpc@0xee200000 { compatible = "renesas,rpc-r7s72100", "renesas,rpc"; reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; @@ -76,3 +85,8 @@ &scif2_pins { u-boot,dm-pre-reloc; }; + +&usbhs0 { + vbus-supply = <®_usbhs0_vbus>; + status = "okay"; +}; diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 32254b3b0e..adabfbc085 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -10,6 +10,7 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -30,7 +31,7 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_USE_ENV_SPI_MODE=y CONFIG_ENV_SPI_MODE=0x0 CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_BLK=y CONFIG_DM_GPIO=y CONFIG_RZA1_GPIO=y CONFIG_LED=y @@ -43,11 +44,17 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_DM_ETH=y CONFIG_SH_ETHER=y CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y CONFIG_TIMER=y CONFIG_RENESAS_OSTM_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_R8A66597_HCD=y +CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set