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powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
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@ -244,6 +244,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
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puts("Work-around for Erratum A006593 enabled\n");
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puts("Work-around for Erratum A006593 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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puts("Work-around for Erratum A-005812 enabled\n");
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#endif
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#endif
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return 0;
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return 0;
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}
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}
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@ -399,6 +399,14 @@ int cpu_init_r(void)
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sync();
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sync();
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}
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}
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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/*
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* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
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* in write shadow mode. Checking DCWS before setting SPR 976.
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*/
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if (mfspr(L1CSR2) & L1CSR2_DCWS)
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mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
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#endif
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#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
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#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
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spin = getenv("spin_table_compat");
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spin = getenv("spin_table_compat");
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@ -226,6 +226,21 @@ __secondary_start_page:
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2:
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2:
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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/*
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* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
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* write shadow mode. This code should run after other code setting
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* DCWS.
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*/
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mfspr r3,L1CSR2
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andis. r3,r3,(L1CSR2_DCWS)@h
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beq 1f
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mfspr r3, SPRN_HDBCR0
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oris r3, r3, 0x8000
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mtspr SPRN_HDBCR0, r3
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1:
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#endif
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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/* skip L2 setup on P2040/P2040E as they have no L2 */
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/* skip L2 setup on P2040/P2040E as they have no L2 */
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mfspr r3,SPRN_SVR
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mfspr r3,SPRN_SVR
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@ -368,6 +368,7 @@
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_A005812
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#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
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#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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@ -413,6 +414,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_A004580
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#define CONFIG_SYS_FSL_ERRATUM_A004580
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#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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#define CONFIG_SYS_FSL_ERRATUM_A005812
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#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
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#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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@ -474,6 +476,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_ERRATUM_A005812
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#elif defined(CONFIG_BSC9131)
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#elif defined(CONFIG_BSC9131)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_MAX_CPUS 1
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