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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

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This commit is contained in:
Tom Rini 2020-04-20 08:45:27 -04:00
commit d1bbf833aa
92 changed files with 3152 additions and 491 deletions
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11
arch/arm/dts/Makefile
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@ -620,12 +620,14 @@ dtb-y += \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-mba6a.dtb \
imx6dl-mba6b.dtb \
imx6dl-mamoj.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-pico.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revb1.dtb \
imx6dl-wandboard-revd1.dtb \
endif
@ -649,6 +651,8 @@ dtb-y += \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
imx6q-novena.dtb \
@ -657,7 +661,7 @@ dtb-y += \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-tbs2910.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
imx6qp-wandboard-revd1.dtb \
@ -728,7 +732,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-evk.dtb \
imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \

7
arch/arm/dts/imx53-kp-u-boot.dtsi
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@ -5,6 +5,13 @@
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
&fec {
fixed-link { /* RMII fixed link for both HSC|DDC */
speed = <100>;
full-duplex;
};
};
&pmic {
u-boot,i2c-transaction-bytes = <3>;
};

6
arch/arm/dts/imx6dl-dhcom-pdk2-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
#include "imx6qdl-dhcom-pdk2-u-boot.dtsi"

18
arch/arm/dts/imx6dl-mba6.dtsi Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <0>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <300>;
txd0-skew-ps = <120>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};

16
arch/arm/dts/imx6dl-mba6a.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6a", "tq,tqma6dl", "fsl,imx6dl";
};

16
arch/arm/dts/imx6dl-mba6b.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S on MBa6x";
compatible = "tq,mba6b", "tq,tqma6dl", "fsl,imx6dl";
};

14
arch/arm/dts/imx6dl-tqma6a.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x20000000>;
};
};

14
arch/arm/dts/imx6dl-tqma6b.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6dl.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x20000000>;
};
};

4
arch/arm/dts/imx6dl-wandboard-revb1.dts → arch/arm/dts/imx6dl-wandboard-revd1.dts
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@ -6,10 +6,10 @@
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
#include "imx6qdl-wandboard-revd1.dtsi"
/ {
model = "Wandboard i.MX6 Dual Lite Board rev B1";
model = "Wandboard i.MX6 Dual Lite Board revD1";
compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
memory@10000000 {

2
arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi
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@ -3,6 +3,8 @@
* Copyright (C) 2019 Claudius Heine <ch@denx.de>
*/
#include "imx6qdl-dhcom-pdk2-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";

18
arch/arm/dts/imx6q-mba6.dtsi Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <120>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <180>;
txd0-skew-ps = <360>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};

16
arch/arm/dts/imx6q-mba6a.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6a", "fsl,imx6q";
};

16
arch/arm/dts/imx6q-mba6b.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,mba6b", "fsl,imx6q";
};

14
arch/arm/dts/imx6q-tqma6a.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6q.dtsi"
#include "imx6qdl-tqma6a.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x40000000>;
};
};

14
arch/arm/dts/imx6q-tqma6b.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
#include "imx6q.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"
/ {
memory {
reg = <0x10000000 0x40000000>;
};
};

4
arch/arm/dts/imx6q-wandboard-revb1.dts → arch/arm/dts/imx6q-wandboard-revd1.dts
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@ -6,10 +6,10 @@
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-wandboard-revb1.dtsi"
#include "imx6qdl-wandboard-revd1.dtsi"
/ {
model = "Wandboard i.MX6 Quad Board rev B1";
model = "Wandboard i.MX6 Quad Board revD1";
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
memory@10000000 {

23
arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi Normal file
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@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
#include "imx6qdl-dhcom-u-boot.dtsi"
/ {
fec_vio: regulator-fec {
compatible = "regulator-fixed";
regulator-name = "fec-vio";
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
};
&fec {
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;
phy-supply = <&fec_vio>;
};

9
arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
*/
&reg_usb_otg_vbus {
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

207
arch/arm/dts/imx6qdl-mba6.dtsi Normal file
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@ -0,0 +1,207 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/ {
aliases {
mmc1 = &usdhc2;
};
chosen {
linux,stdout-path = &uart2;
stdout-path = &uart2;
};
regulators {
reg_mba6_3p3v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "supply-mba6-3p3v";
reg = <1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_otgvbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_otgpwr>;
regulator-name = "otg-vbus-supply";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin_supply = <&reg_3p3v>;
};
};
};
&fec {
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <100>;
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
reg = <3>;
force-master;
max-speed = <1000>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
mba6 {
pinctrl_enet: enetgrp {
fsl,pins = <
/* FEC phy IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
/* FEC phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
/* DSE = 100, 100k up, SPEED = MED */
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
/* DSE = 111, pull 100k up */
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
/* DSE = 111, pull external */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */
/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
>;
};
pinctrl_reg_otgpwr: regotgpwrgrp {
fsl,pins = <
/* OTG_PWR */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
>;
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "otg";
vbus-supply = <&reg_otgvbus>;
status = "okay";
};
&usdhc2 { /* Baseboard Slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_mba6_3p3v>;
bus-width = <4>;
no-1-8-v;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wdog1 {
status = "okay";
};

39
arch/arm/dts/imx6qdl-mba6a.dtsi Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c1 {
sensor1: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};

45
arch/arm/dts/imx6qdl-mba6b.dtsi Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c3 {
sensor1: lm75@49 {
compatible = "lm75";
reg = <0x49>;
};
eeprom1: m24c64@57 {
compatible = "st,24c64", "at24";
reg = <0x57>;
pagesize = <32>;
};
rtc1: ds1339@68 {
compatible = "ds1339";
reg = <0x68>;
};
};
&iomuxc {
mba6 {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
};
};

211
arch/arm/dts/imx6qdl-tqma6.dtsi Normal file
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@ -0,0 +1,211 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
/ {
aliases {
mmc0 = &usdhc3;
/delete-property/ mmc1;
/delete-property/ mmc2;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
reg = <0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
status = "okay";
flash: m25p80@0 {
status = "okay";
compatible = "micron,n25q128a13", "n25q128a13";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
m25p,fast-read;
};
};
&iomuxc {
tqma6 {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
/* eCSPI1 SS1 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
>;
};
pinctrl_i2c1_tqma6: i2c1-tqma6grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
pinctrl_i2c3_tqma6: i2c3-tqma6grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
};
&pmic {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio6>;
interrupts = <10 8>;
regulators {
reg_vddcore: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_vddsoc: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
reg_gen_3v3: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_ddr_1v5a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
reg_ddr_1v5b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5v_600mA: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-always-on;
};
reg_snvs_3v: vsnvs {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
reg_vrefddr: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1_1v5: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
/* not used */
};
reg_vgen2_1v2_eth: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
reg_vgen3_2v8: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen4_1v8: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5_1v8_eth: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6_3v3: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
non-removable;
disable-wp;
bus-width = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mmccard: mmccard@0 {
reg = <0>;
compatible = "mmc-card";
broken-hpi;
};
};

27
arch/arm/dts/imx6qdl-tqma6a.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_tqma6>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
reg = <0x50>;
pagesize = <32>;
};
};

27
arch/arm/dts/imx6qdl-tqma6b.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_tqma6>;
clock-frequency = <100000>;
status = "okay";
pmic: pf0100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
};
sensor0: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
eeprom0: m24c64@50 {
compatible = "st,24c64", "at24";
reg = <0x50>;
pagesize = <32>;
};
};

44
arch/arm/dts/imxrt1020-evk-u-boot.dtsi Normal file
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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
/ {
chosen {
u-boot,dm-spl;
};
};
&lpuart1 { /* console */
u-boot,dm-spl;
};
&semc {
bank1: bank@0 {
u-boot,dm-spl;
};
};
&iomuxc {
u-boot,dm-spl;
imxrt1020-evk {
u-boot,dm-spl;
pinctrl_lpuart1: lpuart1grp {
u-boot,dm-spl;
};
pinctrl_semc: semcgrp {
u-boot,dm-spl;
};
pinctrl_usdhc0: usdhc0grp {
u-boot,dm-spl;
};
};
};
&usdhc1 {
u-boot,dm-spl;
};

198
arch/arm/dts/imxrt1020-evk.dts Normal file
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@ -0,0 +1,198 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
#include <dt-bindings/pinctrl/pins-imxrt1020.h>
/ {
model = "NXP IMXRT1020-evk board";
compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x80000000 0x2000000>;
};
};
&lpuart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&semc {
/*
* Memory configuration from sdram datasheet IS42S16160J-6TLI
*/
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS1
0
0
0
0>;
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8
COL_9BITS
CL_3>;
fsl,sdram-timing = /bits/ 8 <0x2
0x2
0x9
0x1
0x5
0x6
0x20
0x09
0x01
0x00
0x04
0x0A
0x21
0x50>;
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
imxrt1020-evk {
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
0xf1
MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
0xf1
>;
};
pinctrl_semc: semcgrp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
0xf1 /* SEMC_CAS */
MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
0xf1 /* SEMC_RAS */
MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
0xf1 /* SEMC_CS0 */
MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
0xf1 /* SEMC_BA0 */
MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
0xf1 /* SEMC_BA1 */
MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
0xf1 /* SEMC_A10 */
MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
0xf1 /* SEMC_A1 */
MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
0xf1 /* SEMC_A2 */
MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
0xf1 /* SEMC_A3 */
MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
0xf1 /* SEMC_A4 */
MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
0xf1 /* SEMC_A5 */
MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
0xf1 /* SEMC_A6 */
MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
0xf1 /* SEMC_A7 */
MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
0xf1 /* SEMC_A8 */
MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
0xf1 /* SEMC_A9 */
MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
0xf1 /* SEMC_A11 */
MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
0xf1 /* SEMC_A12 */
MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
0xf1 /* SEMC_CKE */
MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
0xf1 /* SEMC_CLK */
MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
0xf1 /* SEMC_DM01 */
MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
0xf1 /* SEMC_D8 */
MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
0xf1 /* SEMC_D9 */
MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
0xf1 /* SEMC_D10 */
MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
0xf1 /* SEMC_D11 */
MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
0xf1 /* SEMC_D12 */
MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
0xf1 /* SEMC_D13 */
MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
0xf1 /* SEMC_D14 */
MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
0xf1 /* SEMC_D15 */
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
0x1B000
MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
0x17061
MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
0x17061
>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
status = "okay";
cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};

133
arch/arm/dts/imxrt1020.dtsi Normal file
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@ -0,0 +1,133 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1020-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
mmc0 = &usdhc1;
serial0 = &lpuart1;
};
clocks {
u-boot,dm-spl;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
soc {
u-boot,dm-spl;
semc: semc@402f0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1020_CLK_SEMC>;
pinctrl-0 = <&pinctrl_semc>;
pinctrl-names = "default";
status = "okay";
};
lpuart1: serial@40184000 {
compatible = "fsl,imxrt-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1020_CLK_LPUART1>;
clock-names = "per";
status = "disabled";
};
iomuxc: iomuxc@401f8000 {
compatible = "fsl,imxrt-iomuxc";
reg = <0x401f8000 0x4000>;
fsl,mux_mask = <0x7>;
};
clks: ccm@400fc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
usdhc1: usdhc@402c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1020_CLK_USDHC1>;
clock-names = "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
gpio1: gpio@401b8000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@401bc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@401c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

60
arch/arm/dts/imxrt1050-evk.dts
View File

@ -185,6 +185,33 @@
0x17061
>;
};
pinctrl_lcdif: lcdifgrp {
u-boot,dm-spl;
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>;
};
};
};
@ -198,3 +225,36 @@
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
status = "okay";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
timing0: timing0 {
clock-frequency = <9300000>;
hactive = <480>;
vactive = <272>;
hback-porch = <4>;
hfront-porch = <8>;
vback-porch = <4>;
vfront-porch = <8>;
hsync-len = <41>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};

14
arch/arm/dts/imxrt1050.dtsi
View File

@ -4,7 +4,6 @@
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
@ -12,7 +11,11 @@
#include <dt-bindings/memory/imxrt-sdram.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
display0 = &lcdif;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@ -142,5 +145,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
lcdif: lcdif@402b8000 {
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF>;
clock-names = "per";
status = "disabled";
};
};
};

6
arch/arm/include/asm/arch-imxrt/imx-regs.h
View File

@ -17,4 +17,10 @@
#define ANATOP_BASE_ADDR 0x400d8000
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#endif
#endif /* __ASM_ARCH_IMX_REGS_H__ */

19
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View File

@ -306,6 +306,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
/*
* NoC scheduler registers - only on IMX6DQP
*/
#define MX6DQP_NOC_SCHED_BASE 0x00bb0000
struct mx6dqp_noc_sched_regs {
u32 coreid;
u32 revid;
u32 ddrconf;
u32 ddrtiming;
u32 ddrmode;
u32 rlat;
u32 res1[4];
u32 ipu1;
u32 ipu2;
u32 res2[2];
u32 activate;
u32 res3[16];
};
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];

6
arch/arm/include/asm/mach-imx/regs-lcdif.h
View File

@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_IMX8M)
defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@ -49,7 +49,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_IMX8M)
defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */

9
arch/arm/mach-imx/imxrt/Kconfig
View File

@ -3,6 +3,10 @@ if ARCH_IMXRT
config IMXRT
bool
config IMXRT1020
bool
select IMXRT
config IMXRT1050
bool
select IMXRT
@ -14,12 +18,17 @@ choice
prompt "NXP i.MXRT board select"
optional
config TARGET_IMXRT1020_EVK
bool "Support imxrt1020 EVK board"
select IMXRT1020
config TARGET_IMXRT1050_EVK
bool "Support imxrt1050 EVK board"
select IMXRT1050
endchoice
source "board/freescale/imxrt1020-evk/Kconfig"
source "board/freescale/imxrt1050-evk/Kconfig"
endif

11
arch/arm/mach-imx/mx6/Kconfig
View File

@ -590,7 +590,18 @@ config TARGET_KP_IMX6Q_TPC
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select MXC_SPI
select SPI
imply DM
imply DM_GPIO
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply DM_I2C
imply CMD_SF
imply CMD_DM
config TARGET_UDOO
bool "udoo"

96
arch/arm/mach-imx/mx6/ddr.c
View File

@ -945,6 +945,27 @@ void mx6sdl_dram_iocfg(unsigned width,
mmdc1->entry = value; \
} while (0)
/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
#define BOOT_CFG3_DDR_MASK 0x30
#define BOOT_CFG3_EXT_DDR_MASK 0x33
#define DDR_MMAP_NOC_SINGLE 0
#define DDR_MMAP_NOC_DUAL 0x31
/* NoC ACTIVATE shifts */
#define NOC_RD_SHIFT 0
#define NOC_FAW_PERIOD_SHIFT 4
#define NOC_FAW_BANKS_SHIFT 10
/* NoC DdrTiming shifts */
#define NOC_ACT_TO_ACT_SHIFT 0
#define NOC_RD_TO_MISS_SHIFT 6
#define NOC_WR_TO_MISS_SHIFT 12
#define NOC_BURST_LEN_SHIFT 18
#define NOC_RD_TO_WR_SHIFT 21
#define NOC_WR_TO_RD_SHIFT 26
#define NOC_BW_RATIO_SHIFT 31
/*
* According JESD209-2B-LPDDR2: Table 103
* WL: write latency
@ -1234,6 +1255,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
{
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@ -1526,6 +1549,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
/*
* Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
* configure it and disable MMDC arbitration/reordering (see EB828)
*/
if (is_mx6dqp() &&
((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
(soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
struct mx6dqp_noc_sched_regs *noc_sched =
(struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
/*
* These values are fixed based on integration parameters and
* should not be modified
*/
noc_sched->rlat = 0x00000040;
noc_sched->ipu1 = 0x00000020;
noc_sched->ipu2 = 0x00000020;
noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
(tfaw << NOC_FAW_PERIOD_SHIFT) |
(trrd << NOC_RD_SHIFT);
noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
<< NOC_BW_RATIO_SHIFT) |
((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
(4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
((tcwl + twr + trp + trcd)
<< NOC_WR_TO_MISS_SHIFT) |
((trtp + trp + trcd - 4)
<< NOC_RD_TO_MISS_SHIFT) |
(trc << NOC_ACT_TO_ACT_SHIFT);
if (sysinfo->dsize == 2) {
if (ddr3_cfg->coladdr == 10) {
if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 4;
else
noc_sched->ddrconf = 0;
} else if (ddr3_cfg->coladdr == 11) {
noc_sched->ddrconf = 1;
}
} else {
if (ddr3_cfg->coladdr == 9) {
if (ddr3_cfg->rowaddr == 13)
noc_sched->ddrconf = 2;
else if (ddr3_cfg->rowaddr == 14)
noc_sched->ddrconf = 15;
} else if (ddr3_cfg->coladdr == 10) {
if (ddr3_cfg->rowaddr == 14 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 14;
else if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 9;
else
noc_sched->ddrconf = 3;
} else if (ddr3_cfg->coladdr == 11) {
if (ddr3_cfg->rowaddr == 15 &&
sysinfo->ncs == 2)
noc_sched->ddrconf = 4;
else
noc_sched->ddrconf = 0;
} else if (ddr3_cfg->coladdr == 12) {
if (ddr3_cfg->rowaddr == 14)
noc_sched->ddrconf = 1;
}
}
/* Disable MMDC arbitration/reordering */
mmdc0->maarcr = 0x14420000;
}
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = 0x00000000;

29
arch/arm/mach-imx/mx7ulp/soc.c
View File

@ -118,12 +118,26 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
return false;
}
#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
unsigned int reg;
if (ldo_mode_is_enabled())
return;
/* Set LDOOKDIS */
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
@ -193,21 +207,6 @@ const char *get_imx_type(u32 imxtype)
return "7ULP";
}
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
#define PMC0_CTRL_LDOEN BIT(31)
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
return false;
}
int print_cpuinfo(void)
{
u32 cpurev;

51
board/dhelectronics/dh_imx6/dh_imx6.c
View File

@ -28,10 +28,7 @@
#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c_eeprom.h>
#include <miiphy.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
@ -52,24 +49,6 @@ int overwrite_console(void)
return 1;
}
#ifdef CONFIG_FEC_MXC
static void eth_phy_reset(void)
{
/* Reset PHY */
gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(5, 0), 1);
/* Enable VIO */
gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
/*
* KSZ9021 PHY needs at least 10 mSec after PHY reset
* is released to stabilize
*/
mdelay(10);
}
static int setup_fec_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -80,34 +59,6 @@ static int setup_fec_clock(void)
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
gpio_request(IMX_GPIO_NR(1, 7), "VIO");
setup_fec_clock();
eth_phy_reset();
bus = fec_get_miibus(base, -1);
if (!bus)
return -EINVAL;
/* Scan PHY 0 */
phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("Ethernet PHY not found!\n");
return -EINVAL;
}
return fec_probe(bis, -1, base, bus, phydev);
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
@ -190,6 +141,8 @@ int board_init(void)
setup_dhcom_mac_from_fuse();
setup_fec_clock();
return 0;
}

6
board/freescale/imx8mm_evk/imx8mm_evk.c
View File

@ -15,7 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}

18
board/freescale/imx8qxp_mek/spl.c
View File

@ -12,9 +12,24 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19)
static iomux_cfg_t usdhc2_sd_pwr[] = {
SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
void spl_board_init(void)
{
struct udevice *dev;
@ -32,6 +47,9 @@ void spl_board_init(void)
timer_init();
imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
gpio_direction_output(USDHC2_SD_PWR, 0);
preloader_console_init();
puts("Normal Boot\n");

22
board/freescale/imxrt1020-evk/Kconfig Normal file
View File

@ -0,0 +1,22 @@
if TARGET_IMXRT1020_EVK
config SYS_BOARD
string
default "imxrt1020-evk"
config SYS_VENDOR
string
default "freescale"
config SYS_SOC
string
default "imxrt1020"
config SYS_CONFIG_NAME
string
default "imxrt1020-evk"
config IMX_CONFIG
default "board/freescale/imxrt1020-evk/imximage.cfg"
endif

6
board/freescale/imxrt1020-evk/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
IMXRT1020 EVALUATION KIT
M: Giulio Benetti <giulio.benetti@benettiengineering.com>
S: Maintained
F: board/freescale/imxrt1020-evk
F: include/configs/imxrt1020-evk.h
F: configs/imxrt1020-evk_defconfig

6
board/freescale/imxrt1020-evk/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020
# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
obj-y := imxrt1020-evk.o

31
board/freescale/imxrt1020-evk/README Normal file
View File

@ -0,0 +1,31 @@
How to use U-Boot on NXP i.MXRT1020 EVK
-----------------------------------------------
- Build U-Boot for i.MXRT1020 EVK:
$ make mrproper
$ make imxrt1020-evk_defconfig
$ make
This will generate the SPL image called SPL and the u-boot.img.
- Flash the SPL image into the micro SD card:
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- Flash the u-boot.img image into the micro SD card:
sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
- Jumper settings:
SW8: 0 1 1 0
where 0 means bottom position and 1 means top position (from the
switch label numbers reference).
- Connect the USB cable between the EVK and the PC for the console.
(The USB console connector is the one close the ethernet connector)
- Insert the micro SD card in the board, power it up and U-Boot messages should
come up.

36
board/freescale/imxrt1020-evk/imximage.cfg Normal file
View File

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Set all FlexRAM as OCRAM(01b) */
DATA 4 0x400AC044 0x00005555
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
SET_BIT 4 0x400AC040 0x4

81
board/freescale/imxrt1020-evk/imxrt1020-evk.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <common.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/armv7m.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifndef CONFIG_SUPPORT_SPL
int rv;
struct udevice *dev;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
debug("DRAM init failed: %d\n", rv);
return rv;
}
#endif
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
debug("SPL: booting kernel\n");
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
int spl_dram_init(void)
{
struct udevice *dev;
int rv;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv)
debug("DRAM init failed: %d\n", rv);
return rv;
}
void spl_board_init(void)
{
spl_dram_init();
preloader_console_init();
arch_cpu_init(); /* to configure mpu for sdram rw permissions */
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
#endif
u32 get_board_rev(void)
{
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}

50
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
View File

@ -196,56 +196,6 @@ int board_ehci_hcd_init(int port)
#endif
#ifdef CONFIG_FEC_MXC
/*
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
* be used for ENET1 or ENET2, cannot be used for both.
*/
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
{
if (fec_id == 0)
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
}
int board_eth_init(bd_t *bis)
{
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
}
static int setup_fec(int fec_id)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

47
board/freescale/mx6ullevk/mx6ullevk.c
View File

@ -19,6 +19,7 @@
#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@ -60,11 +61,57 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_FEC_MXC
static int setup_fec(int fec_id)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (fec_id == 0) {
/*
* Use 50MHz anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
/*
* Use 50MHz anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
}
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
return 0;
}

2
board/k+p/kp_imx53/kp_imx53.c
View File

@ -48,7 +48,7 @@ static int power_init(void)
struct udevice *dev;
int ret;
ret = pmic_get("mc34708", &dev);
ret = pmic_get("mc34708@8", &dev);
if (ret) {
printf("%s: mc34708 not found !\n", __func__);
return ret;

7
board/toradex/verdin-imx8mm/verdin-imx8mm.c
View File

@ -5,6 +5,7 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
@ -13,7 +14,11 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}

15
board/tqc/tqma6/Kconfig
View File

@ -63,6 +63,17 @@ choice
config MBA6
bool "TQMa6 on MBa6 Starterkit"
select DM_ETH
select USB
select DM_USB
select CMD_USB
select USB_STORAGE
select USB_HOST_ETHER
select USB_ETHER_SMSC95XX
select PHYLIB
select PHY_MICREL
select PHY_MICREL_KSZ90X1
select MXC_UART
help
Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
etc.
@ -74,6 +85,10 @@ config WRU4
endchoice
config SYS_TEXT_BASE
default 0x2fc00000 if TQMA6S
default 0x4fc00000 if TQMA6Q || TQMA6DL
config IMX_CONFIG
default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL

12
board/tqc/tqma6/tqma6.c
View File

@ -60,6 +60,7 @@ int dram_init(void)
static const uint16_t tqma6_emmc_dsr = 0x0100;
#ifndef CONFIG_DM_MMC
/* eMMC on USDHCI3 always present */
static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
@ -132,7 +133,9 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif
#ifndef CONFIG_DM_SPI
static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
/* SS1 */
NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
@ -164,7 +167,9 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
(cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
}
#endif
#endif
#ifdef CONFIG_SYS_I2C
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
@ -194,6 +199,7 @@ static void tqma6_setup_i2c(void)
if (ret)
printf("setup I2C3 failed: %d\n", ret);
}
#endif
int board_early_init_f(void)
{
@ -205,8 +211,12 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifndef CONFIG_DM_SPI
tqma6_iomuxc_spi();
#endif
#ifdef CONFIG_SYS_I2C
tqma6_setup_i2c();
#endif
tqma6_bb_board_init();
@ -235,6 +245,7 @@ static const char *tqma6_get_boardname(void)
};
}
#ifdef CONFIG_POWER
/* setup board specific PMIC */
int power_init_board(void)
{
@ -251,6 +262,7 @@ int power_init_board(void)
return 0;
}
#endif
int board_late_init(void)
{

171
board/tqc/tqma6/tqma6_mba6.c
View File

@ -68,13 +68,6 @@
#endif
#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_34ohm)
#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_60ohm)
/* disable on die termination for RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
@ -82,34 +75,6 @@
/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
static iomux_v3_cfg_t const mba6_enet_pads[] = {
NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
ENET_TX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
/*
* these pins are also used for config strapping by phy
*/
NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
ENET_RX_PAD_CTRL),
/* KSZ9031 PHY Reset */
NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
};
static void mba6_setup_iomuxc_enet(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -121,22 +86,6 @@ static void mba6_setup_iomuxc_enet(void)
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
ARRAY_SIZE(mba6_enet_pads));
/* Reset PHY */
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
/* Need delay 10ms after power on according to KSZ9031 spec */
mdelay(10);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
/*
* KSZ9031 manual: 100 usec wait time after reset before communication
* over MDIO
* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
* reset before the phy sees a high level
*/
mdelay(15);
}
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
@ -150,91 +99,14 @@ static void mba6_setup_iomuxc_uart(void)
ARRAY_SIZE(mba6_uart2_pads));
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
int board_mmc_get_env_dev(int devno)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = gpio_get_value(USDHC2_WP_GPIO);
return ret;
}
static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
.esdhc_base = USDHC2_BASE_ADDR,
.max_bus_width = 4,
};
static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
/* CD */
NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
/* WP */
NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
};
int tqma6_bb_board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
ARRAY_SIZE(mba6_usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
gpio_direction_input(USDHC2_WP_GPIO);
mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
puts("Warning: failed to initialize SD\n");
return 0;
}
static struct i2c_pads_info mba6_i2c1_pads = {
/* I2C1: MBa6x */
.scl = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
I2C_PAD_CTRL),
.gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 26)
}
};
static void mba6_setup_i2c(void)
{
int ret;
/*
* use logical index for bus, e.g. I2C1 -> 0
* warn on error
* This assumes that the baseboard registered
* the boot device first ...
* Note: SDHC3 == idx2
*/
ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
if (ret)
printf("setup I2C1 failed: %d\n", ret);
return (2 == devno) ? 0 : 1;
}
int board_phy_config(struct phy_device *phydev)
@ -284,37 +156,6 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
bus = fec_get_miibus(base, -1);
if (!bus)
return -EINVAL;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
ret = -EINVAL;
goto free_bus;
}
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret)
goto free_phydev;
return 0;
free_phydev:
free(phydev);
free_bus:
free(bus);
return ret;
}
int tqma6_bb_board_early_init_f(void)
{
mba6_setup_iomuxc_uart();
@ -324,8 +165,6 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void)
{
mba6_setup_i2c();
/* do it here - to have reset completed */
mba6_setup_iomuxc_enet();
return 0;

29
board/wandboard/wandboard.c
View File

@ -369,7 +369,7 @@ int power_init_board(void)
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
if (reg < 0) {
printf("pmic_reg_read() ret %d\n", reg);
debug("pmic_reg_read() ret %d\n", reg);
return 0;
}
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
@ -404,6 +404,7 @@ static const struct boot_mode board_boot_modes[] = {
static bool is_revc1(void)
{
SETUP_IOMUX_PADS(rev_detection_pad);
gpio_request(REV_DETECTION, "REV_DETECT");
gpio_direction_input(REV_DETECTION);
if (gpio_get_value(REV_DETECTION))
@ -442,6 +443,14 @@ int board_late_init(void)
env_set("board_name", "B1");
#endif
setup_iomux_enet();
if (is_revd1())
puts("Board: Wandboard rev D1\n");
else if (is_revc1())
puts("Board: Wandboard rev C1\n");
else
puts("Board: Wandboard rev B1\n");
return 0;
}
@ -466,31 +475,17 @@ int board_init(void)
return 0;
}
int checkboard(void)
{
gpio_request(REV_DETECTION, "REV_DETECT");
if (is_revd1())
puts("Board: Wandboard rev D1\n");
else if (is_revc1())
puts("Board: Wandboard rev C1\n");
else
puts("Board: Wandboard rev B1\n");
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq()) {
if (!strcmp(name, "imx6q-wandboard-revb1"))
if (!strcmp(name, "imx6q-wandboard-revd1"))
return 0;
} else if (is_mx6dqp()) {
if (!strcmp(name, "imx6qp-wandboard-revd1"))
return 0;
} else if (is_mx6dl() || is_mx6solo()) {
if (!strcmp(name, "imx6dl-wandboard-revb1"))
if (!strcmp(name, "imx6dl-wandboard-revd1"))
return 0;
}

2
configs/dh_imx6_defconfig
View File

@ -74,6 +74,8 @@ CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y

67
configs/imxrt1020-evk_defconfig Normal file
View File

@ -0,0 +1,67 @@
CONFIG_ARM=y
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DM_GPIO=y
CONFIG_TARGET_IMXRT1020_EVK=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_SIZE_LIMIT=131072
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x20209000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_SPL_CRC32_SUPPORT is not set
# CONFIG_SPL_DM_GPIO is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_MII is not set
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_TFTP_BLOCKSIZE=512
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMXRT1020=y
CONFIG_CLK_IMXRT1020=y
CONFIG_MXC_GPIO=y
# CONFIG_INPUT is not set
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMXRT=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_IMXRT_SDRAM=y
CONFIG_FSL_LPUART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_HEXDUMP=y

6
configs/imxrt1050-evk_defconfig
View File

@ -1,4 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
CONFIG_SPL_GPIO_SUPPORT=y
@ -17,6 +19,7 @@ CONFIG_SPL_TEXT_BASE=0x20209000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SD_BOOT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@ -62,6 +65,9 @@ CONFIG_IMXRT_SDRAM=y
CONFIG_FSL_LPUART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DM_VIDEO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_HEXDUMP=y

1
configs/kp_imx53_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_FIXED=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y

1
configs/mx6ul_14x14_evk_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PINCTRL=y

8
configs/mx6ull_14x14_evk_defconfig
View File

@ -38,9 +38,17 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y

1
configs/mx6ulz_14x14_evk_defconfig
View File

@ -29,6 +29,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y

31
configs/tqma6dl_mba6_mmc_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x4fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
@ -13,16 +12,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -32,21 +28,26 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

31
configs/tqma6dl_mba6_spi_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x4fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
@ -16,16 +15,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -35,22 +31,27 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

31
configs/tqma6q_mba6_mmc_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x4fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
@ -12,16 +11,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -31,21 +27,26 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

31
configs/tqma6q_mba6_spi_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x4fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
@ -15,16 +14,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -34,22 +30,27 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

31
configs/tqma6s_mba6_mmc_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x2fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
@ -13,16 +12,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -32,21 +28,26 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

31
configs/tqma6s_mba6_spi_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x2fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
@ -16,16 +15,13 @@ CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -35,22 +31,27 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set

9
configs/tqma6s_wru4_mmc_defconfig
View File

@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x2fc00000
CONFIG_TARGET_TQMA6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_TQMA6S=y
@ -16,7 +18,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6s-wru4.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
@ -40,7 +41,9 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_DM is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=0
@ -66,6 +69,8 @@ CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_MII=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y

5
configs/wandboard_defconfig
View File

@ -29,7 +29,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SEPARATE_BSS=y
@ -46,8 +45,8 @@ CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revb1"
CONFIG_OF_LIST="imx6q-wandboard-revb1 imx6qp-wandboard-revd1 imx6dl-wandboard-revb1"
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revd1"
CONFIG_OF_LIST="imx6q-wandboard-revd1 imx6qp-wandboard-revd1 imx6dl-wandboard-revd1"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y

16
drivers/clk/imx/Kconfig
View File

@ -69,6 +69,22 @@ config CLK_IMX8MP
help
This enables support clock driver for i.MX8MP platforms.
config SPL_CLK_IMXRT1020
bool "SPL clock support for i.MXRT1020"
depends on ARCH_IMXRT && SPL
select SPL_CLK
select SPL_CLK_CCF
help
This enables SPL DM/DTS support for clock driver in i.MXRT1020
config CLK_IMXRT1020
bool "Clock support for i.MXRT1020"
depends on ARCH_IMXRT
select CLK
select CLK_CCF
help
This enables support clock driver for i.MXRT1020 platforms.
config SPL_CLK_IMXRT1050
bool "SPL clock support for i.MXRT1050"
depends on ARCH_IMXRT && SPL

1
drivers/clk/imx/Makefile
View File

@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o

227
drivers/clk/imx/clk-imxrt1020.c Normal file
View File

@ -0,0 +1,227 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright(C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <dt-bindings/clock/imxrt1020-clock.h>
#include "clk.h"
static ulong imxrt1020_clk_get_rate(struct clk *clk)
{
struct clk *c;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
ret = clk_get_by_id(clk->id, &c);
if (ret)
return ret;
return clk_get_rate(c);
}
static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *c;
int ret;
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
ret = clk_get_by_id(clk->id, &c);
if (ret)
return ret;
return clk_set_rate(c, rate);
}
static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
{
struct clk *c;
int ret;
debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
ret = clk_get_by_id(clk->id, &c);
if (ret)
return ret;
if (enable)
ret = clk_enable(c);
else
ret = clk_disable(c);
return ret;
}
static int imxrt1020_clk_disable(struct clk *clk)
{
return __imxrt1020_clk_enable(clk, 0);
}
static int imxrt1020_clk_enable(struct clk *clk)
{
return __imxrt1020_clk_enable(clk, 1);
}
static struct clk_ops imxrt1020_clk_ops = {
.set_rate = imxrt1020_clk_set_rate,
.get_rate = imxrt1020_clk_get_rate,
.enable = imxrt1020_clk_enable,
.disable = imxrt1020_clk_disable,
};
static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
static int imxrt1020_clk_probe(struct udevice *dev)
{
void *base;
/* Anatop clocks */
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMXRT1020_CLK_PLL2_SYS,
imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
base + 0x30, 0x1));
clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x1));
/* PLL bypass out */
clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
pll2_bypass_sels,
ARRAY_SIZE(pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
pll3_bypass_sels,
ARRAY_SIZE(pll3_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1020_CLK_PLL3_80M,
imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
/* CCM clocks */
base = dev_read_addr_ptr(dev);
if (base == (void *)FDT_ADDR_T_NONE)
return -EINVAL;
clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
clk_dm(IMXRT1020_CLK_PERIPH_SEL,
imx_clk_mux("periph_sel", base + 0x14, 25, 1,
periph_sels, ARRAY_SIZE(periph_sels)));
clk_dm(IMXRT1020_CLK_USDHC1_SEL,
imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1020_CLK_USDHC2_SEL,
imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1020_CLK_LPUART_SEL,
imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
lpuart_sels, ARRAY_SIZE(lpuart_sels)));
clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
clk_dm(IMXRT1020_CLK_SEMC_SEL,
imx_clk_mux("semc_sel", base + 0x14, 6, 1,
semc_sels, ARRAY_SIZE(semc_sels)));
clk_dm(IMXRT1020_CLK_AHB_PODF,
imx_clk_divider("ahb_podf", "periph_sel",
base + 0x14, 10, 3));
clk_dm(IMXRT1020_CLK_USDHC1_PODF,
imx_clk_divider("usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
clk_dm(IMXRT1020_CLK_USDHC2_PODF,
imx_clk_divider("usdhc2_podf", "usdhc2_sel",
base + 0x24, 16, 3));
clk_dm(IMXRT1020_CLK_LPUART_PODF,
imx_clk_divider("lpuart_podf", "lpuart_sel",
base + 0x24, 0, 6));
clk_dm(IMXRT1020_CLK_SEMC_PODF,
imx_clk_divider("semc_podf", "semc_sel",
base + 0x14, 16, 3));
clk_dm(IMXRT1020_CLK_USDHC1,
imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
clk_dm(IMXRT1020_CLK_USDHC2,
imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
clk_dm(IMXRT1020_CLK_LPUART1,
imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1020_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
#ifdef CONFIG_SPL_BUILD
struct clk *clk, *clk1;
clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
clk_set_parent(clk1, clk);
/* Configure PLL3_USB_OTG to 480MHz */
clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
clk_enable(clk);
clk_set_rate(clk, 480000000UL);
clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
clk_set_parent(clk1, clk);
clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
clk_set_rate(clk, 297000000UL);
clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
clk_enable(clk);
clk_set_rate(clk, 528000000UL);
clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
clk_set_parent(clk1, clk);
#endif
return 0;
}
static const struct udevice_id imxrt1020_clk_ids[] = {
{ .compatible = "fsl,imxrt1020-ccm" },
{ },
};
U_BOOT_DRIVER(imxrt1020_clk) = {
.name = "clk_imxrt1020",
.id = UCLASS_CLK,
.of_match = imxrt1020_clk_ids,
.ops = &imxrt1020_clk_ops,
.probe = imxrt1020_clk_probe,
.flags = DM_FLAG_PRE_RELOC,
};

30
drivers/clk/imx/clk-imxrt1050.c
View File

@ -71,11 +71,30 @@ static int imxrt1050_clk_enable(struct clk *clk)
return __imxrt1050_clk_enable(clk, 1);
}
static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent)
{
struct clk *c, *cp;
int ret;
debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
ret = clk_get_by_id(clk->id, &c);
if (ret)
return ret;
ret = clk_get_by_id(parent->id, &cp);
if (ret)
return ret;
return clk_set_parent(c, cp);
}
static struct clk_ops imxrt1050_clk_ops = {
.set_rate = imxrt1050_clk_set_rate,
.get_rate = imxrt1050_clk_get_rate,
.enable = imxrt1050_clk_enable,
.disable = imxrt1050_clk_disable,
.set_parent = imxrt1050_clk_set_parent,
};
static const char * const pll_ref_sels[] = {"osc", "dummy", };
@ -90,7 +109,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
static int imxrt1050_clk_probe(struct udevice *dev)
{
@ -238,9 +257,9 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_LCDIF,
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
#ifdef CONFIG_SPL_BUILD
struct clk *clk, *clk1;
#ifdef CONFIG_SPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
@ -271,7 +290,14 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
clk_set_parent(clk1, clk);
#else
/* Set PLL5 for LCDIF to its default 650Mhz */
clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk);
clk_enable(clk);
clk_set_rate(clk, 650000000UL);
clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1);
clk_set_parent(clk1, clk);
#endif
return 0;

9
drivers/clk/imx/clk-pllv3.c
View File

@ -25,6 +25,7 @@
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK (0x1 << 31)
struct clk_pllv3 {
@ -32,6 +33,7 @@ struct clk_pllv3 {
void __iomem *base;
u32 power_bit;
bool powerup_set;
u32 enable_bit;
u32 div_mask;
u32 div_shift;
};
@ -83,6 +85,9 @@ static int clk_pllv3_generic_enable(struct clk *clk)
val |= pll->power_bit;
else
val &= ~pll->power_bit;
val |= pll->enable_bit;
writel(val, pll->base);
return 0;
@ -98,6 +103,9 @@ static int clk_pllv3_generic_disable(struct clk *clk)
val &= ~pll->power_bit;
else
val |= pll->power_bit;
val &= ~pll->enable_bit;
writel(val, pll->base);
return 0;
@ -238,6 +246,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
return ERR_PTR(-ENOMEM);
pll->power_bit = BM_PLL_POWER;
pll->enable_bit = BM_PLL_ENABLE;
switch (type) {
case IMX_PLLV3_GENERIC:

2
drivers/power/pmic/pfuze100.c
View File

@ -41,7 +41,7 @@ static int pfuze100_write(struct udevice *dev, uint reg, const uint8_t *buff,
static int pfuze100_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
{
if (dm_i2c_read(dev, reg, buff, len)) {
pr_err("read error from device: %p register: %#x!\n", dev, reg);
debug("read error from device: %p register: %#x!\n", dev, reg);
return -EIO;
}

92
drivers/video/mxsfb.c
View File

@ -5,6 +5,7 @@
* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <env.h>
#include <dm/device_compat.h>
@ -52,14 +53,34 @@ __weak void mxsfb_system_setup(void)
* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
struct display_timing *timings, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
const enum display_flags flags = timings->flags;
uint32_t word_len = 0, bus_width = 0;
uint8_t valid_data = 0;
uint32_t vdctrl0;
#if CONFIG_IS_ENABLED(CLK)
struct clk per_clk;
int ret;
ret = clk_get_by_name(dev, "per", &per_clk);
if (ret) {
dev_err(dev, "Failed to get mxs clk: %d\n", ret);
return;
}
ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
if (ret < 0) {
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
#endif
/* Restart the LCDIF block */
mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
@ -96,25 +117,36 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
mxsfb_system_setup();
writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
&regs->hw_lcdif_transfer_count);
writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
timings->hactive.typ, &regs->hw_lcdif_transfer_count);
writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
mode->vsync_len, &regs->hw_lcdif_vdctrl0);
writel(mode->upper_margin + mode->lower_margin +
mode->vsync_len + mode->yres,
vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
timings->vsync_len.typ;
if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
if(flags & DISPLAY_FLAGS_DE_HIGH)
vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
writel(timings->vback_porch.typ + timings->vfront_porch.typ +
timings->vsync_len.typ + timings->vactive.typ,
&regs->hw_lcdif_vdctrl1);
writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
(mode->left_margin + mode->right_margin +
mode->hsync_len + mode->xres),
writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
(timings->hback_porch.typ + timings->hfront_porch.typ +
timings->hsync_len.typ + timings->hactive.typ),
&regs->hw_lcdif_vdctrl2);
writel(((mode->left_margin + mode->hsync_len) <<
writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
(mode->upper_margin + mode->vsync_len),
(timings->vback_porch.typ + timings->vsync_len.typ),
&regs->hw_lcdif_vdctrl3);
writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
&regs->hw_lcdif_vdctrl4);
writel(fb_addr, &regs->hw_lcdif_cur_buf);
@ -135,10 +167,11 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
}
static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
int bpp, u32 fb)
{
/* Start framebuffer */
mxs_lcd_init(fb, mode, bpp);
mxs_lcd_init(dev, fb, timings, bpp);
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
/*
@ -204,6 +237,7 @@ void *video_hw_init(void)
char *penv;
void *fb = NULL;
struct ctfb_res_modes mode;
struct display_timing timings;
puts("Video: ");
@ -260,7 +294,9 @@ void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
ret = mxs_probe_common(&mode, bpp, (u32)fb);
video_ctfb_mode_to_display_timing(&mode, &timings);
ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
if (ret)
goto dealloc_fb;
@ -314,7 +350,6 @@ static int mxs_video_probe(struct udevice *dev)
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct ctfb_res_modes mode;
struct display_timing timings;
u32 bpp = 0;
u32 fb_start, fb_end;
@ -327,17 +362,7 @@ static int mxs_video_probe(struct udevice *dev)
if (ret)
return ret;
mode.xres = timings.hactive.typ;
mode.yres = timings.vactive.typ;
mode.left_margin = timings.hback_porch.typ;
mode.right_margin = timings.hfront_porch.typ;
mode.upper_margin = timings.vback_porch.typ;
mode.lower_margin = timings.vfront_porch.typ;
mode.hsync_len = timings.hsync_len.typ;
mode.vsync_len = timings.vsync_len.typ;
mode.pixclock = HZ2PS(timings.pixelclock.typ);
ret = mxs_probe_common(&mode, bpp, plat->base);
ret = mxs_probe_common(dev, &timings, bpp, plat->base);
if (ret)
return ret;
@ -358,8 +383,8 @@ static int mxs_video_probe(struct udevice *dev)
return -EINVAL;
}
uc_priv->xsize = mode.xres;
uc_priv->ysize = mode.yres;
uc_priv->xsize = timings.hactive.typ;
uc_priv->ysize = timings.vactive.typ;
/* Enable dcache for the frame buffer */
fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
@ -420,6 +445,7 @@ static const struct udevice_id mxs_video_ids[] = {
{ .compatible = "fsl,imx23-lcdif" },
{ .compatible = "fsl,imx28-lcdif" },
{ .compatible = "fsl,imx7ulp-lcdif" },
{ .compatible = "fsl,imxrt-lcdif" },
{ /* sentinel */ }
};

33
drivers/video/sunxi/sunxi_display.c
View File

@ -615,35 +615,6 @@ static void sunxi_lcdc_backlight_enable(void)
gpio_direction_output(pin, PWM_ON);
}
static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
struct display_timing *timing)
{
timing->pixelclock.typ = mode->pixclock_khz * 1000;
timing->hactive.typ = mode->xres;
timing->hfront_porch.typ = mode->right_margin;
timing->hback_porch.typ = mode->left_margin;
timing->hsync_len.typ = mode->hsync_len;
timing->vactive.typ = mode->yres;
timing->vfront_porch.typ = mode->lower_margin;
timing->vback_porch.typ = mode->upper_margin;
timing->vsync_len.typ = mode->vsync_len;
timing->flags = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
if (mode->vmode == FB_VMODE_INTERLACED)
timing->flags |= DISPLAY_FLAGS_INTERLACED;
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
@ -673,7 +644,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
sunxi_is_composite());
sunxi_ctfb_mode_to_display_timing(mode, &timing);
video_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}
@ -689,7 +660,7 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct display_timing timing;
sunxi_ctfb_mode_to_display_timing(mode, &timing);
video_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
sunxi_is_composite());

29
drivers/video/videomodes.c
View File

@ -444,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
return 0;
}
void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
struct display_timing *timing)
{
timing->pixelclock.typ = mode->pixclock_khz * 1000;
timing->hactive.typ = mode->xres;
timing->hfront_porch.typ = mode->right_margin;
timing->hback_porch.typ = mode->left_margin;
timing->hsync_len.typ = mode->hsync_len;
timing->vactive.typ = mode->yres;
timing->vfront_porch.typ = mode->lower_margin;
timing->vback_porch.typ = mode->upper_margin;
timing->vsync_len.typ = mode->vsync_len;
timing->flags = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else
timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
if (mode->vmode == FB_VMODE_INTERLACED)
timing->flags |= DISPLAY_FLAGS_INTERLACED;
}

11
drivers/video/videomodes.h
View File

@ -92,3 +92,14 @@ int video_get_option_int(const char *options, const char *name, int def);
int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
struct ctfb_res_modes *mode);
/**
* video_ctfb_mode_to_display_timing() - Convert a ctfb(Cathode Tube Frame
* Buffer)_res_modes struct to a
* display_timing struct.
*
* @mode: Input ctfb_res_modes structure pointer to be converted
* from
* @timing: Output display_timing structure pointer to be converted to
*/
void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
struct display_timing *timing);

2
include/configs/apalis_imx6.h
View File

@ -146,8 +146,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12200000\0" \

2
include/configs/colibri-imx6ull.h
View File

@ -40,8 +40,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82200000\0" \

2
include/configs/colibri_imx6.h
View File

@ -134,8 +134,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12200000\0" \

2
include/configs/colibri_imx7.h
View File

@ -108,8 +108,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"ramdisk_addr_r=0x82100000\0" \
"scriptaddr=0x82500000\0"

2
include/configs/colibri_vf.h
View File

@ -51,8 +51,6 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82100000\0" \

46
include/configs/imxrt1020-evk.h Normal file
View File

@ -0,0 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __IMXRT1020_EVK_H
#define __IMXRT1020_EVK_H
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_INIT_SP_ADDR 0x20240000
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SYS_LOAD_ADDR 0x20209000
#else
#define CONFIG_SYS_LOAD_ADDR 0x80000000
#define CONFIG_LOADADDR 0x80000000
#endif
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_LEN 0x00008000
#define CONFIG_SYS_UBOOT_START 0x800023FD
#endif
/* For SPL ends */
#endif /* __IMXRT1020_EVK_H */

15
include/configs/imxrt1050-evk.h
View File

@ -30,6 +30,21 @@
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#endif
/*
* Configuration of the external SDRAM memory
*/

1
include/configs/mx6ul_14x14_evk.h
View File

@ -172,7 +172,6 @@
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)

9
include/configs/mx6ullevk.h
View File

@ -166,4 +166,13 @@
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define CONFIG_ETHPRIME "eth0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define CONFIG_ETHPRIME "eth1"
#endif
#endif
#endif

9
include/configs/tqma6.h
View File

@ -28,18 +28,11 @@
#define PHYS_SDRAM_SIZE (SZ_1G)
#endif
#define CONFIG_MXC_UART
/* SPI Flash */
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
@ -49,11 +42,13 @@
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
#if !defined(CONFIG_DM_PMIC)
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define TQMA6_PFUZE100_I2C_BUS 2
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

3
include/configs/tqma6_wru4.h
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@ -30,4 +30,7 @@
/* Bootcounter */
#define CONFIG_SYS_BOOTCOUNT_BE
/* I2C */
#define CONFIG_SYS_I2C
#endif /* __CONFIG_TQMA6_WRU4_H */

6
include/configs/verdin-imx8mm.h
View File

@ -66,6 +66,12 @@
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_image=Image\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \
"tftp ${fdt_addr} verdin/${fdtfile}; " \
"booti ${loadaddr} - ${fdt_addr}\0" \
"setup=setenv setupargs console=${console},${baudrate} " \
"console=tty1 consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \

52
include/dt-bindings/clock/imxrt1020-clock.h Normal file
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@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright(C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
#define __DT_BINDINGS_CLOCK_IMXRT1020_H
#define IMXRT1020_CLK_DUMMY 0
#define IMXRT1020_CLK_CKIL 1
#define IMXRT1020_CLK_CKIH 2
#define IMXRT1020_CLK_OSC 3
#define IMXRT1020_CLK_PLL2_PFD0_352M 4
#define IMXRT1020_CLK_PLL2_PFD1_594M 5
#define IMXRT1020_CLK_PLL2_PFD2_396M 6
#define IMXRT1020_CLK_PLL2_PFD3_297M 7
#define IMXRT1020_CLK_PLL3_PFD0_720M 8
#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
#define IMXRT1020_CLK_PLL2_198M 12
#define IMXRT1020_CLK_PLL3_120M 13
#define IMXRT1020_CLK_PLL3_80M 14
#define IMXRT1020_CLK_PLL3_60M 15
#define IMXRT1020_CLK_PLL2_BYPASS 16
#define IMXRT1020_CLK_PLL3_BYPASS 17
#define IMXRT1020_CLK_PLL6_BYPASS 18
#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
#define IMXRT1020_CLK_PERIPH_SEL 20
#define IMXRT1020_CLK_SEMC_ALT_SEL 21
#define IMXRT1020_CLK_SEMC_SEL 22
#define IMXRT1020_CLK_USDHC1_SEL 23
#define IMXRT1020_CLK_USDHC2_SEL 24
#define IMXRT1020_CLK_LPUART_SEL 25
#define IMXRT1020_CLK_ARM_PODF 26
#define IMXRT1020_CLK_LPUART_PODF 27
#define IMXRT1020_CLK_USDHC1_PODF 28
#define IMXRT1020_CLK_USDHC2_PODF 29
#define IMXRT1020_CLK_SEMC_PODF 30
#define IMXRT1020_CLK_AHB_PODF 31
#define IMXRT1020_CLK_USDHC1 32
#define IMXRT1020_CLK_USDHC2 33
#define IMXRT1020_CLK_LPUART1 34
#define IMXRT1020_CLK_SEMC 35
#define IMXRT1020_CLK_PLL2_SYS 36
#define IMXRT1020_CLK_PLL3_USB_OTG 37
#define IMXRT1020_CLK_PLL4_AUDIO 38
#define IMXRT1020_CLK_PLL6_ENET 39
#define IMXRT1020_CLK_END 40
#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */

763
include/dt-bindings/pinctrl/pins-imxrt1020.h Normal file
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@ -0,0 +1,763 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
#define IMX_PAD_SION 0x40000000
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x188 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x014 0x188 0x420 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x014 0x188 0x3E0 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014 0x188 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x188 0x3B0 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x014 0x188 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x014 0x188 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x014 0x188 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x18C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x018 0x18C 0x424 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x018 0x18C 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x018 0x18C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x18C 0x3AC 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x018 0x18C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x018 0x18C 0x320 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x018 0x18C 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x190 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x01C 0x190 0x428 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX 0x01C 0x190 0x3E8 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x01C 0x190 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x190 0x3B8 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x01C 0x190 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x01C 0x190 0x37C 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x194 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x020 0x194 0x42C 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX 0x020 0x194 0x3E4 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x020 0x194 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x194 0x3B4 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x020 0x194 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x020 0x194 0x380 0x6 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x198 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x024 0x198 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x024 0x198 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024 0x198 0x464 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x024 0x198 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x024 0x198 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x19C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x028 0x19C 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN 0x028 0x19C 0x488 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x19C 0x468 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x028 0x19C 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x028 0x19C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x1A0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x02C 0x1A0 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX 0x02C 0x1A0 0x3DC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C 0x1A0 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x02C 0x1A0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x02C 0x1A0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x1A4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x030 0x1A4 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX 0x030 0x1A4 0x3D8 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030 0x1A4 0x460 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x030 0x1A4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x030 0x1A4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x1A8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x034 0x1A8 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x034 0x1A8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x1A8 0x45C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x034 0x1A8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x034 0x1A8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x1AC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x038 0x1AC 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x038 0x1AC 0x324 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038 0x1AC 0x458 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x038 0x1AC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x038 0x1AC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS 0x03C 0x1B0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x03C 0x1B0 0x4B0 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x03C 0x1B0 0x398 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C 0x1B0 0x450 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x03C 0x1B0 0x3B0 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x03C 0x1B0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x03C 0x1B0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS 0x040 0x1B4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x040 0x1B4 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x040 0x1B4 0x394 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040 0x1B4 0x44C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x040 0x1B4 0x3AC 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x040 0x1B4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x040 0x1B4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0 0x044 0x1B8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x044 0x1B8 0x4B4 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX 0x044 0x1B8 0x3F8 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x044 0x1B8 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x044 0x1B8 0x3B8 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x044 0x1B8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x044 0x1B8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0 0x048 0x1BC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x048 0x1BC 0x4B8 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX 0x048 0x1BC 0x3F4 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x048 0x1BC 0x438 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x048 0x1BC 0x3B4 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x048 0x1BC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x048 0x1BC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048 0x1BC 0x300 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1 0x04C 0x1C0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x04C 0x1C0 0x4A0 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x04C 0x1C0 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C 0x1C0 0x434 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x1C0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x04C 0x1C0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x04C 0x1C0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x050 0x1C4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x050 0x1C4 0x4A4 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x050 0x1C4 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050 0x1C4 0x448 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B 0x050 0x1C4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x050 0x1C4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x050 0x1C4 0x320 0x6 0x3
#define MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x054 0x1C8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x054 0x1C8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x054 0x1C8 0x454 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x054 0x1C8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x054 0x1C8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x058 0x1CC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT 0x058 0x1CC 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x058 0x1CC 0x46C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x058 0x1CC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x058 0x1CC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x05C 0x1D0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x05C 0x1D0 0x4A8 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x05C 0x1D0 0x388 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C 0x1D0 0x448 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x05C 0x1D0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x05C 0x1D0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C 0x1D0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x060 0x1D4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x060 0x1D4 0x4AC 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x060 0x1D4 0x384 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060 0x1D4 0x434 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x060 0x1D4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x060 0x1D4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060 0x1D4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x064 0x1D8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x064 0x1D8 0x334 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x064 0x1D8 0x3CC 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x064 0x1D8 0x430 0x3 0x3
#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x064 0x1D8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x064 0x1D8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064 0x1D8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x068 0x1DC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x068 0x1DC 0x344 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x068 0x1DC 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x068 0x1DC 0x438 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x068 0x1DC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x068 0x1DC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068 0x1DC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x06C 0x1E0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x06C 0x1E0 0x330 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX 0x06C 0x1E0 0x3D4 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x06C 0x1E0 0x43C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x06C 0x1E0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x06C 0x1E0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C 0x1E0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x070 0x1E4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x070 0x1E4 0x340 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX 0x070 0x1E4 0x3D0 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x070 0x1E4 0x440 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x070 0x1E4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x070 0x1E4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070 0x1E4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x074 0x1E8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x074 0x1E8 0x32C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x074 0x1E8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x074 0x1E8 0x444 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x074 0x1E8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x074 0x1E8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074 0x1E8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x078 0x1EC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x078 0x1EC 0x33C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x078 0x1EC 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x078 0x1EC 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x078 0x1EC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x078 0x1EC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078 0x1EC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x07C 0x1F0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x07C 0x1F0 0x328 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX 0x07C 0x1F0 0x408 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C 0x1F0 0x44C 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x07C 0x1F0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x07C 0x1F0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C 0x1F0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x080 0x1F4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x080 0x1F4 0x338 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX 0x080 0x1F4 0x404 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080 0x1F4 0x450 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x080 0x1F4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x080 0x1F4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080 0x1F4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS 0x084 0x1F8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x084 0x1F8 0x354 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x084 0x1F8 0x4BC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x084 0x1F8 0x46C 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x084 0x1F8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x084 0x1F8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x084 0x1F8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x084 0x1F8 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE 0x088 0x1FC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x088 0x1FC 0x364 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x088 0x1FC 0x4C0 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088 0x1FC 0x470 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x088 0x1FC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x088 0x1FC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x088 0x1FC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x088 0x1FC 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK 0x08C 0x200 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x08C 0x200 0x350 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x08C 0x200 0x3E0 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C 0x200 0x478 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x08C 0x200 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x08C 0x200 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x08C 0x200 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x08C 0x200 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01 0x090 0x204 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x090 0x204 0x360 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x090 0x204 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090 0x204 0x474 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B 0x090 0x204 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x090 0x204 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK 0x090 0x204 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x090 0x204 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x094 0x208 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x094 0x208 0x410 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX 0x094 0x208 0x3E8 0x2 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094 0x208 0x000 0x3 0x4
#define MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x094 0x208 0x3C0 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x094 0x208 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x094 0x208 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x098 0x20C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x098 0x20C 0x414 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX 0x098 0x20C 0x3E4 0x2 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098 0x20C 0x47C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x098 0x20C 0x3BC 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x098 0x20C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x09C 0x210 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x09C 0x210 0x418 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX 0x09C 0x210 0x400 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C 0x210 0x480 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x09C 0x210 0x3C8 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x09C 0x210 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS 0x09C 0x210 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x0A0 0x214 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x0A0 0x214 0x41C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX 0x0A0 0x214 0x3FC 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP 0x0A0 0x214 0x49C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x0A0 0x214 0x3C4 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x0A0 0x214 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL 0x0A0 0x214 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x0A4 0x218 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x0A4 0x218 0x34C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x0A4 0x218 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4 0x218 0x300 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x0A4 0x218 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x0A4 0x218 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x0A4 0x218 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x218 0x494 0x7 0x4
#define MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x0A8 0x21C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x0A8 0x21C 0x35C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x0A8 0x21C 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x0A8 0x21C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x0A8 0x21C 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x0A8 0x21C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8 0x21C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x0A8 0x21C 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x0AC 0x220 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x0AC 0x220 0x348 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX 0x0AC 0x220 0x3F0 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT 0x0AC 0x220 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x0AC 0x220 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x0AC 0x220 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC 0x220 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x0AC 0x220 0x490 0x7 0x3
#define MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x0B0 0x224 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x0B0 0x224 0x358 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX 0x0B0 0x224 0x3EC 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x0B0 0x224 0x48C 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x224 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x0B0 0x224 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x0B0 0x224 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK 0x0B0 0x224 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x0B4 0x228 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x0B4 0x228 0x4BC 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x0B4 0x228 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x0B4 0x228 0x2FC 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO 0x0B4 0x228 0x308 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x0B4 0x228 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4 0x228 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x0B4 0x228 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY 0x0B8 0x22C 0x484 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x0B8 0x22C 0x4C0 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN 0x0B8 0x22C 0x488 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8 0x22C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC 0x0B8 0x22C 0x000 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x0B8 0x22C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8 0x22C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x0B8 0x22C 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x0BC 0x230 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x230 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x0BC 0x230 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x0C0 0x234 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x234 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x0C0 0x234 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x0C4 0x238 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x238 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x0C4 0x238 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x0C8 0x23C 0x000 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x0C8 0x23C 0x498 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x0C8 0x23C 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x0C8 0x23C 0x430 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x0C8 0x23C 0x494 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x23C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x23C 0x48C 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x0C8 0x23C 0x300 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x0CC 0x240 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x0CC 0x240 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x0CC 0x240 0x494 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x0CC 0x240 0x420 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x0CC 0x240 0x308 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x240 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x0CC 0x240 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x0CC 0x240 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0 0x244 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x0D0 0x244 0x320 0x1 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x0D0 0x244 0x490 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x0D0 0x244 0x424 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x0D0 0x244 0x000 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x244 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x0D0 0x244 0x2FC 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x0D0 0x244 0x40C 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x0D4 0x248 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x0D4 0x248 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4 0x248 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x0D4 0x248 0x428 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x0D4 0x248 0x354 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x248 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x0D4 0x248 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x0D8 0x24C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x0D8 0x24C 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8 0x24C 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x0D8 0x24C 0x42C 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x0D8 0x24C 0x364 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x24C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x0D8 0x24C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x0DC 0x250 0x31C 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC 0x250 0x38C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x0DC 0x250 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x0DC 0x250 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x0DC 0x250 0x304 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x250 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x0DC 0x250 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x0E0 0x254 0x310 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0 0x254 0x390 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x0E0 0x254 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x0E0 0x254 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x254 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x0E0 0x254 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x0E4 0x258 0x30C 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4 0x258 0x3A0 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4 0x258 0x3F0 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x0E4 0x258 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x0E4 0x258 0x350 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x258 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x0E4 0x258 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8 0x25C 0x314 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x0E8 0x25C 0x39C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8 0x25C 0x3EC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x0E8 0x25C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x0E8 0x25C 0x360 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x25C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x0E8 0x25C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC 0x260 0x318 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC 0x260 0x3A8 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x0EC 0x260 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x0EC 0x260 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x0EC 0x260 0x34C 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x260 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x0EC 0x260 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x0EC 0x260 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0 0x264 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0 0x264 0x3A4 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x0F0 0x264 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x0F0 0x264 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x0F0 0x264 0x35C 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x264 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x0F0 0x264 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x0F0 0x264 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x0F4 0x268 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x268 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4 0x268 0x3DC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x0F4 0x268 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x0F4 0x268 0x348 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x268 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x0F4 0x268 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x0F4 0x268 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x0F8 0x26C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x26C 0x324 0x1 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8 0x26C 0x3D8 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x0F8 0x26C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x0F8 0x26C 0x358 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x26C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x0F8 0x26C 0x000 0x6 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC 0x270 0x484 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x0FC 0x270 0x374 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX 0x0FC 0x270 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK 0x0FC 0x270 0x430 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 0x0FC 0x270 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x270 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT 0x0FC 0x270 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04 0x0FC 0x270 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100 0x274 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x100 0x274 0x378 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX 0x100 0x274 0x324 0x2 0x3
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK 0x100 0x274 0x44C 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 0x100 0x274 0x000 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x274 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN 0x100 0x274 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04 0x100 0x274 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104 0x278 0x000 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x104 0x278 0x368 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104 0x278 0x3C0 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC 0x104 0x278 0x450 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 0x104 0x278 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x278 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT 0x104 0x278 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05 0x104 0x278 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108 0x27C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x108 0x27C 0x370 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 0x108 0x27C 0x3BC 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00 0x108 0x27C 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 0x108 0x27C 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x27C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN 0x108 0x27C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05 0x108 0x27C 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C 0x280 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x10C 0x280 0x36C 0x1 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C 0x280 0x3C8 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC 0x10C 0x280 0x448 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 0x10C 0x280 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x280 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 0x10C 0x280 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06 0x10C 0x280 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP 0x110 0x284 0x494 0x0 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x110 0x284 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110 0x284 0x3C4 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00 0x110 0x284 0x438 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 0x110 0x284 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x284 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 0x110 0x284 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06 0x110 0x284 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x114 0x288 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x114 0x288 0x328 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x114 0x288 0x3CC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x114 0x288 0x434 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x114 0x288 0x000 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x288 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x114 0x288 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x114 0x288 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x118 0x28C 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x118 0x28C 0x338 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x118 0x28C 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x118 0x28C 0x444 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x118 0x28C 0x000 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x28C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x118 0x28C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x118 0x28C 0x000 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C 0x290 0x384 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x11C 0x290 0x32C 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C 0x290 0x3D4 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x11C 0x290 0x440 0x3 0x3
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x11C 0x290 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x290 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x11C 0x290 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x11C 0x290 0x4B4 0x7 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120 0x294 0x388 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x120 0x294 0x33C 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120 0x294 0x3D0 0x2 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x120 0x294 0x43C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26 0x120 0x294 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x294 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x120 0x294 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x120 0x294 0x4B8 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x124 0x298 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x124 0x298 0x330 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124 0x298 0x3E8 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x124 0x298 0x490 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x124 0x298 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x298 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x124 0x298 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x128 0x29C 0x2FC 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x128 0x29C 0x340 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128 0x29C 0x3E4 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x128 0x29C 0x494 0x3 0x3
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x128 0x29C 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x29C 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x128 0x29C 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x12C 0x2A0 0x48C 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x2A0 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C 0x2A0 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x12C 0x2A0 0x498 0x3 0x2
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x12C 0x2A0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x2A0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x12C 0x2A0 0x334 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x130 0x2A4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x2A4 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x130 0x2A4 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x130 0x2A4 0x49C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x130 0x2A4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x2A4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x130 0x2A4 0x344 0x6 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134 0x2A8 0x37C 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x2A8 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x2A8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x134 0x2A8 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x134 0x2A8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x2A8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138 0x2AC 0x380 0x0 0x1
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x2AC 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138 0x2AC 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x138 0x2AC 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x138 0x2AC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x2AC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x13C 0x2B0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x13C 0x2B0 0x410 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x13C 0x2B0 0x430 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x13C 0x2B0 0x454 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C 0x2B0 0x38C 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C 0x2B0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x13C 0x2B0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x13C 0x2B0 0x4A0 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x140 0x2B4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x140 0x2B4 0x414 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x140 0x2B4 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x140 0x2B4 0x460 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140 0x2B4 0x390 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140 0x2B4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x140 0x2B4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x140 0x2B4 0x4A4 0x7 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144 0x2B8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x144 0x2B8 0x418 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x144 0x2B8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x144 0x2B8 0x458 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144 0x2B8 0x3A0 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144 0x2B8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x144 0x2B8 0x308 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x144 0x2B8 0x4A8 0x7 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148 0x2BC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x148 0x2BC 0x41C 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x148 0x2BC 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x148 0x2BC 0x45C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x148 0x2BC 0x39C 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148 0x2BC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x148 0x2BC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x14C 0x2C0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x14C 0x2C0 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C 0x2C0 0x400 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x14C 0x2C0 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C 0x2C0 0x3A8 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C 0x2C0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x14C 0x2C0 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x150 0x2C4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x150 0x2C4 0x324 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150 0x2C4 0x3FC 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x150 0x2C4 0x464 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150 0x2C4 0x3A4 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150 0x2C4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x150 0x2C4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x154 0x2C8 0x490 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x154 0x2C8 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x154 0x2C8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x154 0x2C8 0x468 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x154 0x2C8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154 0x2C8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x154 0x2C8 0x4AC 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x158 0x2CC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x158 0x2CC 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158 0x2CC 0x3F8 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x158 0x2CC 0x4B0 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x158 0x2CC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158 0x2CC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x15C 0x2D0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x15C 0x2D0 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C 0x2D0 0x3F4 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x15C 0x2D0 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x15C 0x2D0 0x320 0x4 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C 0x2D0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160 0x2D4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x160 0x2D4 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160 0x2D4 0x408 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160 0x2D4 0x394 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x160 0x2D4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160 0x2D4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x160 0x2D4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164 0x2D8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x164 0x2D8 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164 0x2D8 0x404 0x2 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164 0x2D8 0x398 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x164 0x2D8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164 0x2D8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x164 0x2D8 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x168 0x2DC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x168 0x2DC 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x168 0x2DC 0x31C 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x168 0x2DC 0x304 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x168 0x2DC 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168 0x2DC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x168 0x2DC 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x16C 0x2E0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x16C 0x2E0 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x16C 0x2E0 0x310 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x16C 0x2E0 0x46C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x16C 0x2E0 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C 0x2E0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x16C 0x2E0 0x300 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x170 0x2E4 0x498 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x170 0x2E4 0x374 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x170 0x2E4 0x30C 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x170 0x2E4 0x47C 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x170 0x2E4 0x3AC 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170 0x2E4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x170 0x2E4 0x000 0x6 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x174 0x2E8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x174 0x2E8 0x378 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174 0x2E8 0x314 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x174 0x2E8 0x480 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174 0x2E8 0x3B0 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174 0x2E8 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x178 0x2EC 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x178 0x2EC 0x368 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178 0x2EC 0x318 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x178 0x2EC 0x000 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178 0x2EC 0x3B8 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178 0x2EC 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x17C 0x2F0 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x17C 0x2F0 0x370 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C 0x2F0 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x17C 0x2F0 0x470 0x3 0x1
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C 0x2F0 0x3B4 0x4 0x2
#define MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C 0x2F0 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x180 0x2F4 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x180 0x2F4 0x36C 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x180 0x2F4 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x180 0x2F4 0x478 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x180 0x2F4 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180 0x2F4 0x000 0x5 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x184 0x2F8 0x000 0x0 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x184 0x2F8 0x000 0x1 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x184 0x2F8 0x000 0x2 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x184 0x2F8 0x474 0x3 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x184 0x2F8 0x000 0x4 0x0
#define MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184 0x2F8 0x000 0x5 0x0
#endif /* _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */