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ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
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@ -250,16 +250,31 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
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static void mmdc_set_sdqs(bool set)
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{
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struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
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(struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
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struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
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(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
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struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
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(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
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struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
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(struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
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struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
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(struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
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int i, sdqs_cnt;
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u32 sdqs;
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if (is_mx6sx()) {
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sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
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sdqs_cnt = 2;
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} else if (is_mx6sl()) {
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sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
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sdqs_cnt = 2;
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} else if (is_mx6ul() || is_mx6ull()) {
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sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
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sdqs_cnt = 2;
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} else if (is_mx6sdl()) {
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sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
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sdqs_cnt = 8;
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} else { /* MX6DQ */
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sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
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sdqs_cnt = 8;
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