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pci: layerscape: enable PCIe config ready

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In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Hou Zhiqiang 2017-02-10 15:42:11 +08:00 committed by York Sun
parent ac55dadb1c
commit d170aca1a0
2 changed files with 9 additions and 0 deletions
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7
drivers/pci/pcie_layerscape.c
View File

@ -409,6 +409,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
}
static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
{
ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
}
static void ls_pcie_setup_ep(struct ls_pcie *pcie)
{
u32 sriov;
@ -432,6 +437,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
ls_pcie_ep_setup_atu(pcie);
}
ls_pcie_ep_enable_cfg(pcie);
}
static int ls_pcie_probe(struct udevice *dev)

2
drivers/pci/pcie_layerscape.h
View File

@ -94,8 +94,10 @@
#define PCIE_LUT_ENTRY_COUNT 32
/* PF Controll registers */
#define PCIE_PF_CONFIG 0x14
#define PCIE_PF_VF_CTRL 0x7F8
#define PCIE_PF_DBG 0x7FC
#define PCIE_CONFIG_READY (1 << 0)
#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
#define PCIE_SYS_BASE_ADDR 0x3400000