mirror of
https://github.com/brain-hackers/u-boot-brain
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sparc: leon3: Added memory controller initialization using new AMBA PnP routines.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
This commit is contained in:
Daniel Hellstrom
Francois Retief
parent
3f33f6a28b
commit
cff009ed6f
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@ -7,4 +7,4 @@
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extra-y = start.o
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obj-y = cpu_init.o serial.o cpu.o ambapp.o ambapp_low.o ambapp_low_c.o \
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interrupts.o prom.o usb_uhci.o
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interrupts.o prom.o usb_uhci.o memcfg.o memcfg_low.o
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237
arch/sparc/cpu/leon3/memcfg.c
Normal file
237
arch/sparc/cpu/leon3/memcfg.c
Normal file
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@ -0,0 +1,237 @@
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/* GRLIB Memory controller setup. The register values are used
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* from the associated low level assembler routine implemented
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* in memcfg_low.S.
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*
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* (C) Copyright 2010, 2015
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <ambapp.h>
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#include "memcfg.h"
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#include <config.h>
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#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
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struct mctrl_setup esa_mctrl1_cfg = {
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.reg_mask = 0x7,
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.regs = {
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{
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.mask = 0x00000300,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3,
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},
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}
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};
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#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
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struct mctrl_setup esa_mctrl2_cfg = {
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.reg_mask = 0x7,
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.regs = {
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{
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.mask = 0x00000300,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3,
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},
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}
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};
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#endif
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#endif
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#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
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struct mctrl_setup gaisler_ftmctrl1_cfg = {
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.reg_mask = 0x7,
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.regs = {
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{
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.mask = 0x00000300,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3,
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},
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}
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};
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#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
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struct mctrl_setup gaisler_ftmctrl2_cfg = {
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.reg_mask = 0x7,
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.regs = {
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{
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.mask = 0x00000300,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3,
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},
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}
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};
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#endif
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#endif
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#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
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struct mctrl_setup gaisler_sdctrl1_cfg = {
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.reg_mask = 0x1,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL,
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},
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}
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};
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#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
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struct mctrl_setup gaisler_sdctrl2_cfg = {
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.reg_mask = 0x1,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL,
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},
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}
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};
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#endif
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#endif
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
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struct ahbmctrl_setup gaisler_ddr2spa1_cfg = {
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.ahb_mbar_no = 1,
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.reg_mask = 0xd,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1,
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},
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{ 0x00000000, 0},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4,
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},
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}
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};
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
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struct ahbmctrl_setup gaisler_ddr2spa2_cfg = {
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.ahb_mbar_no = 1,
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.reg_mask = 0xd,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1,
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},
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{ 0x00000000, 0},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3,
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},
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4,
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},
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}
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};
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#endif
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#endif
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
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struct ahbmctrl_setup gaisler_ddrspa1_cfg = {
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.ahb_mbar_no = 1,
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.reg_mask = 0x1,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL,
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},
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}
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};
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
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struct ahbmctrl_setup gaisler_ddrspa2_cfg = {
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.ahb_mbar_no = 1,
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.reg_mask = 0x1,
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.regs = {
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{
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.mask = 0x00000000,
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.value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL,
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},
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}
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};
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#endif
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#endif
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struct grlib_mctrl_handler grlib_mctrl_handlers[] = {
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/* ESA MCTRL (PROM/FLASH/IO/SRAM/SDRAM) */
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#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
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{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
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_nomem_mctrl_init, (void *)&esa_mctrl1_cfg},
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#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
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{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
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_nomem_mctrl_init, (void *)&esa_mctrl2_cfg},
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#endif
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#endif
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/* GAISLER Fault Tolerant Memory controller (PROM/FLASH/IO/SRAM/SDRAM) */
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#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
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{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
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_nomem_mctrl_init, (void *)&gaisler_ftmctrl1_cfg},
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#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
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{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
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_nomem_mctrl_init, (void *)&gaisler_ftmctrl2_cfg},
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#endif
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#endif
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/* GAISLER SDRAM-only Memory controller (SDRAM) */
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#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
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{DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
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_nomem_mctrl_init, (void *)&gaisler_sdctrl1_cfg},
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#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
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{DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
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_nomem_mctrl_init, (void *)&gaisler_sdctrl2_cfg},
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#endif
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#endif
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/* GAISLER DDR Memory controller (DDR) */
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
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{DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
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_nomem_ahbmctrl_init, (void *)&gaisler_ddrspa1_cfg},
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
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{DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
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_nomem_ahbmctrl_init, (void *)&gaisler_ddrspa2_cfg},
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#endif
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#endif
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/* GAISLER DDR2 Memory controller (DDR2) */
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
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{DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
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_nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa1_cfg},
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#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
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{DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
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_nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa2_cfg},
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#endif
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#endif
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/* Mark end */
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MH_END
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};
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90
arch/sparc/cpu/leon3/memcfg.h
Normal file
90
arch/sparc/cpu/leon3/memcfg.h
Normal file
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@ -0,0 +1,90 @@
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/* GRLIB Memory controller setup structures
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*
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* (C) Copyright 2010, 2015
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MEMCFG_H__
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#define __MEMCFG_H__
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/*********** Low Level Memory Controller Initalization ***********/
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#ifndef __ASSEMBLER__
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struct grlib_mctrl_handler;
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typedef void (*mctrl_handler_t)(
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struct grlib_mctrl_handler *dev,
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void *conf,
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unsigned int ioarea
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);
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/* Memory Controller Handler Structure */
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struct grlib_mctrl_handler {
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unsigned char type; /* 0x00. MASK: AHB MST&SLV, APB SLV */
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char index; /* 0x01. Unit number, 0, 1, 2... */
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char unused[2]; /* 0x02 */
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unsigned int ven_dev; /* 0x04. Device and Vendor */
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mctrl_handler_t func; /* 0x08. Memory Controller Handler */
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void *priv; /* 0x0c. Optional private data, ptr to
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* info how to set up controller */
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};
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extern struct grlib_mctrl_handler grlib_mctrl_handlers[];
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#endif
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#define MH_STRUCT_SIZE (4*4)
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#define MH_TYPE 0x00
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#define MH_INDEX 0x01
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#define MH_VENDOR_DEVICE 0x04
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#define MH_FUNC 0x08
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#define MH_PRIV 0x0c
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#define MH_TYPE_NONE DEV_NONE
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#define MH_TYPE_AHB_MST DEV_AHB_MST
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#define MH_TYPE_AHB_SLV DEV_AHB_SLV
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#define MH_TYPE_APB_SLV DEV_APB_SLV
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#define MH_UNUSED {0, 0}
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#define MH_END {DEV_NONE, 0, MH_UNUSED, AMBA_PNP_ID(0, 0), 0, 0}
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/*********** Low Level Memory Controller Initalization Handlers ***********/
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#ifndef __ASSEMBLER__
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extern void _nomem_mctrl_init(
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struct grlib_mctrl_handler *dev,
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void *conf,
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unsigned int ioarea_apbmst);
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struct mctrl_setup {
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unsigned int reg_mask; /* Which registers to write */
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struct {
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unsigned int mask; /* Mask used keep reg bits unchanged */
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unsigned int value; /* Value written to register */
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} regs[8];
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};
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extern void _nomem_ahbmctrl_init(
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struct grlib_mctrl_handler *dev,
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void *conf,
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unsigned int ioarea_apbmst);
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struct ahbmctrl_setup {
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int ahb_mbar_no; /* MBAR to get register address from */
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unsigned int reg_mask; /* Which registers to write */
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struct {
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unsigned int mask; /* Mask used keep reg bits unchanged */
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unsigned int value; /* Value written to register */
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} regs[8];
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};
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#endif
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/* mctrl_setup data structure defines */
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#define NREGS_OFS 0
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#define REGS_OFS 0x4
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#define REGS_SIZE 8
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#endif
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253
arch/sparc/cpu/leon3/memcfg_low.S
Normal file
253
arch/sparc/cpu/leon3/memcfg_low.S
Normal file
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@ -0,0 +1,253 @@
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/* This is the memory initialization functions, the function
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* implemented below initializes each memory controller
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* found and specified by the input grlib_mctrl_handler structure.
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*
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* After the memory controllers have been initialized the stack
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* can be used.
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*
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* (C) Copyright 2010, 2015
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <ambapp.h>
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#include "memcfg.h"
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#include <config.h>
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.seg "text"
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.globl _nomem_memory_ctrl_init
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.globl _nomem_mctrl_init, _nomem_ahbmctrl_init
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.extern _nomem_find_apb
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.extern _nomem_find_ahb
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/* FUNCTION
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* _nomem_memory_controller_init(struct grlib_mctrl_handler *mem_handlers)
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*
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* Initialize AMBA devices, _nomem_amba_init() has prepared i0-i5
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* with the AHB buses on the system.
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*
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* For each entry in mem_handlers find the VENDOR:DEVICE and handle it
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* by calling the handler function pointer.
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*
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* Constraints:
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* i6, i7, o6, l7, l6, g3, g4, g5, g6, g7 is used by caller
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* o7 is return address
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* l5 reserved for this function for future use.
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*
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* Arguments
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* - o0 Pointer to memory handler array
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*
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* Results
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* - o0 Number of memory controllers found
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*
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* Clobbered
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* - o0 (Current AHB slave conf address)
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* - l0 (mem handler entry address)
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* - l1 (Return value, number of memory controllers found)
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* - o7 (function pointer)
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* - l0, l1, l2, l3, l4, g1, g2 (used by _nomem_ambapp_find_buses)
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* - o0, o1, o2, o3, o4, o5 (Used as arguments)
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*
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* - g1 ( level 1 return address)
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* - g2 ( level 2 return address)
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*/
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_nomem_memory_ctrl_init:
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/* At this point all AHB buses has been found and the I/O Areas of
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* all AHB buses is stored in the i0-i5 registers. Max 6 buses. Next,
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* memory controllers are found by searching all buses for matching
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* VENDOR:DEVICE. The VENDOR:DEVICE to search for are taken from the
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* mem_handlers array. For each match the function pointer stored in
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* the mem_handler entry is called to handle the hardware setup.
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*/
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mov %o7, %g1 /* Save return address */
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mov %o0, %l0
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mov %g0, %l1 /* The return value */
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.L_do_one_mem_handler:
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ld [%l0 + MH_FUNC], %o7
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cmp %o7, %g0
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be .L_all_mctrl_handled
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nop
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/*** Scan for memory controller ***/
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/* Set up argments, o5 not used by _nomem_find_apb */
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ldub [%l0 + MH_TYPE], %o5
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clr %o4
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clr %o3
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ldub [%l0 + MH_INDEX], %o2
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ld [%l0 + MH_VENDOR_DEVICE], %o1
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/* An empty config? */
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cmp %o5, DEV_NONE
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beq .L_all_mctrl_next
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/* Select function (APB or AHB) */
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cmp %o5, DEV_APB_SLV
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bne .L_find_ahb_memctrl
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clr %o0
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.L_find_apb_memctrl:
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call _nomem_find_apb /* Scan for APB slave device */
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nop
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/* o3 = iobar address
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* o4 = AHB Bus index
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*
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* REG ADR = ((iobar >> 12) & (iobar << 4) & 0xfff00) | "APB Base"
|
||||
*/
|
||||
ld [%o3 + AMBA_APB_IOBAR_OFS], %o5
|
||||
srl %o5, 12, %o2
|
||||
sll %o5, 4, %o5
|
||||
and %o2, %o5, %o5
|
||||
set 0xfff00, %o2
|
||||
and %o2, %o5, %o5
|
||||
sethi %hi(0xfff00000), %o2
|
||||
and %o3, %o2, %o2
|
||||
or %o5, %o2, %o5 /* Register base address */
|
||||
|
||||
ba .L_call_one_mem_handler
|
||||
nop
|
||||
|
||||
.L_find_ahb_memctrl:
|
||||
call _nomem_find_ahb /* Scan for AHB Slave or Master.
|
||||
* o5 determine type. */
|
||||
nop
|
||||
clr %o5
|
||||
|
||||
/* Call the handler function if the hardware was found
|
||||
*
|
||||
* o0 = mem_handler
|
||||
* o1 = Configuration address
|
||||
* o2 = AHB Bus index
|
||||
* o3 = APB Base register (if APB Slave)
|
||||
*
|
||||
* Constraints:
|
||||
* i0-i7, l0, l1, l5, g1, g3-g7 may no be used.
|
||||
*/
|
||||
.L_call_one_mem_handler:
|
||||
cmp %o0, %g0
|
||||
be .L_all_mctrl_next
|
||||
mov %l0, %o0 /* Mem handler pointer */
|
||||
mov %o3, %o1 /* AMBA PnP Configuration address */
|
||||
mov %o4, %o2 /* AHB Bus index */
|
||||
ld [%l0 + MH_FUNC], %o7 /* Get Function pointer */
|
||||
call %o7
|
||||
mov %o5, %o3 /* APB Register Base Address */
|
||||
|
||||
inc %l1 /* Number of Memory controllers
|
||||
* handled. */
|
||||
|
||||
/* Do next entry in mem_handlers */
|
||||
.L_all_mctrl_next:
|
||||
ba .L_do_one_mem_handler
|
||||
add %l0, MH_STRUCT_SIZE, %l0
|
||||
|
||||
.L_all_mctrl_handled:
|
||||
mov %g1, %o7 /* Restore return address */
|
||||
retl
|
||||
mov %l1, %o0
|
||||
|
||||
|
||||
|
||||
/* Generic Memory controller initialization routine (APB Registers)
|
||||
*
|
||||
* o0 = mem_handler structure pointer
|
||||
* o1 = Configuration address
|
||||
* o2 = AHB Bus index
|
||||
* o3 = APB Base register
|
||||
*
|
||||
* Clobbered
|
||||
* o0-o4
|
||||
*/
|
||||
_nomem_mctrl_init:
|
||||
ld [%o0 + MH_PRIV], %o0 /* Get Private structure */
|
||||
ld [%o0], %o1 /* Get Reg Mask */
|
||||
and %o1, 0xff, %o1
|
||||
add %o0, REGS_OFS, %o0 /* Point to first reg */
|
||||
.L_do_one_reg:
|
||||
andcc %o1, 0x1, %g0
|
||||
beq .L_do_next_reg
|
||||
ld [%o0], %o2
|
||||
ld [%o3], %o4
|
||||
and %o4, %o2, %o4
|
||||
ld [%o0 + 4], %o2
|
||||
or %o4, %o2, %o4
|
||||
st %o4, [%o3]
|
||||
|
||||
.L_do_next_reg:
|
||||
add %o0, REGS_SIZE, %o0
|
||||
add %o3, 4, %o3
|
||||
srl %o1, 1, %o1
|
||||
cmp %o1, 0
|
||||
bne .L_do_one_reg
|
||||
nop
|
||||
|
||||
/* No more registers to write */
|
||||
retl
|
||||
nop
|
||||
|
||||
|
||||
|
||||
/* Generic Memory controller initialization routine (AHB Registers)
|
||||
*
|
||||
* o0 = mem_handler structure pointer
|
||||
* o1 = Configuration address of memory controller
|
||||
* o2 = AHB Bus index
|
||||
*
|
||||
* Clobbered
|
||||
* o0-o5
|
||||
*/
|
||||
_nomem_ahbmctrl_init:
|
||||
ld [%o0 + MH_PRIV], %o0 /* Get Private structure */
|
||||
|
||||
/* Get index of AHB MBAR to get registers from */
|
||||
ld [%o0], %o5
|
||||
add %o0, 4, %o0
|
||||
|
||||
/* Get Address of MBAR in PnP info */
|
||||
add %o5, 4, %o5
|
||||
sll %o5, 2, %o5
|
||||
add %o5, %o1, %o5 /* Address of MBAR */
|
||||
|
||||
/* Get Address of registers from PnP information
|
||||
* Address is in AHB I/O format, i.e. relative to bus
|
||||
*
|
||||
* ADR = (iobar & (iobar << 16) & 0xfff00000)
|
||||
* IOADR = (ADR >> 12) | "APB Base"
|
||||
*/
|
||||
ld [%o5], %o5
|
||||
sll %o5, 16, %o4
|
||||
and %o5, %o4, %o5
|
||||
sethi %hi(0xfff00000), %o4
|
||||
and %o5, %o4, %o5 /* ADR */
|
||||
and %o4, %o1, %o4
|
||||
srl %o5, 12, %o5
|
||||
or %o5, %o4, %o3 /* IOADR in o3 */
|
||||
|
||||
ld [%o0], %o1 /* Get Reg Mask */
|
||||
and %o1, 0xff, %o1
|
||||
add %o0, REGS_OFS, %o0 /* Point to first reg */
|
||||
.L_do_one_ahbreg:
|
||||
andcc %o1, 0x1, %g0
|
||||
beq .L_do_next_reg
|
||||
ld [%o0], %o2
|
||||
ld [%o3], %o4
|
||||
and %o4, %o2, %o4
|
||||
ld [%o0 + 4], %o2
|
||||
or %o4, %o2, %o4
|
||||
st %o4, [%o3]
|
||||
|
||||
.L_do_next_ahbreg:
|
||||
add %o0, REGS_SIZE, %o0
|
||||
add %o3, 4, %o3
|
||||
srl %o1, 1, %o1
|
||||
cmp %o1, 0
|
||||
bne .L_do_one_reg
|
||||
nop
|
||||
|
||||
/* No more registers to write */
|
||||
retl
|
||||
nop
|
||||
|
|
@ -13,6 +13,12 @@
|
|||
#include <asm/stack.h>
|
||||
#include <asm/leon.h>
|
||||
#include <version.h>
|
||||
#include <ambapp.h>
|
||||
|
||||
/* Default Plug&Play I/O area */
|
||||
#ifndef CONFIG_AMBAPP_IOAREA
|
||||
#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
|
||||
#endif
|
||||
|
||||
/* Entry for traps which jump to a programmer-specified trap handler. */
|
||||
#define TRAPR(H) \
|
||||
|
|
@ -208,6 +214,7 @@ version_string:
|
|||
.ascii U_BOOT_VERSION_STRING, "\0"
|
||||
|
||||
.section ".text"
|
||||
.extern _nomem_amba_init, _nomem_memory_ctrl_init
|
||||
.align 4
|
||||
|
||||
_hardreset:
|
||||
|
|
@ -259,6 +266,38 @@ stackp:
|
|||
andn %fp, 0x0f, %fp
|
||||
sub %fp, 64, %sp
|
||||
|
||||
/* Obtain the address of _GLOBAL_OFFSET_TABLE_ */
|
||||
SPARC_PIC_THUNK_CALL(l7)
|
||||
|
||||
/* Scan AMBA Bus for AMBA buses using PnP information. All found
|
||||
* AMBA buses I/O area will be located in i0-i5 upon return.
|
||||
* The i0-i5 registers are later used by _nomem_amba_init2
|
||||
*/
|
||||
ambainit:
|
||||
call _nomem_amba_init
|
||||
sethi %hi(CONFIG_AMBAPP_IOAREA), %o0
|
||||
|
||||
/* Scan AMBA Buses for memory controllers, then initialize the
|
||||
* memory controllers. Note that before setting up the memory controller
|
||||
* the stack can not be used.
|
||||
*/
|
||||
memory_ctrl_init:
|
||||
SPARC_LOAD_ADDRESS(grlib_mctrl_handlers, l7, o0)
|
||||
|
||||
call _nomem_memory_ctrl_init
|
||||
nop
|
||||
|
||||
/* The return valu indicate how many memory controllers where found and
|
||||
* initialized, if no memory controller was initialized, we can not continue
|
||||
* because from here on we expect memory to be working.
|
||||
*/
|
||||
cmp %o0, 0
|
||||
memory_ctrl_init_failed:
|
||||
beq memory_ctrl_init_failed
|
||||
nop
|
||||
|
||||
/*** From now on the stack can be used. ***/
|
||||
|
||||
cpu_init_unreloc:
|
||||
call cpu_init_f
|
||||
nop
|
||||
|
|
@ -269,7 +308,6 @@ cpu_init_unreloc:
|
|||
/* un relocated end address of monitor */
|
||||
#define DATA_END __init_end
|
||||
|
||||
SPARC_PIC_THUNK_CALL(l7)
|
||||
reloc:
|
||||
SPARC_LOAD_ADDRESS(TEXT_START, l7, g2)
|
||||
SPARC_LOAD_ADDRESS(DATA_END, l7, g3)
|
||||
|
|
@ -389,6 +427,7 @@ jump:
|
|||
|
||||
SPARC_LOAD_ADDRESS(board_init_f, l7, o1)
|
||||
set CONFIG_SYS_RELOC_MONITOR_BASE,%o2
|
||||
SPARC_LOAD_ADDRESS(TEXT_START, l7, g1)
|
||||
add %o1,%o2,%o1
|
||||
sub %o1,%g1,%o1
|
||||
call %o1
|
||||
|
|
|
|||
|
|
@ -312,31 +312,36 @@
|
|||
|
||||
#define CONFIG_SYS_GRLIB_SDRAM 0
|
||||
|
||||
/* No SDRAM Configuration */
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
|
||||
|
||||
/* See, GRLIB Docs (grip.pdf) on how to set up
|
||||
* These the memory controller registers.
|
||||
*/
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG1 (0x10f800ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
|
||||
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
|
||||
#else
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x82205260
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82205260
|
||||
#endif
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG3 0x0809a000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x0809a000
|
||||
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x10f800ff | (1<<11))
|
||||
/* GRLIB FT-MCTRL configuration */
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
|
||||
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
|
||||
#else
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82205260
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82205260
|
||||
#endif
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x0809a000
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x0809a000
|
||||
|
||||
/* no DDR controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR_CFG 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
|
||||
|
||||
/* no DDR2 Controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
|
||||
|
||||
/* Identification string */
|
||||
#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-CPCI-AX2000"
|
||||
|
|
|
|||
|
|
@ -289,21 +289,29 @@
|
|||
|
||||
#define CONFIG_SYS_GRLIB_SDRAM 0
|
||||
|
||||
/* No SDRAM Configuration */
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
|
||||
|
||||
/* See, GRLIB Docs (grip.pdf) on how to set up
|
||||
* These the memory controller registers.
|
||||
*/
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG1 (0x10f800ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG3 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
|
||||
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x10f800ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x00000000
|
||||
/* GRLIB FT-MCTRL configuration */
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
|
||||
|
||||
#define CONFIG_SYS_GRLIB_DDR_CFG 0xa900830a
|
||||
/* DDR controller */
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
|
||||
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
|
||||
/* no DDR2 Controller */
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
|
||||
|
||||
/* Identification string */
|
||||
#define CONFIG_IDENT_STRING "GAISLER LEON3 EP2S60"
|
||||
|
|
|
|||
|
|
@ -252,23 +252,28 @@
|
|||
|
||||
#define CONFIG_SYS_GRLIB_SDRAM 0
|
||||
|
||||
/* No SDRAM Configuration */
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
|
||||
|
||||
/* See, GRLIB Docs (grip.pdf) on how to set up
|
||||
* These the memory controller registers.
|
||||
*/
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000
|
||||
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x00136000
|
||||
/* GRLIB FT-MCTRL configuration */
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000
|
||||
|
||||
/* no DDR controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR_CFG 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
|
||||
|
||||
/* no DDR2 Controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
|
||||
|
||||
/* Identification string */
|
||||
#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-XC3S-1500"
|
||||
|
|
|
|||
|
|
@ -264,25 +264,33 @@
|
|||
#define CONFIG_SYS_GRLIB_SDRAM 0
|
||||
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
|
||||
|
||||
/* No SDRAM Configuration */
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
|
||||
|
||||
/* LEON2 MCTRL configuration */
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11))
|
||||
#if CONFIG_GRSIM
|
||||
/* GRSIM configuration */
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
|
||||
#else
|
||||
/* TSIM configuration */
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG2 0x81805220
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x81805220
|
||||
#endif
|
||||
#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000
|
||||
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000
|
||||
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_FT_MEMCFG3 0x00136000
|
||||
/* GRLIB FT-MCTRL configuration */
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11))
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
|
||||
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000
|
||||
|
||||
/* no DDR controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR_CFG 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
|
||||
|
||||
/* no DDR2 Controller */
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
|
||||
#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
|
||||
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
|
||||
|
||||
/* default kernel command line */
|
||||
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user