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rockchip: clk: rk3368: add support for configuring the SPI clocks
As SPI support may be useful in the boot-flow, this adds support for configuring the SPI controller's clocks in the RK3368 clock driver. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -282,32 +282,6 @@ static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
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}
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}
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#endif
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#endif
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static ulong rk3368_clk_get_rate(struct clk *clk)
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{
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struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
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ulong rate = 0;
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debug("%s: id %ld\n", __func__, clk->id);
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switch (clk->id) {
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case PLL_CPLL:
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rate = rkclk_pll_get_rate(priv->cru, CPLL);
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break;
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case PLL_GPLL:
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rate = rkclk_pll_get_rate(priv->cru, GPLL);
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break;
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#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
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case HCLK_SDMMC:
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case HCLK_EMMC:
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rate = rk3368_mmc_get_clk(priv->cru, clk->id);
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break;
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#endif
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default:
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return -ENOENT;
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}
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return rate;
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}
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#if IS_ENABLED(CONFIG_TPL_BUILD)
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#if IS_ENABLED(CONFIG_TPL_BUILD)
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static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
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static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
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{
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{
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@ -351,6 +325,110 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
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}
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}
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#endif
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#endif
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/*
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* RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
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* to select either CPLL or GPLL as the clock-parent. The location within
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* the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
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*/
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struct spi_clkreg {
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uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
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uint8_t div_shift;
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uint8_t sel_shift;
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};
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/*
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* The entries are numbered relative to their offset from SCLK_SPI0.
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*/
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static const struct spi_clkreg spi_clkregs[] = {
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[0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
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[1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
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[2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
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};
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static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
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{
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return (val >> shift) & ((1 << width) - 1);
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}
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static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
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{
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const struct spi_clkreg *spiclk = NULL;
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u32 div, val;
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switch (clk_id) {
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case SCLK_SPI0 ... SCLK_SPI2:
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spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
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break;
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default:
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error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
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return -EINVAL;
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}
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val = readl(&cru->clksel_con[spiclk->reg]);
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div = extract_bits(val, 7, spiclk->div_shift);
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debug("%s: div 0x%x\n", __func__, div);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
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{
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const struct spi_clkreg *spiclk = NULL;
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
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assert(src_clk_div < 127);
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switch (clk_id) {
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case SCLK_SPI0 ... SCLK_SPI2:
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spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
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break;
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default:
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error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
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return -EINVAL;
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}
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rk_clrsetreg(&cru->clksel_con[spiclk->reg],
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((0x7f << spiclk->div_shift) |
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(0x1 << spiclk->sel_shift)),
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((src_clk_div << spiclk->div_shift) |
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(1 << spiclk->sel_shift)));
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return rk3368_spi_get_clk(cru, clk_id);
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}
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static ulong rk3368_clk_get_rate(struct clk *clk)
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{
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struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
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ulong rate = 0;
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debug("%s: id %ld\n", __func__, clk->id);
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switch (clk->id) {
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case PLL_CPLL:
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rate = rkclk_pll_get_rate(priv->cru, CPLL);
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break;
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case PLL_GPLL:
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rate = rkclk_pll_get_rate(priv->cru, GPLL);
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break;
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case SCLK_SPI0 ... SCLK_SPI2:
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rate = rk3368_spi_get_clk(priv->cru, clk->id);
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break;
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#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
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case HCLK_SDMMC:
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case HCLK_EMMC:
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rate = rk3368_mmc_get_clk(priv->cru, clk->id);
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break;
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#endif
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default:
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return -ENOENT;
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}
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return rate;
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}
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static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
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static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
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{
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{
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__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
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__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
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@ -358,6 +436,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
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debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
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debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
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switch (clk->id) {
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switch (clk->id) {
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case SCLK_SPI0 ... SCLK_SPI2:
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ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
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break;
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#if IS_ENABLED(CONFIG_TPL_BUILD)
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#if IS_ENABLED(CONFIG_TPL_BUILD)
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case CLK_DDR:
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case CLK_DDR:
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ret = rk3368_ddr_set_clk(priv->cru, rate);
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ret = rk3368_ddr_set_clk(priv->cru, rate);
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