mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
arm: davinci: remove leftover code for dm* SoCs
The support for DaVinci DM* SoCs has been dropped a while ago. There's still a lot of leftover code in mach-davinci though. Entirely remove certain files and modify the common code to no longer reference unsupported chips. Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX but not all define SOC_DA850 (e.g. omapl138). We can safely remove all ifdefs for the former, but let's leave the ones for the latter. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Bartosz Golaszewski
Tom Rini
parent
028020247d
commit
cef443c166
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@ -27,25 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV9 0x174
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/* SOC-specific pll info */
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#ifdef CONFIG_SOC_DM355
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#define ARM_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DM644X
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV2
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#endif
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#ifdef CONFIG_SOC_DM646X
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DA8XX
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unsigned int sysdiv[9] = {
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PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
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PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
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@ -110,103 +91,6 @@ int set_cpu_clk_info(void)
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return 0;
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}
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#else /* CONFIG_SOC_DA8XX */
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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{
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u32 div;
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div = REG(pllbase + offset);
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return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
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}
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static inline unsigned pll_prediv(volatile void *pllbase)
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{
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#ifdef CONFIG_SOC_DM355
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/* this register read seems to fail on pll0 */
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return 8;
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else
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return pll_div(pllbase, PLLC_PREDIV);
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#elif defined(CONFIG_SOC_DM365)
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return pll_div(pllbase, PLLC_PREDIV);
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#endif
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return 1;
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}
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static inline unsigned pll_postdiv(volatile void *pllbase)
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{
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#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
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return pll_div(pllbase, PLLC_POSTDIV);
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#elif defined(CONFIG_SOC_DM6446)
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return pll_div(pllbase, PLLC_POSTDIV);
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#endif
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return 1;
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}
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static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
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{
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volatile void *pllbase = (volatile void *) pll_addr;
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#ifdef CONFIG_SOC_DM646X
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unsigned base = CONFIG_REFCLK_FREQ / 1000;
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#else
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unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
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#endif
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/* the PLL might be bypassed */
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if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
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base /= pll_prediv(pllbase);
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#if defined(CONFIG_SOC_DM365)
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base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
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#else
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base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
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#endif
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base /= pll_postdiv(pllbase);
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}
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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}
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#ifdef DAVINCI_DM6467EVM
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unsigned int davinci_arm_clk_get()
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{
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
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}
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#endif
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#if defined(CONFIG_SOC_DM365)
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unsigned int davinci_clk_get(unsigned int div)
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{
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return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
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}
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#endif
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int set_cpu_clk_info(void)
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{
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unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#if defined(CONFIG_SOC_DM365)
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pllbase = DAVINCI_PLL_CNTRL1_BASE;
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#endif
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gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
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#ifdef DSP_PLLDIV
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gd->bd->bi_dsp_freq =
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
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#else
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gd->bd->bi_dsp_freq = 0;
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#endif
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pllbase = DAVINCI_PLL_CNTRL1_BASE;
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#if defined(CONFIG_SOC_DM365)
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pllbase = DAVINCI_PLL_CNTRL0_BASE;
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#endif
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gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
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return 0;
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}
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#endif /* !CONFIG_SOC_DA8XX */
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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@ -1,29 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SoC-specific code for tms320dm355 and similar chips
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*
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* Copyright (C) 2009 David Brownell
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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void davinci_enable_uart0(void)
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{
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lpsc_on(DAVINCI_LPSC_UART0);
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x00006001;
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}
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#ifdef CONFIG_SYS_I2C_DAVINCI
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void davinci_enable_i2c(void)
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{
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lpsc_on(DAVINCI_LPSC_I2C);
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/* Enable I2C pin Mux */
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REG(PINMUX3) |= (1 << 20) | (1 << 19);
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}
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#endif
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@ -1,19 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SoC-specific code for tms320dm365 and similar chips
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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void davinci_enable_uart0(void)
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{
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lpsc_on(DAVINCI_LPSC_UART0);
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}
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#ifdef CONFIG_SYS_I2C_DAVINCI
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void davinci_enable_i2c(void)
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{
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lpsc_on(DAVINCI_LPSC_I2C);
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}
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#endif
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@ -1,459 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SoC-specific lowlevel code for tms320dm365 and similar chips
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* Actually used for booting from NAND with nand_spl.
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#include <common.h>
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#include <nand.h>
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#include <ns16550.h>
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#include <post.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/dm365_lowlevel.h>
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#include <asm/arch/hardware.h>
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void dm365_waitloop(unsigned long loopcnt)
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{
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unsigned long i;
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for (i = 0; i < loopcnt; i++)
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asm(" NOP");
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}
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int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
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{
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unsigned int clksrc = 0x0;
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/* Power up the PLL */
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
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setbits_le32(&dv_pll0_regs->pllctl,
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clksrc << PLLCTL_CLOCK_MODE_SHIFT);
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/*
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* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
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dm365_waitloop(150);
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/* PLLRST=1(reset assert) */
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setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
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dm365_waitloop(300);
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/*Bring PLL out of Reset*/
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
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/* Program the Multiper and Pre-Divider for PLL1 */
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writel(pllmult, &dv_pll0_regs->pllm);
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writel(prediv, &dv_pll0_regs->prediv);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
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PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
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&dv_pll0_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
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/* Program the PostDiv for PLL1 */
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writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
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/* Post divider setting for PLL1 */
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
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dm365_waitloop(300);
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/* Set the GOSET bit */
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writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
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dm365_waitloop(300);
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/* Wait for PLL to LOCK */
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while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
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== PLL0_LOCK))
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;
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/* Enable the PLL Bit of PLLCTL*/
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setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
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return 0;
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}
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int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
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{
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unsigned int clksrc = 0x0;
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/* Power up the PLL*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
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/*
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* Select the Clock Mode as Onchip Oscilator or External Clock on
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* MXI pin
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* VDB has input on MXI pin
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*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
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setbits_le32(&dv_pll1_regs->pllctl,
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clksrc << PLLCTL_CLOCK_MODE_SHIFT);
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/*
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* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
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dm365_waitloop(50);
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/* PLLRST=1(reset assert) */
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setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
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dm365_waitloop(300);
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/* Bring PLL out of Reset */
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
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/* Program the Multiper and Pre-Divider for PLL2 */
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writel(pllm, &dv_pll1_regs->pllm);
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writel(prediv, &dv_pll1_regs->prediv);
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writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
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PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
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&dv_pll1_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
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/* Post divider setting for PLL2 */
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
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/* GoCmd for PostDivider to take effect */
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writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
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dm365_waitloop(150);
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/* Wait for PLL to LOCK */
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while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
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== PLL1_LOCK))
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;
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dm365_waitloop(4100);
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/* Enable the PLL2 */
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setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
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/* do this after PLL's have been set up */
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writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
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&dv_sys_module_regs->peri_clkctl);
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return 0;
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}
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int dm365_ddr_setup(void)
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{
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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clrbits_le32(&dv_sys_module_regs->vtpiocr,
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VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
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/* Set bit CLRZ (bit 13) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
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/* Check VTP READY Status */
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while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
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;
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/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
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/* Set bit LOCK(bit7) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
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/*
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* Powerdown VTP as it is locked (bit 6)
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* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
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*/
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setbits_le32(&dv_sys_module_regs->vtpiocr,
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VPTIO_IOPWRDN | VPTIO_PWRDN);
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/* Wait for calibration to complete */
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dm365_waitloop(150);
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/* Set the DDR2 to synreset, then enable it again */
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lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
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/* Program SDRAM Bank Config Register */
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writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
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&dv_ddr2_regs_ctrl->sdbcr);
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writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
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&dv_ddr2_regs_ctrl->sdbcr);
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/* Program SDRAM Timing Control Register1 */
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writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
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/* Program SDRAM Timing Control Register2 */
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writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
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writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
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writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
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/* Program SDRAM Refresh Control Register */
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writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
|
||||
|
||||
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
|
||||
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dm365_vpss_sync_reset(void)
|
||||
{
|
||||
unsigned int PdNum = 0;
|
||||
|
||||
/* VPSS_CLKMD 1:1 */
|
||||
setbits_le32(&dv_sys_module_regs->vpss_clkctl,
|
||||
VPSS_CLK_CTL_VPSS_CLKMD);
|
||||
|
||||
/* LPSC SyncReset DDR Clock Enable */
|
||||
writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
|
||||
~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
|
||||
&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
|
||||
|
||||
writel((1 << PdNum), &dv_psc_regs->ptcmd);
|
||||
|
||||
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
|
||||
;
|
||||
while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
|
||||
PSC_MD_STATE_MSK) == PSC_SYNCRESET))
|
||||
;
|
||||
}
|
||||
|
||||
static void dm365_por_reset(void)
|
||||
{
|
||||
struct davinci_timer *wdog =
|
||||
(struct davinci_timer *)DAVINCI_WDOG_BASE;
|
||||
|
||||
if (readl(&dv_pll0_regs->rstype) &
|
||||
(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
|
||||
dm365_vpss_sync_reset();
|
||||
|
||||
writel(DV_TMPBUF_VAL, TMPBUF);
|
||||
setbits_le32(TMPSTATUS, FLAG_PORRST);
|
||||
writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
|
||||
writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
|
||||
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
static void dm365_wdt_reset(void)
|
||||
{
|
||||
struct davinci_timer *wdog =
|
||||
(struct davinci_timer *)DAVINCI_WDOG_BASE;
|
||||
|
||||
if (readl(TMPBUF) != DV_TMPBUF_VAL) {
|
||||
writel(DV_TMPBUF_VAL, TMPBUF);
|
||||
setbits_le32(TMPSTATUS, FLAG_PORRST);
|
||||
setbits_le32(TMPSTATUS, FLAG_FLGOFF);
|
||||
|
||||
dm365_waitloop(100);
|
||||
|
||||
dm365_vpss_sync_reset();
|
||||
|
||||
writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
|
||||
writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
|
||||
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
static void dm365_wdt_flag_on(void)
|
||||
{
|
||||
/* VPSS_CLKMD 1:2 */
|
||||
clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
|
||||
VPSS_CLK_CTL_VPSS_CLKMD);
|
||||
writel(0, TMPBUF);
|
||||
setbits_le32(TMPSTATUS, FLAG_FLGON);
|
||||
}
|
||||
|
||||
void dm365_psc_init(void)
|
||||
{
|
||||
unsigned char i = 0;
|
||||
unsigned char lpsc_start;
|
||||
unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
|
||||
unsigned int PdNum = 0;
|
||||
|
||||
lpscmin = 0;
|
||||
lpscmax = 2;
|
||||
|
||||
for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
|
||||
if (lpscgroup == 0) {
|
||||
/* Enabling LPSC 3 to 28 SCR first */
|
||||
lpsc_start = DAVINCI_LPSC_VPSSMSTR;
|
||||
lpsc_end = DAVINCI_LPSC_TIMER1;
|
||||
} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
|
||||
lpsc_start = DAVINCI_LPSC_CFG5;
|
||||
lpsc_end = DAVINCI_LPSC_VPSSMASTER;
|
||||
} else {
|
||||
lpsc_start = DAVINCI_LPSC_MJCP;
|
||||
lpsc_end = DAVINCI_LPSC_HDVICP;
|
||||
}
|
||||
|
||||
/* NEXT=0x3, Enable LPSC's */
|
||||
for (i = lpsc_start; i <= lpsc_end; i++)
|
||||
setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
|
||||
|
||||
/*
|
||||
* Program goctl to start transition sequence for LPSCs
|
||||
* CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
|
||||
* Domain 0 Modules
|
||||
*/
|
||||
writel((1 << PdNum), &dv_psc_regs->ptcmd);
|
||||
|
||||
/*
|
||||
* Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
|
||||
*/
|
||||
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
|
||||
== 0))
|
||||
;
|
||||
|
||||
/* Wait for MODSTAT = ENABLE from LPSC's */
|
||||
for (i = lpsc_start; i <= lpsc_end; i++)
|
||||
while (!((readl(&dv_psc_regs->mdstat[i]) &
|
||||
PSC_MD_STATE_MSK) == PSC_ENABLE))
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
static void dm365_emif_init(void)
|
||||
{
|
||||
writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
|
||||
writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
|
||||
|
||||
setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
|
||||
|
||||
writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
|
||||
unsigned long value)
|
||||
{
|
||||
clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
|
||||
setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
|
||||
}
|
||||
|
||||
__attribute__((weak))
|
||||
void board_gpio_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
int post_log(char *format, ...)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void dm36x_lowlevel_init(ulong bootflag)
|
||||
{
|
||||
struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
|
||||
(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
|
||||
DAVINCI_UART_CTRL_BASE);
|
||||
|
||||
/* Mask all interrupts */
|
||||
writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
|
||||
writel(0x0, &dv_aintc_regs->eabase);
|
||||
writel(0x0, &dv_aintc_regs->eint0);
|
||||
writel(0x0, &dv_aintc_regs->eint1);
|
||||
|
||||
/* Clear all interrupts */
|
||||
writel(0xffffffff, &dv_aintc_regs->fiq0);
|
||||
writel(0xffffffff, &dv_aintc_regs->fiq1);
|
||||
writel(0xffffffff, &dv_aintc_regs->irq0);
|
||||
writel(0xffffffff, &dv_aintc_regs->irq1);
|
||||
|
||||
dm365_por_reset();
|
||||
dm365_wdt_reset();
|
||||
|
||||
/* System PSC setup - enable all */
|
||||
dm365_psc_init();
|
||||
|
||||
/* Setup Pinmux */
|
||||
dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
|
||||
dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
|
||||
dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
|
||||
dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
|
||||
dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
|
||||
|
||||
/* PLL setup */
|
||||
dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
|
||||
CONFIG_SYS_DM36x_PLL1_PREDIV);
|
||||
dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
|
||||
CONFIG_SYS_DM36x_PLL2_PREDIV);
|
||||
|
||||
/* GPIO setup */
|
||||
board_gpio_init();
|
||||
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
/*
|
||||
* Fix Power and Emulation Management Register
|
||||
* see sprufh2.pdf page 38 Table 22
|
||||
*/
|
||||
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
|
||||
DAVINCI_UART_PWREMU_MGMT_UTRST),
|
||||
&davinci_uart_ctrl_regs->pwremu_mgmt);
|
||||
|
||||
puts("ddr init\n");
|
||||
dm365_ddr_setup();
|
||||
|
||||
puts("emif init\n");
|
||||
dm365_emif_init();
|
||||
|
||||
dm365_wdt_flag_on();
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Do memory tests, calls arch_memory_failure_handle()
|
||||
* if error detected.
|
||||
*/
|
||||
memory_post_test(0);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* SoC-specific code for tms320dm644x chips
|
||||
*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
|
||||
* Copyright (C) 2004 Texas Instruments.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
|
||||
#define PINMUX0_EMACEN (1 << 31)
|
||||
#define PINMUX0_AECS5 (1 << 11)
|
||||
#define PINMUX0_AECS4 (1 << 10)
|
||||
|
||||
#define PINMUX1_I2C (1 << 7)
|
||||
#define PINMUX1_UART1 (1 << 1)
|
||||
#define PINMUX1_UART0 (1 << 0)
|
||||
|
||||
|
||||
void davinci_enable_uart0(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_LPSC_UART0);
|
||||
|
||||
/* Bringup UART0 out of reset */
|
||||
REG(UART0_PWREMU_MGMT) = 0x00006001;
|
||||
|
||||
/* Enable UART0 MUX lines */
|
||||
REG(PINMUX1) |= PINMUX1_UART0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC
|
||||
void davinci_enable_emac(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_LPSC_EMAC);
|
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
|
||||
lpsc_on(DAVINCI_LPSC_MDIO);
|
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */
|
||||
REG(VDD3P3V_PWDN) = 0;
|
||||
|
||||
/* Enable EMAC. */
|
||||
REG(PINMUX0) |= PINMUX0_EMACEN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_DAVINCI
|
||||
void davinci_enable_i2c(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_LPSC_I2C);
|
||||
|
||||
/* Enable I2C pin Mux */
|
||||
REG(PINMUX1) |= PINMUX1_I2C;
|
||||
}
|
||||
#endif
|
||||
|
||||
void davinci_errata_workarounds(void)
|
||||
{
|
||||
/*
|
||||
* Workaround for TMS320DM6446 errata 1.3.22:
|
||||
* PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
|
||||
* Revision(s) Affected: 1.3 and earlier
|
||||
*/
|
||||
REG(PSC_SILVER_BULLET) = 0;
|
||||
|
||||
/*
|
||||
* Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
|
||||
* as suggested in TMS320DM6446 errata 2.1.2:
|
||||
*
|
||||
* On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
|
||||
* low priority modules can occupy the bus and prevent high priority
|
||||
* modules like the VPSS from getting the required DDR2 throughput.
|
||||
* A hex value of 0x20 should provide a good ARM (cache enabled)
|
||||
* performance and still allow good utilization by the VPSS or other
|
||||
* modules.
|
||||
*/
|
||||
REG(VBPR) = 0x20;
|
||||
}
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* SoC-specific code for TMS320DM646x chips
|
||||
*/
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
void davinci_enable_uart0(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_DM646X_LPSC_UART0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC
|
||||
void davinci_enable_emac(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_DAVINCI
|
||||
void davinci_enable_i2c(void)
|
||||
{
|
||||
lpsc_on(DAVINCI_DM646X_LPSC_I2C);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -40,13 +40,11 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
|
|||
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
|
||||
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
|
||||
int n_items);
|
||||
#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
|
||||
#if defined(CONFIG_DRIVER_TI_EMAC)
|
||||
void davinci_emac_mii_mode_sel(int mode_sel);
|
||||
#endif
|
||||
#if defined(CONFIG_SOC_DA8XX)
|
||||
void irq_init(void);
|
||||
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
|
||||
const int n_items);
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
|
|
|||
|
|
@ -23,50 +23,15 @@
|
|||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#ifdef CONFIG_SOC_DM365
|
||||
#define EMAC_BASE_ADDR (0x01d07000)
|
||||
#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
|
||||
#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
|
||||
#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
#elif defined(CONFIG_SOC_DA8XX)
|
||||
#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
|
||||
#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
|
||||
#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
|
||||
#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
#else
|
||||
#define EMAC_BASE_ADDR (0x01c80000)
|
||||
#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
|
||||
#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
|
||||
#define EMAC_MDIO_BASE_ADDR (0x01c84000)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_DM646X
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
#define DAVINCI_EMAC_GIG_ENABLE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_DM646X
|
||||
/* MDIO module input frequency */
|
||||
#define EMAC_MDIO_BUS_FREQ 76500000
|
||||
/* MDIO clock output frequency */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
|
||||
#elif defined(CONFIG_SOC_DM365)
|
||||
/* MDIO module input frequency */
|
||||
#define EMAC_MDIO_BUS_FREQ 121500000
|
||||
/* MDIO clock output frequency */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
|
||||
#elif defined(CONFIG_SOC_DA8XX)
|
||||
/* MDIO module input frequency */
|
||||
#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
|
||||
/* MDIO clock output frequency */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
|
||||
#else
|
||||
/* MDIO module input frequency */
|
||||
#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
|
||||
/* MDIO clock output frequency */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
|
||||
#endif
|
||||
|
||||
#endif /* _DM644X_EMAC_H_ */
|
||||
|
|
|
|||
|
|
@ -5,21 +5,12 @@
|
|||
#ifndef _GPIO_DEFS_H_
|
||||
#define _GPIO_DEFS_H_
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
#define DAVINCI_GPIO_BINTEN 0x01C67008
|
||||
#define DAVINCI_GPIO_BANK01 0x01C67010
|
||||
#define DAVINCI_GPIO_BANK23 0x01C67038
|
||||
#define DAVINCI_GPIO_BANK45 0x01C67060
|
||||
#define DAVINCI_GPIO_BANK67 0x01C67088
|
||||
|
||||
#else /* CONFIG_SOC_DA8XX */
|
||||
#define DAVINCI_GPIO_BINTEN 0x01E26008
|
||||
#define DAVINCI_GPIO_BANK01 0x01E26010
|
||||
#define DAVINCI_GPIO_BANK23 0x01E26038
|
||||
#define DAVINCI_GPIO_BANK45 0x01E26060
|
||||
#define DAVINCI_GPIO_BANK67 0x01E26088
|
||||
#define DAVINCI_GPIO_BANK8 0x01E260B0
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
|
||||
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
|
||||
|
|
@ -31,10 +22,7 @@
|
|||
#define gpio_status() gpio_info()
|
||||
#endif
|
||||
#define GPIO_NAME_SIZE 20
|
||||
#if defined(CONFIG_SOC_DM644X)
|
||||
/* GPIO0 to GPIO53, omit the V3.3 volts one */
|
||||
#define MAX_NUM_GPIOS 70
|
||||
#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
|
||||
#if !defined(CONFIG_SOC_DA850)
|
||||
#define MAX_NUM_GPIOS 128
|
||||
#else
|
||||
#define MAX_NUM_GPIOS 144
|
||||
|
|
|
|||
|
|
@ -23,89 +23,6 @@ typedef volatile unsigned int dv_reg;
|
|||
typedef volatile unsigned int * dv_reg_p;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Base register addresses
|
||||
*
|
||||
* NOTE: some of these DM6446-specific addresses DO NOT WORK
|
||||
* on other DaVinci chips. Double check them before you try
|
||||
* using the addresses ... or PSC module identifiers, etc.
|
||||
*/
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
|
||||
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
|
||||
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
|
||||
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
|
||||
#define DAVINCI_UART0_BASE (0x01c20000)
|
||||
#define DAVINCI_UART1_BASE (0x01c20400)
|
||||
#define DAVINCI_TIMER3_BASE (0x01c20800)
|
||||
#define DAVINCI_I2C_BASE (0x01c21000)
|
||||
#define DAVINCI_TIMER0_BASE (0x01c21400)
|
||||
#define DAVINCI_TIMER1_BASE (0x01c21800)
|
||||
#define DAVINCI_WDOG_BASE (0x01c21c00)
|
||||
#define DAVINCI_PWM0_BASE (0x01c22000)
|
||||
#define DAVINCI_PWM1_BASE (0x01c22400)
|
||||
#define DAVINCI_PWM2_BASE (0x01c22800)
|
||||
#define DAVINCI_TIMER4_BASE (0x01c23800)
|
||||
#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
|
||||
#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
|
||||
#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
|
||||
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
|
||||
#define DAVINCI_ARM_INTC_BASE (0x01c48000)
|
||||
#define DAVINCI_USB_OTG_BASE (0x01c64000)
|
||||
#define DAVINCI_CFC_ATA_BASE (0x01c66000)
|
||||
#define DAVINCI_SPI_BASE (0x01c66800)
|
||||
#define DAVINCI_GPIO_BASE (0x01c67000)
|
||||
#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
|
||||
#if !defined(CONFIG_SOC_DM646X)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
|
||||
#endif
|
||||
#define DAVINCI_DDR_BASE (0x80000000)
|
||||
|
||||
#ifdef CONFIG_SOC_DM644X
|
||||
#define DAVINCI_UART2_BASE 0x01c20800
|
||||
#define DAVINCI_UHPI_BASE 0x01c67800
|
||||
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
|
||||
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
|
||||
#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
|
||||
#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
|
||||
#define DAVINCI_IMCOP_BASE 0x01cc0000
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
|
||||
#define DAVINCI_VLYNQ_BASE 0x01e01000
|
||||
#define DAVINCI_ASP_BASE 0x01e02000
|
||||
#define DAVINCI_MMC_SD_BASE 0x01e10000
|
||||
#define DAVINCI_MS_BASE 0x01e20000
|
||||
#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
|
||||
|
||||
#elif defined(CONFIG_SOC_DM355)
|
||||
#define DAVINCI_MMC_SD1_BASE 0x01e00000
|
||||
#define DAVINCI_ASP0_BASE 0x01e02000
|
||||
#define DAVINCI_ASP1_BASE 0x01e04000
|
||||
#define DAVINCI_UART2_BASE 0x01e06000
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
|
||||
#define DAVINCI_MMC_SD0_BASE 0x01e11000
|
||||
|
||||
#elif defined(CONFIG_SOC_DM365)
|
||||
#define DAVINCI_MMC_SD1_BASE 0x01d00000
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
|
||||
#define DAVINCI_MMC_SD0_BASE 0x01d11000
|
||||
#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
|
||||
#define DAVINCI_SPI0_BASE 0x01c66000
|
||||
#define DAVINCI_SPI1_BASE 0x01c66800
|
||||
|
||||
#elif defined(CONFIG_SOC_DM646X)
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
|
||||
|
||||
#endif
|
||||
|
||||
#else /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define DAVINCI_UART0_BASE 0x01c42000
|
||||
#define DAVINCI_UART1_BASE 0x01d0c000
|
||||
#define DAVINCI_UART2_BASE 0x01d0d000
|
||||
|
|
@ -162,66 +79,11 @@ typedef volatile unsigned int * dv_reg_p;
|
|||
#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
|
||||
#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
|
||||
#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */
|
||||
#define DAVINCI_GPSC_ARMDOMAIN 0
|
||||
#define DAVINCI_GPSC_DSPDOMAIN 1
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
|
||||
#define DAVINCI_LPSC_VPSSMSTR 0
|
||||
#define DAVINCI_LPSC_VPSSSLV 1
|
||||
#define DAVINCI_LPSC_TPCC 2
|
||||
#define DAVINCI_LPSC_TPTC0 3
|
||||
#define DAVINCI_LPSC_TPTC1 4
|
||||
#define DAVINCI_LPSC_EMAC 5
|
||||
#define DAVINCI_LPSC_EMAC_WRAPPER 6
|
||||
#define DAVINCI_LPSC_MDIO 7
|
||||
#define DAVINCI_LPSC_IEEE1394 8
|
||||
#define DAVINCI_LPSC_USB 9
|
||||
#define DAVINCI_LPSC_ATA 10
|
||||
#define DAVINCI_LPSC_VLYNQ 11
|
||||
#define DAVINCI_LPSC_UHPI 12
|
||||
#define DAVINCI_LPSC_DDR_EMIF 13
|
||||
#define DAVINCI_LPSC_AEMIF 14
|
||||
#define DAVINCI_LPSC_MMC_SD 15
|
||||
#define DAVINCI_LPSC_MEMSTICK 16
|
||||
#define DAVINCI_LPSC_McBSP 17
|
||||
#define DAVINCI_LPSC_I2C 18
|
||||
#define DAVINCI_LPSC_UART0 19
|
||||
#define DAVINCI_LPSC_UART1 20
|
||||
#define DAVINCI_LPSC_UART2 21
|
||||
#define DAVINCI_LPSC_SPI 22
|
||||
#define DAVINCI_LPSC_PWM0 23
|
||||
#define DAVINCI_LPSC_PWM1 24
|
||||
#define DAVINCI_LPSC_PWM2 25
|
||||
#define DAVINCI_LPSC_GPIO 26
|
||||
#define DAVINCI_LPSC_TIMER0 27
|
||||
#define DAVINCI_LPSC_TIMER1 28
|
||||
#define DAVINCI_LPSC_TIMER2 29
|
||||
#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
|
||||
#define DAVINCI_LPSC_ARM 31
|
||||
#define DAVINCI_LPSC_SCR2 32
|
||||
#define DAVINCI_LPSC_SCR3 33
|
||||
#define DAVINCI_LPSC_SCR4 34
|
||||
#define DAVINCI_LPSC_CROSSBAR 35
|
||||
#define DAVINCI_LPSC_CFG27 36
|
||||
#define DAVINCI_LPSC_CFG3 37
|
||||
#define DAVINCI_LPSC_CFG5 38
|
||||
#define DAVINCI_LPSC_GEM 39
|
||||
#define DAVINCI_LPSC_IMCOP 40
|
||||
#define DAVINCI_LPSC_VPSSMASTER 47
|
||||
#define DAVINCI_LPSC_MJCP 50
|
||||
#define DAVINCI_LPSC_HDVICP 51
|
||||
|
||||
#define DAVINCI_DM646X_LPSC_EMAC 14
|
||||
#define DAVINCI_DM646X_LPSC_UART0 26
|
||||
#define DAVINCI_DM646X_LPSC_I2C 31
|
||||
#define DAVINCI_DM646X_LPSC_TIMER0 34
|
||||
|
||||
#else /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define DAVINCI_LPSC_TPCC 0
|
||||
#define DAVINCI_LPSC_TPTC0 1
|
||||
#define DAVINCI_LPSC_TPTC1 2
|
||||
|
|
@ -283,8 +145,6 @@ typedef volatile unsigned int * dv_reg_p;
|
|||
#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
|
||||
#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
|
||||
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void lpsc_on(unsigned int id);
|
||||
void lpsc_syncreset(unsigned int id);
|
||||
|
|
@ -296,30 +156,6 @@ void davinci_enable_emac(void);
|
|||
void davinci_enable_i2c(void);
|
||||
void davinci_errata_workarounds(void);
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
|
||||
/* Some PSC defines */
|
||||
#define PSC_CHP_SHRTSW (0x01c40038)
|
||||
#define PSC_GBLCTL (0x01c41010)
|
||||
#define PSC_EPCPR (0x01c41070)
|
||||
#define PSC_EPCCR (0x01c41078)
|
||||
#define PSC_PTCMD (0x01c41120)
|
||||
#define PSC_PTSTAT (0x01c41128)
|
||||
#define PSC_PDSTAT (0x01c41200)
|
||||
#define PSC_PDSTAT1 (0x01c41204)
|
||||
#define PSC_PDCTL (0x01c41300)
|
||||
#define PSC_PDCTL1 (0x01c41304)
|
||||
|
||||
#define PSC_MDCTL_BASE (0x01c41a00)
|
||||
#define PSC_MDSTAT_BASE (0x01c41800)
|
||||
|
||||
#define VDD3P3V_PWDN (0x01c40048)
|
||||
#define UART0_PWREMU_MGMT (0x01c20030)
|
||||
|
||||
#define PSC_SILVER_BULLET (0x01c41a20)
|
||||
|
||||
#else /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define PSC_ENABLE 0x3
|
||||
#define PSC_DISABLE 0x2
|
||||
#define PSC_SYNCRESET 0x1
|
||||
|
|
@ -354,41 +190,9 @@ struct davinci_psc_regs {
|
|||
#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
|
||||
#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
|
||||
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#define PSC_MDSTAT_STATE 0x3f
|
||||
#define PSC_MDCTL_NEXT 0x07
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
|
||||
/* Miscellania... */
|
||||
#define VBPR (0x20000020)
|
||||
|
||||
/* NOTE: system control modules are *highly* chip-specific, both
|
||||
* as to register content (e.g. for muxing) and which registers exist.
|
||||
*/
|
||||
#define PINMUX0 0x01c40000
|
||||
#define PINMUX1 0x01c40004
|
||||
#define PINMUX2 0x01c40008
|
||||
#define PINMUX3 0x01c4000c
|
||||
#define PINMUX4 0x01c40010
|
||||
|
||||
struct davinci_uart_ctrl_regs {
|
||||
dv_reg revid1;
|
||||
dv_reg res;
|
||||
dv_reg pwremu_mgmt;
|
||||
dv_reg mdr;
|
||||
};
|
||||
|
||||
#define DAVINCI_UART_CTRL_BASE 0x28
|
||||
|
||||
/* UART PWREMU_MGMT definitions */
|
||||
#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
|
||||
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
|
||||
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
|
||||
|
||||
#else /* CONFIG_SOC_DA8XX */
|
||||
|
||||
struct davinci_pllc_regs {
|
||||
dv_reg revid;
|
||||
dv_reg rsvd1[56];
|
||||
|
|
@ -606,26 +410,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
|
|||
DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_DA8XX */
|
||||
|
||||
#if defined(CONFIG_SOC_DM365)
|
||||
#include <asm/arch/aintc_defs.h>
|
||||
#include <asm/arch/ddr2_defs.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pll_defs.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
#include <asm/arch/syscfg_defs.h>
|
||||
#include <asm/arch/timer_defs.h>
|
||||
|
||||
#define TMPBUF 0x00017ff8
|
||||
#define TMPSTATUS 0x00017ff0
|
||||
#define DV_TMPBUF_VAL 0x591b3ed7
|
||||
#define FLAG_PORRST 0x00000001
|
||||
#define FLAG_WDTRST 0x00000002
|
||||
#define FLAG_FLGON 0x00000004
|
||||
#define FLAG_FLGOFF 0x00000010
|
||||
|
||||
#endif
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
|
|
|
|||
|
|
@ -8,10 +8,6 @@
|
|||
#ifndef _I2C_DEFS_H_
|
||||
#define _I2C_DEFS_H_
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
#define I2C_BASE 0x01c21000
|
||||
#else
|
||||
#define I2C_BASE 0x01c22000
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,49 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*/
|
||||
#ifndef _DV_SYSCFG_DEFS_H_
|
||||
#define _DV_SYSCFG_DEFS_H_
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
/* System Control Module register structure for DM365 */
|
||||
struct dv_sys_module_regs {
|
||||
unsigned int pinmux[5]; /* 0x00 */
|
||||
unsigned int bootcfg; /* 0x14 */
|
||||
unsigned int arm_intmux; /* 0x18 */
|
||||
unsigned int edma_evtmux; /* 0x1C */
|
||||
unsigned int ddr_slew; /* 0x20 */
|
||||
unsigned int clkout; /* 0x24 */
|
||||
unsigned int device_id; /* 0x28 */
|
||||
unsigned int vdac_config; /* 0x2C */
|
||||
unsigned int timer64_ctl; /* 0x30 */
|
||||
unsigned int usbbphy_ctl; /* 0x34 */
|
||||
unsigned int misc; /* 0x38 */
|
||||
unsigned int mstpri[2]; /* 0x3C */
|
||||
unsigned int vpss_clkctl; /* 0x44 */
|
||||
unsigned int peri_clkctl; /* 0x48 */
|
||||
unsigned int deepsleep; /* 0x4C */
|
||||
unsigned int dft_enable; /* 0x50 */
|
||||
unsigned int debounce[8]; /* 0x54 */
|
||||
unsigned int vtpiocr; /* 0x74 */
|
||||
unsigned int pupdctl0; /* 0x78 */
|
||||
unsigned int pupdctl1; /* 0x7C */
|
||||
unsigned int hdimcopbt; /* 0x80 */
|
||||
unsigned int pll0_config; /* 0x84 */
|
||||
unsigned int pll1_config; /* 0x88 */
|
||||
};
|
||||
|
||||
#define VPTIO_RDY (1 << 15)
|
||||
#define VPTIO_IOPWRDN (1 << 14)
|
||||
#define VPTIO_CLRZ (1 << 13)
|
||||
#define VPTIO_LOCK (1 << 7)
|
||||
#define VPTIO_PWRDN (1 << 6)
|
||||
|
||||
#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
|
||||
|
||||
#define dv_sys_module_regs \
|
||||
((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
|
||||
|
||||
#endif /* !CONFIG_SOC_DA8XX */
|
||||
#endif /* _DV_SYSCFG_DEFS_H_ */
|
||||
|
|
@ -68,7 +68,6 @@ err:
|
|||
/*
|
||||
* Set the mii mode as MII or RMII
|
||||
*/
|
||||
#if defined(CONFIG_SOC_DA8XX)
|
||||
void davinci_emac_mii_mode_sel(int mode_sel)
|
||||
{
|
||||
int val;
|
||||
|
|
@ -80,7 +79,7 @@ void davinci_emac_mii_mode_sel(int mode_sel)
|
|||
val |= (1 << 8);
|
||||
writel(val, &davinci_syscfg_regs->cfgchip3);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If there is no MAC address in the environment, then it will be initialized
|
||||
* (silently) from the value in the EEPROM.
|
||||
|
|
@ -106,7 +105,6 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
|
|||
}
|
||||
#endif /* CONFIG_DRIVER_TI_EMAC */
|
||||
|
||||
#if defined(CONFIG_SOC_DA8XX)
|
||||
void irq_init(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -135,4 +133,3 @@ int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,19 +33,8 @@
|
|||
static void lpsc_transition(unsigned int id, unsigned int state)
|
||||
{
|
||||
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
|
||||
#ifdef CONFIG_SOC_DA8XX
|
||||
struct davinci_psc_regs *psc_regs;
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SOC_DA8XX
|
||||
if (id >= DAVINCI_LPSC_GEM)
|
||||
return; /* Don't work on DSP Power Domain */
|
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
|
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
|
||||
ptstat = REG_P(PSC_PTSTAT);
|
||||
ptcmd = REG_P(PSC_PTCMD);
|
||||
#else
|
||||
if (id < DAVINCI_LPSC_PSC1_BASE) {
|
||||
if (id >= PSC_PSC0_MODULE_ID_CNT)
|
||||
return;
|
||||
|
|
@ -62,7 +51,6 @@ static void lpsc_transition(unsigned int id, unsigned int state)
|
|||
}
|
||||
ptstat = &psc_regs->ptstat;
|
||||
ptcmd = &psc_regs->ptcmd;
|
||||
#endif
|
||||
|
||||
while (readl(ptstat) & 0x01)
|
||||
continue;
|
||||
|
|
@ -71,29 +59,6 @@ static void lpsc_transition(unsigned int id, unsigned int state)
|
|||
return; /* Already in that state */
|
||||
|
||||
writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
|
||||
|
||||
switch (id) {
|
||||
#ifdef CONFIG_SOC_DM644X
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */
|
||||
case DAVINCI_LPSC_VPSSSLV:
|
||||
case DAVINCI_LPSC_EMAC:
|
||||
case DAVINCI_LPSC_EMAC_WRAPPER:
|
||||
case DAVINCI_LPSC_MDIO:
|
||||
case DAVINCI_LPSC_USB:
|
||||
case DAVINCI_LPSC_ATA:
|
||||
case DAVINCI_LPSC_VLYNQ:
|
||||
case DAVINCI_LPSC_UHPI:
|
||||
case DAVINCI_LPSC_DDR_EMIF:
|
||||
case DAVINCI_LPSC_AEMIF:
|
||||
case DAVINCI_LPSC_MMC_SD:
|
||||
case DAVINCI_LPSC_MEMSTICK:
|
||||
case DAVINCI_LPSC_McBSP:
|
||||
case DAVINCI_LPSC_GPIO:
|
||||
writel(readl(mdctl) | 0x200, mdctl);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
writel(0x01, ptcmd);
|
||||
|
||||
while (readl(ptstat) & 0x01)
|
||||
|
|
@ -116,44 +81,3 @@ void lpsc_disable(unsigned int id)
|
|||
{
|
||||
lpsc_transition(id, 0x0);
|
||||
}
|
||||
|
||||
/* Not all DaVinci chips have a DSP power domain. */
|
||||
#ifdef CONFIG_SOC_DM644X
|
||||
|
||||
/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
|
||||
#if !defined(CONFIG_SYS_USE_DSPLINK)
|
||||
void dsp_on(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f)
|
||||
return; /* Already on */
|
||||
|
||||
REG(PSC_GBLCTL) |= 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x01;
|
||||
REG(PSC_PDCTL1) &= ~0x100;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
|
||||
REG(PSC_PTCMD) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (REG(PSC_EPCPR) & 0x02)
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x100;
|
||||
REG(PSC_EPCCR) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (!(REG(PSC_PTSTAT) & 0x02))
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f;
|
||||
}
|
||||
#endif /* CONFIG_SYS_USE_DSPLINK */
|
||||
|
||||
#endif /* have a DSP */
|
||||
|
|
|
|||
|
|
@ -33,12 +33,7 @@ void putc(char c)
|
|||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SOC_DM365
|
||||
dm36x_lowlevel_init(0);
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_DA8XX
|
||||
arch_cpu_init();
|
||||
#endif
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user