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https://github.com/brain-hackers/u-boot-brain
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mmc: am654_sdhci: Add Support for PHY
Add support in the driver for handling phy specific registers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Faiz Abbas
Tom Rini
parent
a8185c50d3
commit
ce142ff0c5
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@ -473,6 +473,7 @@ config MMC_SDHCI_AM654
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depends on ARCH_K3
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depends on MMC_SDHCI
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depends on DM_MMC && OF_CONTROL && BLK
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depends on REGMAP
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help
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Support for Secure Digital Host Controller Interface (SDHCI)
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controllers present on TI's AM654 SOCs.
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@ -10,21 +10,189 @@
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#include <dm.h>
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#include <malloc.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <sdhci.h>
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/* CTL_CFG Registers */
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#define CTL_CFG_2 0x14
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#define SLOTTYPE_MASK GENMASK(31, 30)
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#define SLOTTYPE_EMBEDDED BIT(30)
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/* PHY Registers */
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#define PHY_CTRL1 0x100
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#define PHY_CTRL2 0x104
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#define PHY_CTRL3 0x108
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#define PHY_CTRL4 0x10C
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#define PHY_CTRL5 0x110
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#define PHY_CTRL6 0x114
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#define PHY_STAT1 0x130
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#define PHY_STAT2 0x134
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#define IOMUX_ENABLE_SHIFT 31
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#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
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#define OTAPDLYENA_SHIFT 20
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#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
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#define OTAPDLYSEL_SHIFT 12
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#define OTAPDLYSEL_MASK GENMASK(15, 12)
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#define STRBSEL_SHIFT 24
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#define STRBSEL_MASK GENMASK(27, 24)
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#define SEL50_SHIFT 8
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#define SEL50_MASK BIT(SEL50_SHIFT)
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#define SEL100_SHIFT 9
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#define SEL100_MASK BIT(SEL100_SHIFT)
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#define DLL_TRIM_ICP_SHIFT 4
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#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
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#define DR_TY_SHIFT 20
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#define DR_TY_MASK GENMASK(22, 20)
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#define ENDLL_SHIFT 1
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#define ENDLL_MASK BIT(ENDLL_SHIFT)
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#define DLLRDY_SHIFT 0
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#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
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#define PDB_SHIFT 0
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#define PDB_MASK BIT(PDB_SHIFT)
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#define CALDONE_SHIFT 1
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#define CALDONE_MASK BIT(CALDONE_SHIFT)
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#define RETRIM_SHIFT 17
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#define RETRIM_MASK BIT(RETRIM_SHIFT)
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#define DRIVER_STRENGTH_50_OHM 0x0
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#define DRIVER_STRENGTH_33_OHM 0x1
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#define DRIVER_STRENGTH_66_OHM 0x2
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#define DRIVER_STRENGTH_100_OHM 0x3
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#define DRIVER_STRENGTH_40_OHM 0x4
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#define AM654_SDHCI_MIN_FREQ 400000
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struct am654_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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unsigned int f_max;
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struct regmap *base;
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bool non_removable;
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u32 otap_del_sel;
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u32 trm_icp;
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u32 drv_strength;
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bool dll_on;
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};
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static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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unsigned int speed = host->mmc->clock;
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int sel50, sel100;
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u32 mask, val;
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int ret;
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/* Reset SD Clock Enable */
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val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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val &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
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/* power off phy */
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if (plat->dll_on) {
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
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plat->dll_on = false;
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}
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/* restart clock */
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sdhci_set_clock(host->mmc, speed);
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/* switch phy back on */
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if (speed > AM654_SDHCI_MIN_FREQ) {
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(plat->otap_del_sel << OTAPDLYSEL_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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switch (speed) {
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case 200000000:
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sel50 = 0;
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sel100 = 0;
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break;
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case 100000000:
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sel50 = 0;
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sel100 = 1;
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break;
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default:
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sel50 = 1;
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sel100 = 0;
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}
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/* Configure PHY DLL frequency */
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mask = SEL50_MASK | SEL100_MASK;
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val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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/* Enable DLL */
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
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0x1 << ENDLL_SHIFT);
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/*
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* Poll for DLL ready. Use a one second timeout.
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* Works in all experiments done so far
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*/
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
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val & DLLRDY_MASK, 1000, 1000000);
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if (ret)
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return ret;
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plat->dll_on = true;
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}
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return 0;
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}
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const struct sdhci_ops am654_sdhci_ops = {
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.set_ios_post = &am654_sdhci_set_ios_post,
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};
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int am654_sdhci_init(struct am654_sdhci_plat *plat)
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{
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u32 ctl_cfg_2 = 0;
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u32 mask, val;
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int ret;
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/* Reset OTAP to default value */
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
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regmap_read(plat->base, PHY_STAT1, &val);
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if (~val & CALDONE_MASK) {
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/* Calibrate IO lines */
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regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, PDB_MASK);
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
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val & CALDONE_MASK, 1, 20);
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if (ret)
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return ret;
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}
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/* Configure DLL TRIM */
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mask = DLL_TRIM_ICP_MASK;
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val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
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/* Configure DLL driver strength */
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mask |= DR_TY_MASK;
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val |= plat->drv_strength << DR_TY_SHIFT;
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regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
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/* Enable pins by setting IO mux to 0 */
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regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
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/* Set slot type based on SD or eMMC */
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if (plat->non_removable)
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ctl_cfg_2 = SLOTTYPE_EMBEDDED;
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regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
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return 0;
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}
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static int am654_sdhci_probe(struct udevice *dev)
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{
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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struct power_domain sdhci_pwrdmn;
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struct clk clk;
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unsigned long clock;
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@ -55,16 +223,20 @@ static int am654_sdhci_probe(struct udevice *dev)
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}
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host->max_clk = clock;
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ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
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AM654_SDHCI_MIN_FREQ);
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
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AM654_SDHCI_MIN_FREQ);
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if (ret)
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return ret;
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host->ops = &am654_sdhci_ops;
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host->mmc->priv = host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
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am654_sdhci_init(plat);
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return sdhci_probe(dev);
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}
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@ -72,11 +244,50 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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u32 drv_strength;
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int ret;
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host->name = dev->name;
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host->ioaddr = (void *)dev_read_addr(dev);
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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plat->f_max = dev_read_u32_default(dev, "max-frequency", 0);
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plat->non_removable = dev_read_bool(dev, "non-removable");
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ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
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if (ret)
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return ret;
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ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
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if (ret)
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return ret;
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ret = dev_read_u32(dev, "ti,driver-strength-ohm", &drv_strength);
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if (ret)
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return ret;
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switch (drv_strength) {
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case 50:
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plat->drv_strength = DRIVER_STRENGTH_50_OHM;
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break;
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case 33:
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plat->drv_strength = DRIVER_STRENGTH_33_OHM;
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break;
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case 66:
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plat->drv_strength = DRIVER_STRENGTH_66_OHM;
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break;
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case 100:
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plat->drv_strength = DRIVER_STRENGTH_100_OHM;
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break;
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case 40:
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plat->drv_strength = DRIVER_STRENGTH_40_OHM;
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break;
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default:
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dev_err(dev, "Invalid driver strength\n");
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return -EINVAL;
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}
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ret = mmc_of_parse(dev, cfg);
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if (ret)
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return ret;
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return 0;
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}
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