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https://github.com/brain-hackers/u-boot-brain
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Patch by Curt Brune, 07 Jul 2004:
relocate exception vectors on arm720t if needed
This commit is contained in:
wdenk
parent
a1f4a3dd05
commit
cdc7fea173
@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Curt Brune, 07 Jul 2004:
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relocate exception vectors on arm720t if needed
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* Patch by George G. Davis, 06 Jul 2004:
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- update mach-types.h to latest arm.linux.org.uk master list
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- Set correct OMAP1610 bi_arch_number for build target
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@ -14,7 +14,7 @@
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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@ -38,7 +38,7 @@
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.globl _start
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_start: b reset
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_start: b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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@ -47,7 +47,7 @@ _start: b reset
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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@ -126,13 +126,23 @@ reset:
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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#if TEXT_BASE
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ldr r2, =0x0 /* Relocate the exception vectors */
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cmp r1, r2 /* and associated data to address */
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ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
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stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
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ldmneia r0, {r3-r9}
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stmneia r2, {r3-r9}
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adrne r0, _start /* restore r0 */
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#endif
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ldr r2, _armboot_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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@ -143,26 +153,26 @@ copy_loop:
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/* Set up the stack */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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#ifdef CONFIG_USE_IRQ
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
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#endif
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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ldr pc, _start_armboot
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_start_armboot: .word start_armboot
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_start_armboot: .word start_armboot
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/*
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*************************************************************************
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@ -234,7 +244,7 @@ cpu_init_crit:
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str r1, [r0, #+NETARM_GEN_PORTC]
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/*
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* software reset : see HW Ref. Guide 8.2.4 : Software Service register
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* for an explanation of this process
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* for an explanation of this process
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*/
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ldr r0, =NETARM_GEN_MODULE_BASE
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ldr r1, =NETARM_GEN_SW_SVC_RESETA
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@ -285,7 +295,7 @@ cpu_init_crit:
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* Disable Cache
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*/
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ldr r0, =REG_SYSCFG
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ldr r1, =0x83ffffa0 /* cache-disabled */
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ldr r1, =0x83ffffa0 /* cache-disabled */
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str r1, [r0]
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#else
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@ -359,29 +369,29 @@ cpu_init_crit:
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC
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add r8, sp, #S_PC
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ldr r2, _armboot_start
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sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
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sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
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ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
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sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
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ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
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stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
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mov r0, sp
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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@ -400,7 +410,7 @@ cpu_init_crit:
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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msr spsr_c, r13
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@ -419,35 +429,35 @@ cpu_init_crit:
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/*
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* exception handlers
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*/
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.align 5
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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@ -455,7 +465,7 @@ not_used:
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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bl do_irq
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irq_restore_user_regs
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.align 5
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@ -463,7 +473,7 @@ fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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bl do_fiq
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irq_restore_user_regs
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#else
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@ -472,13 +482,13 @@ fiq:
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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bl do_fiq
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#endif
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@ -486,14 +496,14 @@ fiq:
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.align 5
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.globl reset_cpu
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reset_cpu:
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x2100 @ ..v....s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x2100 @ ..v....s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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#elif defined(CONFIG_NETARM)
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.align 5
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.globl reset_cpu
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