mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
Merge with /home/stefan/git/u-boot/yucca-ddr2
This commit is contained in:
commit
cd84528f20
@ -46,6 +46,11 @@
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|||||||
.globl tlbtabA
|
.globl tlbtabA
|
||||||
tlbtabA:
|
tlbtabA:
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||||||
tlbtab_start
|
tlbtab_start
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
|
*/
|
||||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||||
|
|
||||||
/*
|
/*
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@ -81,6 +86,11 @@ tlbtabA:
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|||||||
.globl tlbtabB
|
.globl tlbtabB
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||||||
tlbtabB:
|
tlbtabB:
|
||||||
tlbtab_start
|
tlbtab_start
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||||||
|
|
||||||
|
/*
|
||||||
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
|
*/
|
||||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1,73 +1,31 @@
|
|||||||
/*
|
/*
|
||||||
*
|
* (C) Copyright 2007
|
||||||
* See file CREDITS for list of people who contributed to this
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
* project.
|
*
|
||||||
*
|
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||||
* This program is free software; you can redistribute it and/or
|
*
|
||||||
* modify it under the terms of the GNU General Public License as
|
* See file CREDITS for list of people who contributed to this
|
||||||
* published by the Free Software Foundation; either version 2 of
|
* project.
|
||||||
* the License, or (at your option) any later version.
|
*
|
||||||
*
|
* This program is free software; you can redistribute it and/or
|
||||||
* This program is distributed in the hope that it will be useful,
|
* modify it under the terms of the GNU General Public License as
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* published by the Free Software Foundation; either version 2 of
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* the License, or (at your option) any later version.
|
||||||
* GNU General Public License for more details.
|
*
|
||||||
*
|
* This program is distributed in the hope that it will be useful,
|
||||||
* You should have received a copy of the GNU General Public License
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
* along with this program; if not, write to the Free Software
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
* GNU General Public License for more details.
|
||||||
* MA 02111-1307 USA
|
*
|
||||||
*/
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
#include <asm-ppc/mmu.h>
|
||||||
/* General */
|
|
||||||
#define TLB_VALID 0x00000200
|
|
||||||
|
|
||||||
/* Supported page sizes */
|
|
||||||
|
|
||||||
#define SZ_1K 0x00000000
|
|
||||||
#define SZ_4K 0x00000010
|
|
||||||
#define SZ_16K 0x00000020
|
|
||||||
#define SZ_64K 0x00000030
|
|
||||||
#define SZ_256K 0x00000040
|
|
||||||
#define SZ_1M 0x00000050
|
|
||||||
#define SZ_16M 0x00000070
|
|
||||||
#define SZ_256M 0x00000090
|
|
||||||
|
|
||||||
/* Storage attributes */
|
|
||||||
#define SA_W 0x00000800 /* Write-through */
|
|
||||||
#define SA_I 0x00000400 /* Caching inhibited */
|
|
||||||
#define SA_M 0x00000200 /* Memory coherence */
|
|
||||||
#define SA_G 0x00000100 /* Guarded */
|
|
||||||
#define SA_E 0x00000080 /* Endian */
|
|
||||||
|
|
||||||
/* Access control */
|
|
||||||
#define AC_X 0x00000024 /* Execute */
|
|
||||||
#define AC_W 0x00000012 /* Write */
|
|
||||||
#define AC_R 0x00000009 /* Read */
|
|
||||||
|
|
||||||
/* Some handy macros */
|
|
||||||
|
|
||||||
#define EPN(e) ((e) & 0xfffffc00)
|
|
||||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
|
||||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
|
||||||
#define TLB2(a) ( (a)&0x00000fbf )
|
|
||||||
|
|
||||||
#define tlbtab_start\
|
|
||||||
mflr r1 ;\
|
|
||||||
bl 0f ;
|
|
||||||
|
|
||||||
#define tlbtab_end\
|
|
||||||
.long 0, 0, 0 ; \
|
|
||||||
0: mflr r0 ; \
|
|
||||||
mtlr r1 ; \
|
|
||||||
blr ;
|
|
||||||
|
|
||||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
|
||||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
|
||||||
|
|
||||||
|
|
||||||
/**************************************************************************
|
/**************************************************************************
|
||||||
* TLB TABLE
|
* TLB TABLE
|
||||||
@ -80,53 +38,37 @@
|
|||||||
*
|
*
|
||||||
*************************************************************************/
|
*************************************************************************/
|
||||||
|
|
||||||
.section .bootpg,"ax"
|
.section .bootpg,"ax"
|
||||||
.globl tlbtab
|
.globl tlbtab
|
||||||
|
|
||||||
tlbtab:
|
tlbtab:
|
||||||
tlbtab_start
|
tlbtab_start
|
||||||
|
|
||||||
#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
|
/*
|
||||||
/* large flash */
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
|
*/
|
||||||
tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
|
tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
|
||||||
tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
|
|
||||||
|
|
||||||
tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
|
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
#else /* else booting from small flash */
|
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||||
|
|
||||||
tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
/*
|
||||||
tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
* TLB entries for SDRAM are not needed on this platform.
|
||||||
tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
* They are dynamically generated in the SPD DDR(2) detection
|
||||||
tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
* routine.
|
||||||
#endif
|
*/
|
||||||
|
|
||||||
tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
|
/* internal ram (l2 cache) */
|
||||||
|
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
|
||||||
|
|
||||||
#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
|
/* peripherals at f0000000 */
|
||||||
tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
|
||||||
tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
|
||||||
#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
|
|
||||||
tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
|
||||||
#elif (CFG_SMALL_FLASH == 0xfff00000)
|
|
||||||
tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
|
|
||||||
#else
|
|
||||||
#error DONT KNOW SRAM LOCATION
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* internal ram (l2 cache) */
|
/* PCI */
|
||||||
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
|
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
|
||||||
|
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
|
||||||
/* peripherals at f0000000 */
|
tlbtab_end
|
||||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
|
|
||||||
/* PCI */
|
|
||||||
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
|
|
||||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
|
|
||||||
#endif
|
|
||||||
tlbtab_end
|
|
||||||
|
@ -105,105 +105,6 @@ int checkboard(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/*************************************************************************
|
|
||||||
* long int fixed_sdram()
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
static long int fixed_sdram(void)
|
|
||||||
{ /* DDR2 init from BDI2000 script */
|
|
||||||
mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
|
|
||||||
mtdcr( 0x11, 0x84000000 );
|
|
||||||
mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
|
|
||||||
mtdcr( 0x11, 0x2D122000 );
|
|
||||||
mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
|
|
||||||
mtdcr( 0x11, 0x00800026 );
|
|
||||||
mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
|
|
||||||
mtdcr( 0x11, 0x82000800 );
|
|
||||||
mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
|
|
||||||
mtdcr( 0x11, 0x80000000 );
|
|
||||||
mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
|
|
||||||
mtdcr( 0x11, 0x08200000 );
|
|
||||||
mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
|
|
||||||
mtdcr( 0x11, 0x80201000 );
|
|
||||||
mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
|
|
||||||
mtdcr( 0x11, 0x42103242 );
|
|
||||||
mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
|
|
||||||
mtdcr( 0x11, 0x0C100D14 );
|
|
||||||
mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
|
|
||||||
mtdcr( 0x11, 0x00000642 );
|
|
||||||
mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
|
|
||||||
mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
|
|
||||||
|
|
||||||
mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
|
|
||||||
mtdcr( 0x11, 0x81b80000 );
|
|
||||||
mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
|
|
||||||
mtdcr( 0x11, 0x82100400 );
|
|
||||||
mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
|
|
||||||
mtdcr( 0x11, 0x80820000 );
|
|
||||||
mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
|
|
||||||
mtdcr( 0x11, 0x80830000 );
|
|
||||||
mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
|
|
||||||
mtdcr( 0x11, 0x80810000 );
|
|
||||||
mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
|
|
||||||
mtdcr( 0x11, 0x80800542 );
|
|
||||||
mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
|
|
||||||
mtdcr( 0x11, 0x82100400 );
|
|
||||||
mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
|
|
||||||
mtdcr( 0x11, 0x99080000 );
|
|
||||||
mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
|
|
||||||
mtdcr( 0x11, 0x99080000 );
|
|
||||||
mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
|
|
||||||
mtdcr( 0x11, 0x99080000 );
|
|
||||||
mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
|
|
||||||
mtdcr( 0x11, 0x99080000 );
|
|
||||||
mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
|
|
||||||
mtdcr( 0x11, 0x80800442 );
|
|
||||||
mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
|
|
||||||
mtdcr( 0x11, 0x80810380 );
|
|
||||||
mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
|
|
||||||
mtdcr( 0x11, 0x80810000 );
|
|
||||||
udelay( 10*1000 );
|
|
||||||
|
|
||||||
mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
|
|
||||||
mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
|
|
||||||
udelay( 100*1000 );
|
|
||||||
|
|
||||||
mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
|
|
||||||
mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
|
|
||||||
|
|
||||||
mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
|
|
||||||
mtdcr( 0x11, 0x00000000 );
|
|
||||||
mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
|
|
||||||
mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
|
|
||||||
mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
|
|
||||||
mtdcr( 0x11, 0x00000200 );
|
|
||||||
|
|
||||||
return 512 << 20;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*************************************************************************
|
|
||||||
* long int initdram
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
long int initdram( int board_type )
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
dram_size = spd_sdram (0);
|
|
||||||
#else
|
|
||||||
dram_size = fixed_sdram ();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return dram_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*************************************************************************
|
/*************************************************************************
|
||||||
* int testdram()
|
* int testdram()
|
||||||
*
|
*
|
||||||
|
@ -68,19 +68,6 @@ SECTIONS
|
|||||||
|
|
||||||
cpu/ppc4xx/start.o (.text)
|
cpu/ppc4xx/start.o (.text)
|
||||||
board/amcc/luan/init.o (.text)
|
board/amcc/luan/init.o (.text)
|
||||||
cpu/ppc4xx/kgdb.o (.text)
|
|
||||||
cpu/ppc4xx/traps.o (.text)
|
|
||||||
cpu/ppc4xx/interrupts.o (.text)
|
|
||||||
cpu/ppc4xx/serial.o (.text)
|
|
||||||
cpu/ppc4xx/cpu_init.o (.text)
|
|
||||||
cpu/ppc4xx/speed.o (.text)
|
|
||||||
common/dlmalloc.o (.text)
|
|
||||||
lib_generic/crc32.o (.text)
|
|
||||||
lib_ppc/extable.o (.text)
|
|
||||||
lib_generic/zlib.o (.text)
|
|
||||||
|
|
||||||
/* . = env_offset;*/
|
|
||||||
/* common/environment.o(.text)*/
|
|
||||||
|
|
||||||
*(.text)
|
*(.text)
|
||||||
*(.fixup)
|
*(.fixup)
|
||||||
|
@ -1,4 +1,7 @@
|
|||||||
/*
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
@ -19,56 +22,10 @@
|
|||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
#include <asm-ppc/mmu.h>
|
||||||
/* General */
|
|
||||||
#define TLB_VALID 0x00000200
|
|
||||||
|
|
||||||
/* Supported page sizes */
|
|
||||||
|
|
||||||
#define SZ_1K 0x00000000
|
|
||||||
#define SZ_4K 0x00000010
|
|
||||||
#define SZ_16K 0x00000020
|
|
||||||
#define SZ_64K 0x00000030
|
|
||||||
#define SZ_256K 0x00000040
|
|
||||||
#define SZ_1M 0x00000050
|
|
||||||
#define SZ_16M 0x00000070
|
|
||||||
#define SZ_256M 0x00000090
|
|
||||||
|
|
||||||
/* Storage attributes */
|
|
||||||
#define SA_W 0x00000800 /* Write-through */
|
|
||||||
#define SA_I 0x00000400 /* Caching inhibited */
|
|
||||||
#define SA_M 0x00000200 /* Memory coherence */
|
|
||||||
#define SA_G 0x00000100 /* Guarded */
|
|
||||||
#define SA_E 0x00000080 /* Endian */
|
|
||||||
|
|
||||||
/* Access control */
|
|
||||||
#define AC_X 0x00000024 /* Execute */
|
|
||||||
#define AC_W 0x00000012 /* Write */
|
|
||||||
#define AC_R 0x00000009 /* Read */
|
|
||||||
|
|
||||||
/* Some handy macros */
|
|
||||||
|
|
||||||
#define EPN(e) ((e) & 0xfffffc00)
|
|
||||||
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
|
|
||||||
#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
|
|
||||||
#define TLB2(a) ((a) & 0x00000fbf)
|
|
||||||
|
|
||||||
#define tlbtab_start\
|
|
||||||
mflr r1 ;\
|
|
||||||
bl 0f ;
|
|
||||||
|
|
||||||
#define tlbtab_end\
|
|
||||||
.long 0, 0, 0 ;\
|
|
||||||
0: mflr r0 ;\
|
|
||||||
mtlr r1 ;\
|
|
||||||
blr ;
|
|
||||||
|
|
||||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
|
||||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
|
||||||
|
|
||||||
/**************************************************************************
|
/**************************************************************************
|
||||||
* TLB TABLE
|
* TLB TABLE
|
||||||
@ -89,12 +46,18 @@
|
|||||||
.globl tlbtabA
|
.globl tlbtabA
|
||||||
tlbtabA:
|
tlbtabA:
|
||||||
tlbtab_start
|
tlbtab_start
|
||||||
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
|
|
||||||
|
|
||||||
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
/*
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
*/
|
||||||
|
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TLB entries for SDRAM are not needed on this platform.
|
||||||
|
* They are dynamically generated in the SPD DDR(2) detection
|
||||||
|
* routine.
|
||||||
|
*/
|
||||||
|
|
||||||
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||||
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
||||||
@ -126,12 +89,18 @@ tlbtabA:
|
|||||||
.globl tlbtabB
|
.globl tlbtabB
|
||||||
tlbtabB:
|
tlbtabB:
|
||||||
tlbtab_start
|
tlbtab_start
|
||||||
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
|
|
||||||
|
|
||||||
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
/*
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
*/
|
||||||
|
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TLB entries for SDRAM are not needed on this platform.
|
||||||
|
* They are dynamically generated in the SPD DDR(2) detection
|
||||||
|
* routine.
|
||||||
|
*/
|
||||||
|
|
||||||
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||||
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
||||||
|
@ -44,8 +44,6 @@ int compare_to_true(char *str );
|
|||||||
char *remove_l_w_space(char *in_str );
|
char *remove_l_w_space(char *in_str );
|
||||||
char *remove_t_w_space(char *in_str );
|
char *remove_t_w_space(char *in_str );
|
||||||
int get_console_port(void);
|
int get_console_port(void);
|
||||||
unsigned long ppcMfcpr(unsigned long cpr_reg);
|
|
||||||
unsigned long ppcMfsdr(unsigned long sdr_reg);
|
|
||||||
|
|
||||||
int ppc440spe_init_pcie_rootport(int port);
|
int ppc440spe_init_pcie_rootport(int port);
|
||||||
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
|
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
|
||||||
@ -221,7 +219,7 @@ int board_early_init_f (void)
|
|||||||
|
|
|
|
||||||
+-------------------------------------------------------------------*/
|
+-------------------------------------------------------------------*/
|
||||||
/* Read Pin Strap Register in PPC440SP */
|
/* Read Pin Strap Register in PPC440SP */
|
||||||
sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
|
mfsdr(SDR0_PINSTP, sdr0_pinstp);
|
||||||
bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
|
bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
|
||||||
|
|
||||||
switch (bootstrap_settings) {
|
switch (bootstrap_settings) {
|
||||||
@ -246,7 +244,7 @@ int board_early_init_f (void)
|
|||||||
* Boot Settings in IIC EEprom address 0x50 or 0x54
|
* Boot Settings in IIC EEprom address 0x50 or 0x54
|
||||||
* Read Serial Device Strap Register1 in PPC440SPe
|
* Read Serial Device Strap Register1 in PPC440SPe
|
||||||
*/
|
*/
|
||||||
sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
|
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
|
||||||
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
|
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
|
||||||
ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
|
ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
|
||||||
|
|
||||||
@ -564,277 +562,6 @@ int checkboard (void)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static long int yucca_probe_for_dimms(void)
|
|
||||||
{
|
|
||||||
int dimm_installed[MAXDIMMS];
|
|
||||||
int dimm_num, result;
|
|
||||||
int dimms_found = 0;
|
|
||||||
uchar dimm_addr = IIC0_DIMM0_ADDR;
|
|
||||||
uchar dimm_spd_data[MAX_SPD_BYTES];
|
|
||||||
|
|
||||||
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
|
|
||||||
/* check if there is a chip at the dimm address */
|
|
||||||
switch (dimm_num) {
|
|
||||||
case 0:
|
|
||||||
dimm_addr = IIC0_DIMM0_ADDR;
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
dimm_addr = IIC0_DIMM1_ADDR;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
result = i2c_probe(dimm_addr);
|
|
||||||
|
|
||||||
memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
|
|
||||||
if (result == 0) {
|
|
||||||
/* read first byte of SPD data, if there is any data */
|
|
||||||
result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
|
|
||||||
|
|
||||||
if (result == 0) {
|
|
||||||
result = dimm_spd_data[0];
|
|
||||||
result = result > MAX_SPD_BYTES ?
|
|
||||||
MAX_SPD_BYTES : result;
|
|
||||||
result = i2c_read(dimm_addr, 0, 1,
|
|
||||||
dimm_spd_data, result);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((result == 0) &&
|
|
||||||
(dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
|
|
||||||
dimm_installed[dimm_num] = TRUE;
|
|
||||||
dimms_found++;
|
|
||||||
debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
|
|
||||||
} else {
|
|
||||||
dimm_installed[dimm_num] = FALSE;
|
|
||||||
debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (dimms_found == 0) {
|
|
||||||
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
|
|
||||||
hang();
|
|
||||||
}
|
|
||||||
|
|
||||||
if (dimm_installed[0] != TRUE) {
|
|
||||||
printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
|
|
||||||
printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
|
|
||||||
hang();
|
|
||||||
}
|
|
||||||
|
|
||||||
return dimms_found;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*************************************************************************
|
|
||||||
* init SDRAM controller with fixed value
|
|
||||||
* the initialization values are for 2x MICRON DDR2
|
|
||||||
* PN: MT18HTF6472DY-53EB2
|
|
||||||
* 512MB, DDR2, 533, CL4, ECC, REG
|
|
||||||
************************************************************************/
|
|
||||||
static long int fixed_sdram(void)
|
|
||||||
{
|
|
||||||
long int yucca_dimms = 0;
|
|
||||||
|
|
||||||
yucca_dimms = yucca_probe_for_dimms();
|
|
||||||
|
|
||||||
/* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */
|
|
||||||
mtdcr( 0x10, 0x00000021 );
|
|
||||||
mtdcr( 0x11, 0x84000000 );
|
|
||||||
|
|
||||||
/* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */
|
|
||||||
mtdcr( 0x10, 0x00000020 );
|
|
||||||
mtdcr( 0x11, 0x2D122000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_CODT Die Termination On */
|
|
||||||
mtdcr( 0x10, 0x00000026 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x2A800021 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x02800021 );
|
|
||||||
|
|
||||||
/* On-Die Termination for Bank 0 */
|
|
||||||
mtdcr( 0x10, 0x00000022 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x18000000 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x06000000 );
|
|
||||||
|
|
||||||
/* On-Die Termination for Bank 1 */
|
|
||||||
mtdcr( 0x10, 0x00000023 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x18000000 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x01800000 );
|
|
||||||
|
|
||||||
/* On-Die Termination for Bank 2 */
|
|
||||||
mtdcr( 0x10, 0x00000024 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x01800000 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x00000000 );
|
|
||||||
|
|
||||||
/* On-Die Termination for Bank 3 */
|
|
||||||
mtdcr( 0x10, 0x00000025 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x01800000 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x00000000 );
|
|
||||||
|
|
||||||
/* Refresh Time register (0x30) Refresh every 7.8125uS */
|
|
||||||
mtdcr( 0x10, 0x00000030 );
|
|
||||||
mtdcr( 0x11, 0x08200000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_MMODE CL 4 */
|
|
||||||
mtdcr( 0x10, 0x00000088 );
|
|
||||||
mtdcr( 0x11, 0x00000642 );
|
|
||||||
|
|
||||||
/* MCIF0_MEMODE */
|
|
||||||
mtdcr( 0x10, 0x00000089 );
|
|
||||||
mtdcr( 0x11, 0x00000004 );
|
|
||||||
|
|
||||||
/*SET MCIF0_MB0CF */
|
|
||||||
mtdcr( 0x10, 0x00000040 );
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
|
|
||||||
/* SET MCIF0_MB1CF */
|
|
||||||
mtdcr( 0x10, 0x00000044 );
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
|
|
||||||
/* SET MCIF0_MB2CF */
|
|
||||||
mtdcr( 0x10, 0x00000048 );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x00000000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_MB3CF */
|
|
||||||
mtdcr( 0x10, 0x0000004c );
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x11, 0x00000201 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x11, 0x00000000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR0 # NOP */
|
|
||||||
mtdcr( 0x10, 0x00000050 );
|
|
||||||
mtdcr( 0x11, 0xB5380000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR1 # PRE */
|
|
||||||
mtdcr( 0x10, 0x00000051 );
|
|
||||||
mtdcr( 0x11, 0x82100400 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR2 # EMR2 */
|
|
||||||
mtdcr( 0x10, 0x00000052 );
|
|
||||||
mtdcr( 0x11, 0x80820000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR3 # EMR3 */
|
|
||||||
mtdcr( 0x10, 0x00000053 );
|
|
||||||
mtdcr( 0x11, 0x80830000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR4 # EMR DLL ENABLE */
|
|
||||||
mtdcr( 0x10, 0x00000054 );
|
|
||||||
mtdcr( 0x11, 0x80810000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR5 # MR DLL RESET */
|
|
||||||
mtdcr( 0x10, 0x00000055 );
|
|
||||||
mtdcr( 0x11, 0x80800542 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR6 # PRE */
|
|
||||||
mtdcr( 0x10, 0x00000056 );
|
|
||||||
mtdcr( 0x11, 0x82100400 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR7 # Refresh */
|
|
||||||
mtdcr( 0x10, 0x00000057 );
|
|
||||||
mtdcr( 0x11, 0x8A080000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR8 # Refresh */
|
|
||||||
mtdcr( 0x10, 0x00000058 );
|
|
||||||
mtdcr( 0x11, 0x8A080000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR9 # Refresh */
|
|
||||||
mtdcr( 0x10, 0x00000059 );
|
|
||||||
mtdcr( 0x11, 0x8A080000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR10 # Refresh */
|
|
||||||
mtdcr( 0x10, 0x0000005A );
|
|
||||||
mtdcr( 0x11, 0x8A080000 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR11 # MR */
|
|
||||||
mtdcr( 0x10, 0x0000005B );
|
|
||||||
mtdcr( 0x11, 0x80800442 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR12 # EMR OCD Default*/
|
|
||||||
mtdcr( 0x10, 0x0000005C );
|
|
||||||
mtdcr( 0x11, 0x80810380 );
|
|
||||||
|
|
||||||
/* SET MCIF0_INITPLR13 # EMR OCD Exit */
|
|
||||||
mtdcr( 0x10, 0x0000005D );
|
|
||||||
mtdcr( 0x11, 0x80810000 );
|
|
||||||
|
|
||||||
/* 0x80: Adv Addr clock by 180 deg */
|
|
||||||
mtdcr( 0x10, 0x00000080 );
|
|
||||||
mtdcr( 0x11, 0x80000000 );
|
|
||||||
|
|
||||||
/* 0x21: Exit self refresh, set DC_EN */
|
|
||||||
mtdcr( 0x10, 0x00000021 );
|
|
||||||
mtdcr( 0x11, 0x28000000 );
|
|
||||||
|
|
||||||
/* 0x81: Write DQS Adv 90 + Fractional DQS Delay */
|
|
||||||
mtdcr( 0x10, 0x00000081 );
|
|
||||||
mtdcr( 0x11, 0x80000800 );
|
|
||||||
|
|
||||||
/* MCIF0_SDTR1 */
|
|
||||||
mtdcr( 0x10, 0x00000085 );
|
|
||||||
mtdcr( 0x11, 0x80201000 );
|
|
||||||
|
|
||||||
/* MCIF0_SDTR2 */
|
|
||||||
mtdcr( 0x10, 0x00000086 );
|
|
||||||
mtdcr( 0x11, 0x42103242 );
|
|
||||||
|
|
||||||
/* MCIF0_SDTR3 */
|
|
||||||
mtdcr( 0x10, 0x00000087 );
|
|
||||||
mtdcr( 0x11, 0x0C100D14 );
|
|
||||||
|
|
||||||
/* SET MQ0_B0BAS base addr 00000000 / 256MB */
|
|
||||||
mtdcr( 0x40, 0x0000F800 );
|
|
||||||
|
|
||||||
/* SET MQ0_B1BAS base addr 10000000 / 256MB */
|
|
||||||
mtdcr( 0x41, 0x0400F800 );
|
|
||||||
|
|
||||||
/* SET MQ0_B2BAS base addr 20000000 / 256MB */
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x42, 0x0800F800 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x42, 0x00000000 );
|
|
||||||
|
|
||||||
/* SET MQ0_B3BAS base addr 30000000 / 256MB */
|
|
||||||
if (yucca_dimms == 2)
|
|
||||||
mtdcr( 0x43, 0x0C00F800 );
|
|
||||||
else if (yucca_dimms == 1)
|
|
||||||
mtdcr( 0x43, 0x00000000 );
|
|
||||||
|
|
||||||
/* SDRAM_RQDC */
|
|
||||||
mtdcr( 0x10, 0x00000070 );
|
|
||||||
mtdcr( 0x11, 0x8000003F );
|
|
||||||
|
|
||||||
/* SDRAM_RDCC */
|
|
||||||
mtdcr( 0x10, 0x00000078 );
|
|
||||||
mtdcr( 0x11, 0x80000000 );
|
|
||||||
|
|
||||||
/* SDRAM_RFDC */
|
|
||||||
mtdcr( 0x10, 0x00000074 );
|
|
||||||
mtdcr( 0x11, 0x00000220 );
|
|
||||||
|
|
||||||
return (yucca_dimms * 512) << 20;
|
|
||||||
}
|
|
||||||
|
|
||||||
long int initdram (int board_type)
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
dram_size = fixed_sdram();
|
|
||||||
|
|
||||||
return dram_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CFG_DRAM_TEST)
|
#if defined(CFG_DRAM_TEST)
|
||||||
int testdram (void)
|
int testdram (void)
|
||||||
{
|
{
|
||||||
@ -1267,42 +994,3 @@ int onboard_pci_arbiter_selected(int core_pci)
|
|||||||
#endif
|
#endif
|
||||||
return (BOARD_OPTION_NOT_SELECTED);
|
return (BOARD_OPTION_NOT_SELECTED);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------+
|
|
||||||
| ppcMfcpr.
|
|
||||||
+---------------------------------------------------------------------------*/
|
|
||||||
unsigned long ppcMfcpr(unsigned long cpr_reg)
|
|
||||||
{
|
|
||||||
unsigned long msr;
|
|
||||||
unsigned long cpr_cfgaddr_temp;
|
|
||||||
unsigned long cpr_value;
|
|
||||||
|
|
||||||
msr = (mfmsr () & ~(MSR_EE));
|
|
||||||
cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR);
|
|
||||||
mtdcr(CPR0_CFGADDR, cpr_reg);
|
|
||||||
cpr_value = mfdcr(CPR0_CFGDATA);
|
|
||||||
mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
|
|
||||||
mtmsr(msr);
|
|
||||||
|
|
||||||
return (cpr_value);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------+
|
|
||||||
| Indirect Access of the System DCR's (SDR)
|
|
||||||
| ppcMfsdr
|
|
||||||
+----------------------------------------------------------------------------*/
|
|
||||||
unsigned long ppcMfsdr(unsigned long sdr_reg)
|
|
||||||
{
|
|
||||||
unsigned long msr;
|
|
||||||
unsigned long sdr_cfgaddr_temp;
|
|
||||||
unsigned long sdr_value;
|
|
||||||
|
|
||||||
msr = (mfmsr () & ~(MSR_EE));
|
|
||||||
sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR);
|
|
||||||
mtdcr(SDR0_CFGADDR, sdr_reg);
|
|
||||||
sdr_value = mfdcr(SDR0_CFGDATA);
|
|
||||||
mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
|
|
||||||
mtmsr(msr);
|
|
||||||
|
|
||||||
return (sdr_value);
|
|
||||||
}
|
|
||||||
|
@ -188,6 +188,7 @@ static void program_initplr(unsigned long *dimm_populated,
|
|||||||
ddr_cas_id_t selected_cas,
|
ddr_cas_id_t selected_cas,
|
||||||
int write_recovery);
|
int write_recovery);
|
||||||
static unsigned long is_ecc_enabled(void);
|
static unsigned long is_ecc_enabled(void);
|
||||||
|
#ifdef CONFIG_DDR_ECC
|
||||||
static void program_ecc(unsigned long *dimm_populated,
|
static void program_ecc(unsigned long *dimm_populated,
|
||||||
unsigned char *iic0_dimm_addr,
|
unsigned char *iic0_dimm_addr,
|
||||||
unsigned long num_dimm_banks,
|
unsigned long num_dimm_banks,
|
||||||
@ -195,6 +196,7 @@ static void program_ecc(unsigned long *dimm_populated,
|
|||||||
static void program_ecc_addr(unsigned long start_address,
|
static void program_ecc_addr(unsigned long start_address,
|
||||||
unsigned long num_bytes,
|
unsigned long num_bytes,
|
||||||
unsigned long tlb_word2_i_value);
|
unsigned long tlb_word2_i_value);
|
||||||
|
#endif
|
||||||
static void program_DQS_calibration(unsigned long *dimm_populated,
|
static void program_DQS_calibration(unsigned long *dimm_populated,
|
||||||
unsigned char *iic0_dimm_addr,
|
unsigned char *iic0_dimm_addr,
|
||||||
unsigned long num_dimm_banks);
|
unsigned long num_dimm_banks);
|
||||||
@ -255,15 +257,6 @@ static void mtdcr_any(u32 dcr, u32 val)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void wait_ddr_idle(void)
|
|
||||||
{
|
|
||||||
u32 val;
|
|
||||||
|
|
||||||
do {
|
|
||||||
mfsdram(SDRAM_MCSTAT, val);
|
|
||||||
} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned char spd_read(uchar chip, uint addr)
|
static unsigned char spd_read(uchar chip, uint addr)
|
||||||
{
|
{
|
||||||
unsigned char data[2];
|
unsigned char data[2];
|
||||||
@ -491,7 +484,7 @@ long int initdram(int board_type)
|
|||||||
(val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
|
(val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
|
||||||
SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
|
SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
|
||||||
(SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
|
(SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
|
||||||
| SDRAM_MEMODE_RTT_75OHM | SDRAM_MEMODE_DQS_ENABLE));
|
| SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
|
||||||
|
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
* Program Initialization preload registers.
|
* Program Initialization preload registers.
|
||||||
@ -537,10 +530,12 @@ long int initdram(int board_type)
|
|||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
|
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
|
||||||
|
|
||||||
|
#ifdef CONFIG_DDR_ECC
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
* If ecc is enabled, initialize the parity bits.
|
* If ecc is enabled, initialize the parity bits.
|
||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
|
program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
ppc440sp_sdram_register_dump();
|
ppc440sp_sdram_register_dump();
|
||||||
@ -702,7 +697,7 @@ static void check_frequency(unsigned long *dimm_populated,
|
|||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
get_sys_info(&board_cfg);
|
get_sys_info(&board_cfg);
|
||||||
|
|
||||||
mfsdr(sdr_ddr0, sdr_ddrpll);
|
mfsdr(SDR0_DDR0, sdr_ddrpll);
|
||||||
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -877,7 +872,11 @@ static void program_copt1(unsigned long *dimm_populated,
|
|||||||
unsigned long ddrtype;
|
unsigned long ddrtype;
|
||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
|
#ifdef CONFIG_DDR_ECC
|
||||||
ecc_enabled = TRUE;
|
ecc_enabled = TRUE;
|
||||||
|
#else
|
||||||
|
ecc_enabled = FALSE;
|
||||||
|
#endif
|
||||||
dimm_32bit = FALSE;
|
dimm_32bit = FALSE;
|
||||||
dimm_64bit = FALSE;
|
dimm_64bit = FALSE;
|
||||||
buf0 = FALSE;
|
buf0 = FALSE;
|
||||||
@ -1314,7 +1313,7 @@ static void program_mode(unsigned long *dimm_populated,
|
|||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
get_sys_info(&board_cfg);
|
get_sys_info(&board_cfg);
|
||||||
|
|
||||||
mfsdr(sdr_ddr0, sdr_ddrpll);
|
mfsdr(SDR0_DDR0, sdr_ddrpll);
|
||||||
sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
|
sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
|
||||||
|
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
@ -1463,11 +1462,12 @@ static void program_mode(unsigned long *dimm_populated,
|
|||||||
mfsdram(SDRAM_MMODE, mmode);
|
mfsdram(SDRAM_MMODE, mmode);
|
||||||
mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
|
mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
|
||||||
|
|
||||||
cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100);
|
/* add 10 here because of rounding problems */
|
||||||
cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100);
|
cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
|
||||||
cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100);
|
cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
|
||||||
cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100);
|
cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
|
||||||
cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100);
|
cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
|
||||||
|
cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
|
||||||
|
|
||||||
if (sdram_ddr1 == TRUE) { /* DDR1 */
|
if (sdram_ddr1 == TRUE) { /* DDR1 */
|
||||||
if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
|
if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
|
||||||
@ -1498,7 +1498,11 @@ static void program_mode(unsigned long *dimm_populated,
|
|||||||
} else {
|
} else {
|
||||||
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
|
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
|
||||||
printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
|
printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
|
||||||
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
|
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
|
||||||
|
printf("cas3=%d cas4=%d cas5=%d\n",
|
||||||
|
cas_3_0_available, cas_4_0_available, cas_5_0_available);
|
||||||
|
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
|
||||||
|
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
|
||||||
hang();
|
hang();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1575,7 +1579,7 @@ static void program_rtr(unsigned long *dimm_populated,
|
|||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
* Set the SDRAM Refresh Timing Register, SDRAM_RTR
|
* Set the SDRAM Refresh Timing Register, SDRAM_RTR
|
||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
mfsdr(sdr_ddr0, sdr_ddrpll);
|
mfsdr(SDR0_DDR0, sdr_ddrpll);
|
||||||
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
||||||
|
|
||||||
max_refresh_rate = 0;
|
max_refresh_rate = 0;
|
||||||
@ -1661,7 +1665,7 @@ static void program_tr(unsigned long *dimm_populated,
|
|||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
get_sys_info(&board_cfg);
|
get_sys_info(&board_cfg);
|
||||||
|
|
||||||
mfsdr(sdr_ddr0, sdr_ddrpll);
|
mfsdr(SDR0_DDR0, sdr_ddrpll);
|
||||||
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
|
||||||
|
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
@ -2069,7 +2073,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
|
|||||||
* Set the sizes
|
* Set the sizes
|
||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
baseadd_size = 0;
|
baseadd_size = 0;
|
||||||
rank_size_bytes = 1024 * 1024 * rank_size_id;
|
rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
|
||||||
switch (rank_size_id) {
|
switch (rank_size_id) {
|
||||||
case 0x02:
|
case 0x02:
|
||||||
baseadd_size |= SDRAM_RXBAS_SDSZ_8;
|
baseadd_size |= SDRAM_RXBAS_SDSZ_8;
|
||||||
@ -2106,8 +2110,8 @@ static void program_memory_queue(unsigned long *dimm_populated,
|
|||||||
|
|
||||||
for (i = 0; i < num_ranks; i++) {
|
for (i = 0; i < num_ranks; i++) {
|
||||||
mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
|
mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
|
||||||
(rank_base_addr & SDRAM_RXBAS_SDBA_MASK) |
|
(SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
|
||||||
baseadd_size);
|
baseadd_size));
|
||||||
rank_base_addr += rank_size_bytes;
|
rank_base_addr += rank_size_bytes;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2130,9 +2134,10 @@ static unsigned long is_ecc_enabled(void)
|
|||||||
ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
|
ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
|
||||||
}
|
}
|
||||||
|
|
||||||
return(ecc);
|
return ecc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_DDR_ECC
|
||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
* program_ecc.
|
* program_ecc.
|
||||||
*-----------------------------------------------------------------------------*/
|
*-----------------------------------------------------------------------------*/
|
||||||
@ -2208,6 +2213,15 @@ static void check_ecc(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
static void wait_ddr_idle(void)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
do {
|
||||||
|
mfsdram(SDRAM_MCSTAT, val);
|
||||||
|
} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
|
||||||
|
}
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
* program_ecc_addr.
|
* program_ecc_addr.
|
||||||
*-----------------------------------------------------------------------------*/
|
*-----------------------------------------------------------------------------*/
|
||||||
@ -2276,6 +2290,7 @@ static void program_ecc_addr(unsigned long start_address,
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
* program_DQS_calibration.
|
* program_DQS_calibration.
|
||||||
@ -2531,7 +2546,6 @@ static void DQS_calibration_process(void)
|
|||||||
}
|
}
|
||||||
} /* for rffd */
|
} /* for rffd */
|
||||||
|
|
||||||
|
|
||||||
/*------------------------------------------------------------------
|
/*------------------------------------------------------------------
|
||||||
* Set the average RFFD value
|
* Set the average RFFD value
|
||||||
*-----------------------------------------------------------------*/
|
*-----------------------------------------------------------------*/
|
||||||
|
@ -1361,7 +1361,7 @@ ppcSync:
|
|||||||
relocate_code:
|
relocate_code:
|
||||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||||
defined(CONFIG_440SPE)
|
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
/*
|
/*
|
||||||
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
|
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
|
||||||
* to speed up the boot process. Now this cache needs to be disabled.
|
* to speed up the boot process. Now this cache needs to be disabled.
|
||||||
|
@ -108,6 +108,7 @@
|
|||||||
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
||||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||||
#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
|
#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
|
||||||
|
#define CONFIG_DDR_ECC 1 /* with ECC support */
|
||||||
#undef CONFIG_STRESS
|
#undef CONFIG_STRESS
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
|
@ -37,8 +37,9 @@
|
|||||||
#define CONFIG_440 1
|
#define CONFIG_440 1
|
||||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||||
|
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* Base addresses -- Note these are effective addresses where the
|
* Base addresses -- Note these are effective addresses where the
|
||||||
@ -132,10 +133,9 @@
|
|||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* DDR SDRAM
|
* DDR SDRAM
|
||||||
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
||||||
#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
|
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||||
#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
|
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
|
||||||
#define IIC0_DIMM0_ADDR 0x52
|
#undef CONFIG_DDR_ECC /* no ECC support for now */
|
||||||
#define IIC0_DIMM1_ADDR 0x53
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* I2C
|
* I2C
|
||||||
@ -206,11 +206,6 @@
|
|||||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||||
#define CONFIG_NET_MULTI /* needed for NetConsole */
|
#define CONFIG_NET_MULTI /* needed for NetConsole */
|
||||||
|
|
||||||
/* Partitions */
|
|
||||||
#define CONFIG_MAC_PARTITION
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
#define CONFIG_ISO_PARTITION
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
#define CONFIG_PANIC_HANG
|
#define CONFIG_PANIC_HANG
|
||||||
#else
|
#else
|
||||||
@ -219,9 +214,7 @@
|
|||||||
|
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||||
CFG_CMD_ASKENV | \
|
CFG_CMD_ASKENV | \
|
||||||
CFG_CMD_CACHE | \
|
|
||||||
CFG_CMD_DHCP | \
|
CFG_CMD_DHCP | \
|
||||||
CFG_CMD_DIAG | \
|
|
||||||
CFG_CMD_ELF | \
|
CFG_CMD_ELF | \
|
||||||
CFG_CMD_EEPROM | \
|
CFG_CMD_EEPROM | \
|
||||||
CFG_CMD_I2C | \
|
CFG_CMD_I2C | \
|
||||||
@ -232,7 +225,6 @@
|
|||||||
CFG_CMD_PCI | \
|
CFG_CMD_PCI | \
|
||||||
CFG_CMD_PING | \
|
CFG_CMD_PING | \
|
||||||
CFG_CMD_REGINFO | \
|
CFG_CMD_REGINFO | \
|
||||||
CFG_CMD_SETGETDCR | \
|
|
||||||
CFG_CMD_SDRAM | \
|
CFG_CMD_SDRAM | \
|
||||||
0)
|
0)
|
||||||
|
|
||||||
|
@ -45,11 +45,11 @@
|
|||||||
#define EXTCLK_50 50000000
|
#define EXTCLK_50 50000000
|
||||||
#define EXTCLK_83 83333333
|
#define EXTCLK_83 83333333
|
||||||
|
|
||||||
#define CONFIG_IBM_EMAC4_V4 1
|
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
|
||||||
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
|
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
|
||||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||||
#undef CONFIG_STRESS
|
#undef CONFIG_STRESS
|
||||||
#undef ENABLE_ECC
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* Base addresses -- Note these are effective addresses where the
|
* Base addresses -- Note these are effective addresses where the
|
||||||
* actual resources get mapped (not physical addresses)
|
* actual resources get mapped (not physical addresses)
|
||||||
@ -118,10 +118,9 @@
|
|||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* DDR SDRAM
|
* DDR SDRAM
|
||||||
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
||||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||||
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */
|
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
|
||||||
#define IIC0_DIMM0_ADDR 0x53
|
#undef CONFIG_DDR_ECC /* no ECC support for now */
|
||||||
#define IIC0_DIMM1_ADDR 0x52
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* I2C
|
* I2C
|
||||||
@ -211,6 +210,7 @@
|
|||||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
#include <cmd_confdefs.h>
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
#define CONFIG_IBM_EMAC4_V4 1
|
||||||
#define CONFIG_MII 1 /* MII PHY management */
|
#define CONFIG_MII 1 /* MII PHY management */
|
||||||
#undef CONFIG_NET_MULTI
|
#undef CONFIG_NET_MULTI
|
||||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
|
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
|
||||||
|
@ -417,7 +417,9 @@
|
|||||||
#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
|
#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
|
||||||
#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
|
#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
|
||||||
#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
|
#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
|
||||||
|
#endif /* CONFIG_440SPE */
|
||||||
|
|
||||||
|
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||||
/*----------------------------------------------------------------------------+
|
/*----------------------------------------------------------------------------+
|
||||||
| SDRAM Controller
|
| SDRAM Controller
|
||||||
+----------------------------------------------------------------------------*/
|
+----------------------------------------------------------------------------*/
|
||||||
@ -453,9 +455,16 @@
|
|||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
| Memory Bank 0-7 configuration
|
| Memory Bank 0-7 configuration
|
||||||
+-----------------------------------------------------------------------------*/
|
+-----------------------------------------------------------------------------*/
|
||||||
#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
|
#if defined(CONFIG_440SPE)
|
||||||
|
#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
|
||||||
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
|
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
|
||||||
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
|
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
|
||||||
|
#endif /* CONFIG_440SPE */
|
||||||
|
#if defined(CONFIG_440SP)
|
||||||
|
#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
|
||||||
|
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
|
||||||
|
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
|
||||||
|
#endif /* CONFIG_440SP */
|
||||||
#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
|
#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
|
||||||
#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
|
#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
|
||||||
#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
|
#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
|
||||||
@ -2167,6 +2176,20 @@
|
|||||||
/*-----------------------------------------------------------------------------+
|
/*-----------------------------------------------------------------------------+
|
||||||
| SDR0 Bit Settings
|
| SDR0 Bit Settings
|
||||||
+-----------------------------------------------------------------------------*/
|
+-----------------------------------------------------------------------------*/
|
||||||
|
#if defined(CONFIG_440SP)
|
||||||
|
#define SDR0_SRST 0x0200
|
||||||
|
|
||||||
|
#define SDR0_DDR0 0x00E1
|
||||||
|
#define SDR0_DDR0_DPLLRST 0x80000000
|
||||||
|
#define SDR0_DDR0_DDRM_MASK 0x60000000
|
||||||
|
#define SDR0_DDR0_DDRM_DDR1 0x20000000
|
||||||
|
#define SDR0_DDR0_DDRM_DDR2 0x40000000
|
||||||
|
#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
|
||||||
|
#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
|
||||||
|
#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
|
||||||
|
#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_440SPE)
|
#if defined(CONFIG_440SPE)
|
||||||
#define SDR0_CP440 0x0180
|
#define SDR0_CP440 0x0180
|
||||||
#define SDR0_CP440_ERPN_MASK 0x30000000
|
#define SDR0_CP440_ERPN_MASK 0x30000000
|
||||||
|
Loading…
Reference in New Issue
Block a user