brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

* Patch by Jian Zhang, 3 Feb 2004:

Browse Source 
- Changed the incorrect FAT12BUFSIZE
  - data_begin in fsdata can be negative. Changed it to be short.
* Code cleanup
This commit is contained in:
wdenk 2004-02-10 00:03:41 +00:00
parent ec4c544bed
commit cd37d9e6e5
9 changed files with 45 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
CHANGELOG
View File

@ -2,6 +2,10 @@
Changes since U-Boot 1.0.1: Changes since U-Boot 1.0.1:
====================================================================== ======================================================================
* Patch by Jian Zhang, 3 Feb 2004:
- Changed the incorrect FAT12BUFSIZE
- data_begin in fsdata can be negative. Changed it to be short.
* Patches by Stephan Linz, 30 Jan 2004: * Patches by Stephan Linz, 30 Jan 2004:
1: - board/altera/common/flash.c:flash_erase(): 1: - board/altera/common/flash.c:flash_erase():
o allow interrupts befor get_timer() call o allow interrupts befor get_timer() call

2
board/esteem192e/esteem192e.c
View File

@ -113,7 +113,7 @@ long int initdram (int board_type)
memctl->memc_mptpr = 0x0200; /* divide by 32 */ memctl->memc_mptpr = 0x0200; /* divide by 32 */
memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */ memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
upmconfig (UPMA, (uint *) sdram_table, upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint)); sizeof (sdram_table) / sizeof (uint));

30
board/omap1610inn/flash.c
View File

@ -19,7 +19,7 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
@ -32,7 +32,7 @@
#include <linux/byteorder/swab.h> #include <linux/byteorder/swab.h>
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */ /* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32 #undef FLASH_PORT_WIDTH32
@ -120,13 +120,13 @@ unsigned long flash_init (void)
*/ */
flash_unlock(flash_info_t * info) flash_unlock(flash_info_t * info)
{ {
int j; int j;
for (j=2;j<CFG_MAX_FLASH_SECT;j++){ for (j=2;j<CFG_MAX_FLASH_SECT;j++){
FPWV *addr = (FPWV *) (info->start[j]); FPWV *addr = (FPWV *) (info->start[j]);
flash_unprotect_sectors (addr); flash_unprotect_sectors (addr);
*addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00FF00FF;/* resest to read mode */ *addr = (FPW) 0x00FF00FF;/* resest to read mode */
} }
} }
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -192,7 +192,7 @@ void flash_print_info (flash_info_t * info)
if ((i % 5) == 0) if ((i % 5) == 0)
printf ("\n "); printf ("\n ");
printf (" %08lX%s", printf (" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " "); info->start[i], info->protect[i] ? " (RO)" : " ");
} }
printf ("\n"); printf ("\n");
return; return;
@ -224,18 +224,18 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
info->sector_count = 0; info->sector_count = 0;
info->size = 0; info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */ return (0); /* no or unknown flash */
} }
mb (); mb ();
value = addr[1]; /* device ID */ value = addr[1]; /* device ID */
switch (value) { switch (value) {
case (FPW) (INTEL_ID_28F256L18T): case (FPW) (INTEL_ID_28F256L18T):
info->flash_id += FLASH_28F256L18T; info->flash_id += FLASH_28F256L18T;
info->sector_count = 259; info->sector_count = 259;
info->size = 0x02000000; info->size = 0x02000000;
break; /* => 32 MB */ break; /* => 32 MB */
default: default:
info->flash_id = FLASH_UNKNOWN; info->flash_id = FLASH_UNKNOWN;
@ -318,7 +318,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
/* Start erase on unprotected sectors */ /* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) { for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */ if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]); FPWV *addr = (FPWV *) (info->start[sect]);
FPW status; FPW status;
@ -348,7 +348,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
} }
} }
/* clear status register cmd. */ /* clear status register cmd. */
*addr = (FPW) 0x00500050; *addr = (FPW) 0x00500050;
*addr = (FPW) 0x00FF00FF;/* resest to read mode */ *addr = (FPW) 0x00FF00FF;/* resest to read mode */
printf (" done\n"); printf (" done\n");

4
board/tb0229/flash.c
View File

@ -860,7 +860,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
} }
for (info = info_first; info <= info_last; ++info) { for (info = info_first; info <= info_last; ++info) {
ulong b_end = info->start[0] + info->size;*//* bank end addr */ ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
/* short s_end = info->sector_count - 1; /* short s_end = info->sector_count - 1;
for (i=0; i<info->sector_count; ++i) { for (i=0; i<info->sector_count; ++i) {
ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
@ -872,7 +872,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
} }
} }
*//* finally write data to flash */ */ /* finally write data to flash */
/* for (info = info_first; info <= info_last && cnt>0; ++info) { /* for (info = info_first; info <= info_last && cnt>0; ++info) {
ulong len; ulong len;

34
drivers/cfi_flash.c
View File

@ -30,11 +30,11 @@
* Tested Architectures * Tested Architectures
* Port Width Chip Width # of banks Flash Chip Board * Port Width Chip Width # of banks Flash Chip Board
* 32 16 1 23F128J3 seranoa/eagle * 32 16 1 23F128J3 seranoa/eagle
* *
*/ */
/* The DEBUG define must be before common to enable debugging */ /* The DEBUG define must be before common to enable debugging */
#undef DEBUG #undef DEBUG
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#ifdef CFG_FLASH_CFI_DRIVER #ifdef CFG_FLASH_CFI_DRIVER
@ -170,8 +170,8 @@ void print_longlong(char * str, unsigned long long data)
int i; int i;
char *cp; char *cp;
cp = (unsigned char *)&data; cp = (unsigned char *)&data;
for(i=0;i<8; i++) for(i=0;i<8; i++)
sprintf(&str[i*2], "%2.2x", *cp++); sprintf(&str[i*2], "%2.2x", *cp++);
} }
#endif #endif
@ -501,7 +501,7 @@ void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int
void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len) void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len)
{ {
uchar * src; uchar * src;
src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION); src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID); flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID);
memcpy(buffer,src + offset,len); memcpy(buffer,src + offset,len);
@ -510,7 +510,7 @@ void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, i
#endif /* CFG_FLASH_PROTECTION */ #endif /* CFG_FLASH_PROTECTION */
static int flash_poll_status(flash_info_t * info, flash_sect_t sect) static int flash_poll_status(flash_info_t * info, flash_sect_t sect)
{ {
int retval; int retval;
switch(info->vendor) { switch(info->vendor) {
@ -626,27 +626,27 @@ static void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset,
flash_make_cmd(info, cmd, &cword); flash_make_cmd(info, cmd, &cword);
switch(info->portwidth) { switch(info->portwidth) {
case FLASH_CFI_8BIT: case FLASH_CFI_8BIT:
debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c, debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.cp = cword.c; *addr.cp = cword.c;
break; break;
case FLASH_CFI_16BIT: case FLASH_CFI_16BIT:
debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w, debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.wp = cword.w; *addr.wp = cword.w;
break; break;
case FLASH_CFI_32BIT: case FLASH_CFI_32BIT:
debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l, debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
*addr.lp = cword.l; *addr.lp = cword.l;
break; break;
case FLASH_CFI_64BIT: case FLASH_CFI_64BIT:
#ifdef DEBUG #ifdef DEBUG
{ {
char str[20]; char str[20];
print_longlong(str, cword.ll); print_longlong(str, cword.ll);
printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str, printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
} }
#endif #endif
@ -685,7 +685,7 @@ static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint offset, uc
retval = (cptr.lp[0] == cword.l); retval = (cptr.lp[0] == cword.l);
break; break;
case FLASH_CFI_64BIT: case FLASH_CFI_64BIT:
#ifdef DEBUG #ifdef DEBUG
{ {
char str1[20]; char str1[20];
char str2[20]; char str2[20];
@ -776,14 +776,14 @@ static int flash_detect_cfi(flash_info_t * info)
info->chipwidth >>= 1) { */ info->chipwidth >>= 1) { */
for(info->chipwidth =FLASH_CFI_BY8; for(info->chipwidth =FLASH_CFI_BY8;
info->chipwidth <= info->portwidth; info->chipwidth <= info->portwidth;
info->chipwidth <<= 1) { info->chipwidth <<= 1) {
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
debug("found port %d chip %d ", info->portwidth, info->chipwidth); debug("found port %d chip %d ", info->portwidth, info->chipwidth);
debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH, debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
return 1; return 1;
} }
@ -823,11 +823,11 @@ static ulong flash_get_size (ulong base, int banknum)
info->cmd_reset = AMD_CMD_RESET; info->cmd_reset = AMD_CMD_RESET;
break; break;
} }
debug("manufacturer is %d\n", info->vendor); debug("manufacturer is %d\n", info->vendor);
size_ratio = info->portwidth / info->chipwidth; size_ratio = info->portwidth / info->chipwidth;
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH); info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
debug("found %d erase regions\n", num_erase_regions); debug("found %d erase regions\n", num_erase_regions);
sect_cnt = 0; sect_cnt = 0;

6
drivers/pci_auto.c
View File

@ -296,11 +296,11 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io); pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
/* TBS: Passing in current_busno allows for sibling P2P bridges */ /* TBS: Passing in current_busno allows for sibling P2P bridges */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
/* /*
* TBS: need to figure out if this is a subordinate bridge on the bus * TBS: need to figure out if this is a subordinate bridge on the bus
* to be able to properly set the pri/sec/sub bridge registers. * to be able to properly set the pri/sec/sub bridge registers.
*/ */
n = pci_hose_scan_bus(hose, hose->current_busno); n = pci_hose_scan_bus(hose, hose->current_busno);

2
include/configs/tb0229.h
View File

@ -84,7 +84,7 @@
"cp.b 80400000 BFC60000 $(filesize)\0" \ "cp.b 80400000 BFC60000 $(filesize)\0" \
"initenv=erase bfc40000 bfc5ffff\0" \ "initenv=erase bfc40000 bfc5ffff\0" \
"" ""
//#define CONFIG_BOOTCOMMAND "run flash_local" /*#define CONFIG_BOOTCOMMAND "run flash_local" */
#define CONFIG_BOOTCOMMAND "run netboot" #define CONFIG_BOOTCOMMAND "run netboot"
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \

4
include/fat.h
View File

@ -43,7 +43,7 @@
#define FATBUFBLOCKS 6 #define FATBUFBLOCKS 6
#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS) #define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS)
#define FAT12BUFSIZE ((FATBUFSIZE*3)/2) #define FAT12BUFSIZE ((FATBUFSIZE*2)/3)
#define FAT16BUFSIZE (FATBUFSIZE/2) #define FAT16BUFSIZE (FATBUFSIZE/2)
#define FAT32BUFSIZE (FATBUFSIZE/4) #define FAT32BUFSIZE (FATBUFSIZE/4)
@ -176,7 +176,7 @@ typedef struct {
__u16 fat_sect; /* Starting sector of the FAT */ __u16 fat_sect; /* Starting sector of the FAT */
__u16 rootdir_sect; /* Start sector of root directory */ __u16 rootdir_sect; /* Start sector of root directory */
__u16 clust_size; /* Size of clusters in sectors */ __u16 clust_size; /* Size of clusters in sectors */
__u16 data_begin; /* The sector of the first cluster */ short data_begin; /* The sector of the first cluster, can be negative */
__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatbufnum; /* Used by get_fatent, init to -1 */ int fatbufnum; /* Used by get_fatent, init to -1 */
} fsdata; } fsdata;

8
rtc/ds1306.c
View File

@ -74,10 +74,6 @@ static unsigned char bcd2bin (unsigned char c);
static unsigned char rtc_read (unsigned char reg); static unsigned char rtc_read (unsigned char reg);
static void rtc_write (unsigned char reg, unsigned char val); static void rtc_write (unsigned char reg, unsigned char val);
/* ************************************************************************* */ /* ************************************************************************* */
#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ #ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
@ -306,10 +302,6 @@ void rtc_reset (void)
#else /* not CONFIG_SXNI855T */ #else /* not CONFIG_SXNI855T */
/* ************************************************************************* */ /* ************************************************************************* */
/* read clock time from DS1306 and return it in *tmp */ /* read clock time from DS1306 and return it in *tmp */
void rtc_get (struct rtc_time *tmp) void rtc_get (struct rtc_time *tmp)
{ {