brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-09-29 16:10:24 +09:00
Code Issues Projects Releases Wiki Activity

* Patch by Yuli Barcohen, 23 Jun 2003:

Browse Source 
Update for MPC8260ADS board

* Patch by Murray Jensen, 23 Jun 2003:
  - cleanup of GCC 3.x compiler warnings
This commit is contained in:
wdenk 2003-06-23 18:12:28 +00:00
parent 3595ac4979
commit cceb871fff
5 changed files with 46 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
CHANGELOG
View File

@ -2,6 +2,12 @@
Changes since U-Boot 0.3.1: Changes since U-Boot 0.3.1:
====================================================================== ======================================================================
* Patch by Yuli Barcohen, 23 Jun 2003:
Update for MPC8260ADS board
* Patch by Murray Jensen, 23 Jun 2003:
- cleanup of GCC 3.x compiler warnings
* Patch by Rune Torgersen, 4 Jun 2003: * Patch by Rune Torgersen, 4 Jun 2003:
add large memory support for MPC8266ADS board add large memory support for MPC8266ADS board

56
board/mpc8260ads/mpc8260ads.c
View File

@ -37,6 +37,7 @@
#include <mpc8260.h> #include <mpc8260.h>
#include <i2c.h> #include <i2c.h>
#include <spd.h> #include <spd.h>
#include <miiphy.h>
/* /*
* I/O Port configuration table * I/O Port configuration table
@ -133,8 +134,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
@ -142,8 +143,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
@ -157,8 +158,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port D */ /* Port D */
{ /* conf ppar psor pdir podr pdat */ { /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
@ -173,14 +174,14 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
@ -192,32 +193,33 @@ const iop_conf_t iop_conf_tab[4][32] = {
} }
}; };
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
void reset_phy (void) void reset_phy (void)
{ {
volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; vu_long *bcsr = (vu_long *)CFG_BCSR;
/* reset the FEC port */ /* reset the FEC port */
bcsr->bcsr1 &= ~FETH_RST; bcsr[1] &= ~FETH_RST;
bcsr->bcsr1 |= FETH_RST; udelay(2);
bcsr[1] |= FETH_RST;
udelay(1000);
#ifdef CONFIG_MII
/*
* Ethernet PHY is configured (by means of configuration pins)
* to work at 10Mb/s only. We reconfigure it using MII
* to advertise all capabilities, including 100Mb/s, and
* restart autonegotiation.
*/
miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
} }
int board_pre_init (void) int board_pre_init (void)
{ {
volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; vu_long *bcsr = (vu_long *)CFG_BCSR;
bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1; bcsr[1] = ~FETHIEN & ~RS232EN_1;
return 0; return 0;
} }

12
common/cmd_ide.c
View File

@ -792,15 +792,7 @@ ide_inb(int dev, int port)
#endif /* __PPC__ */ #endif /* __PPC__ */
#ifdef __PPC__ #ifdef __PPC__
__inline__ unsigned ld_le16(const volatile unsigned short *addr) # ifdef CONFIG_AMIGAONEG3SE
{
unsigned val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));
return val;
}
#ifdef CONFIG_AMIGAONEG3SE
static void static void
output_data_short(int dev, ulong *sect_buf, int words) output_data_short(int dev, ulong *sect_buf, int words)
{ {
@ -818,7 +810,7 @@ output_data_short(int dev, ulong *sect_buf, int words)
if (words&1) if (words&1)
*pbuf = 0; *pbuf = 0;
} }
#endif # endif /* CONFIG_AMIGAONEG3SE */
static void static void
input_swap_data(int dev, ulong *sect_buf, int words) input_swap_data(int dev, ulong *sect_buf, int words)

8
cpu/mpc5xx/cpu.c
View File

@ -131,10 +131,10 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr; ulong addr;
/* Interrupts off, enable reset */ /* Interrupts off, enable reset */
__asm__ volatile (" mtspr 81, %r0 \n\t __asm__ volatile (" mtspr 81, %r0 \n\t"
mfmsr %r3 \n\t " mfmsr %r3 \n\t"
rlwinm %r31,%r3,0,25,23\n\t " rlwinm %r31,%r3,0,25,23\n\t"
mtmsr %r31 \n\t"); " mtmsr %r31 \n\t");
/* /*
* Trying to execute the next instruction at a non-existing address * Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset * should cause a machine check, resulting in reset

7
include/configs/MPC8260ADS.h
View File

@ -7,6 +7,10 @@
* Note: my board is a PILOT rev. * Note: my board is a PILOT rev.
* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
* *
* (C) Copyright 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
* Added support for SDRAM DIMMs SPD EEPROM, MII.
*
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
* *
@ -145,9 +149,8 @@
CFG_CMD_IDE | \ CFG_CMD_IDE | \
CFG_CMD_JFFS2 | \ CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \ CFG_CMD_KGDB | \
CFG_CMD_NAND | \
CFG_CMD_MII | \
CFG_CMD_MMC | \ CFG_CMD_MMC | \
CFG_CMD_NAND | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \ CFG_CMD_PCMCIA | \
CFG_CMD_SCSI | \ CFG_CMD_SCSI | \