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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
video: mb862xx: use macros instead of magic numbers
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin
parent
e86528671e
commit
cce99b2a7d
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@ -70,29 +70,30 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
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#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
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#endif
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#define HOST_RD_REG(off) rd_io((dev->frameAdrs + 0x01fc0000 + (off)))
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#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fc0000 + (off)), \
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#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
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#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
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(val))
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#define DISP_RD_REG(off) rd_io((dev->frameAdrs + 0x01fd0000 + (off)))
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#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fd0000 + (off)), \
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#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
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#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
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(val))
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#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
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#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
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#if defined(CONFIG_VIDEO_CORALP)
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x8400)), (val))
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
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#else
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x04a0)), (val))
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#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
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#endif
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#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + 0x01fd0400 + \
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#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
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(GC_DISP_BASE | GC_L0PAL0) + \
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((idx) << 2)), (val))
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static void gdc_sw_reset (void)
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{
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GraphicDevice *dev = &mb862xx;
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HOST_WR_REG (0x002c, 0x00000001);
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HOST_WR_REG (GC_SRST, 0x1);
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udelay (500);
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video_hw_init ();
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}
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@ -107,7 +108,7 @@ static void de_wait (void)
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* Sync with software writes to framebuffer,
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* try to reset if engine locked
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*/
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while (DE_RD_REG (0x0400) & 0x00000131)
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while (DE_RD_REG (GC_CTR) & 0x00000131)
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if (lc-- < 0) {
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gdc_sw_reset ();
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printf ("gdc reset done after drawing engine lock.\n");
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@ -121,7 +122,7 @@ static void de_wait_slots (int slots)
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int lc = 0x10000;
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/* Wait for free fifo slots */
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while (DE_RD_REG (0x0408) < slots)
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while (DE_RD_REG (GC_IFCNT) < slots)
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if (lc-- < 0) {
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gdc_sw_reset ();
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printf ("gdc reset done after drawing engine lock.\n");
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@ -150,21 +151,21 @@ static void de_init (void)
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GraphicDevice *dev = &mb862xx;
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int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
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dev->dprBase = dev->frameAdrs + 0x01ff0000;
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dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
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/* Setup mode and fbbase, xres, fg, bg */
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de_wait_slots (2);
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DE_WR_FIFO (0xf1010108);
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DE_WR_FIFO (cf | 0x0300);
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DE_WR_REG (0x0440, 0x0000);
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DE_WR_REG (0x0444, dev->winSizeX);
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DE_WR_REG (0x0480, 0x0000);
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DE_WR_REG (0x0484, 0x0000);
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DE_WR_REG (GC_FBR, 0x0);
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DE_WR_REG (GC_XRES, dev->winSizeX);
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DE_WR_REG (GC_FC, 0x0);
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DE_WR_REG (GC_BC, 0x0);
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/* Reset clipping */
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DE_WR_REG (0x0454, 0x0000);
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DE_WR_REG (0x0458, dev->winSizeX);
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DE_WR_REG (0x045c, 0x0000);
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DE_WR_REG (0x0460, dev->winSizeY);
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DE_WR_REG (GC_CXMIN, 0x0);
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DE_WR_REG (GC_CXMAX, dev->winSizeX);
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DE_WR_REG (GC_CYMIN, 0x0);
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DE_WR_REG (GC_CYMAX, dev->winSizeY);
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/* Clear framebuffer using drawing engine */
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de_wait_slots (3);
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@ -200,9 +201,9 @@ unsigned int pci_video_init (void)
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dev->pciBase = dev->frameAdrs;
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/* Setup clocks and memory mode for Coral-P Eval. Board */
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HOST_WR_REG (0x0038, 0x00090000);
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HOST_WR_REG (GC_CCF, 0x00090000);
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udelay (200);
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HOST_WR_REG (0xfffc, 0x11d7fa13);
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HOST_WR_REG (GC_MMR, 0x11d7fa13);
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udelay (100);
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return dev->frameAdrs;
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}
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@ -301,36 +302,39 @@ unsigned int card_init (void)
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}
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/* Setup dot clock (internal pll, division rate) */
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DISP_WR_REG (0x0100, div);
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DISP_WR_REG (GC_DCM1, div);
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/* L0 init */
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cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
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DISP_WR_REG (0x0020, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
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DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
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(dev->winSizeY - 1) | cf);
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DISP_WR_REG (0x0024, 0x00000000);
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DISP_WR_REG (0x0028, 0x00000000);
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DISP_WR_REG (0x002c, 0x00000000);
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DISP_WR_REG (0x0110, 0x00000000);
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DISP_WR_REG (0x0114, 0x00000000);
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DISP_WR_REG (0x0118, (dev->winSizeY - 1) << 16 | dev->winSizeX);
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DISP_WR_REG (GC_L0OA0, 0x0);
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DISP_WR_REG (GC_L0DA0, 0x0);
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DISP_WR_REG (GC_L0DY_L0DX, 0x0);
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DISP_WR_REG (GC_L0EM, 0x0);
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DISP_WR_REG (GC_L0WY_L0WX, 0x0);
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DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
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/* Display timing init */
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DISP_WR_REG (0x0004, (dev->winSizeX +
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res_mode->left_margin +
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res_mode->right_margin +
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res_mode->hsync_len - 1) << 16);
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DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1));
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DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 |
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(res_mode->hsync_len - 1) << 16 |
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(dev->winSizeX + res_mode->right_margin - 1));
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DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin +
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res_mode->upper_margin +
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res_mode->vsync_len - 1) << 16);
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DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 |
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(dev->winSizeY + res_mode->lower_margin - 1));
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DISP_WR_REG (0x0018, 0x00000000);
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DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX);
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DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
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res_mode->left_margin +
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res_mode->right_margin +
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res_mode->hsync_len - 1) << 16);
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DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
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(dev->winSizeX - 1));
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DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
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(res_mode->hsync_len - 1) << 16 |
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(dev->winSizeX +
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res_mode->right_margin - 1));
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DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
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res_mode->upper_margin +
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res_mode->vsync_len - 1) << 16);
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DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
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(dev->winSizeY +
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res_mode->lower_margin - 1));
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DISP_WR_REG (GC_WY_WX, 0x0);
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DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
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/* Display enable, L0 layer */
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DISP_WR_REG (0x0100, 0x80010000 | div);
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DISP_WR_REG (GC_DCM1, 0x80010000 | div);
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return dev->frameAdrs;
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}
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@ -395,7 +399,7 @@ void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
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GraphicDevice *dev = &mb862xx;
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de_wait_slots (3);
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DE_WR_REG (0x0480, color);
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DE_WR_REG (GC_FC, color);
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DE_WR_FIFO (0x09410000);
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DE_WR_FIFO ((dst_y << 16) | dst_x);
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DE_WR_FIFO ((dim_y << 16) | dim_x);
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@ -32,6 +32,75 @@
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#define PCI_DEVICE_ID_CORAL_P 0x2019
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#define PCI_DEVICE_ID_CORAL_PA 0x201E
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#define GC_HOST_BASE 0x01fc0000
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#define GC_DISP_BASE 0x01fd0000
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#define GC_DRAW_BASE 0x01ff0000
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/* Host interface registers */
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#define GC_SRST 0x0000002c
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#define GC_CCF 0x00000038
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#define GC_MMR 0x0000fffc
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/*
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* Display Controller registers
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* _A means the offset is aligned, we use these for boards
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* with 8-/16-bit GDC access not working or buggy.
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*/
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#define GC_DCM0 0x00000000
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#define GC_HTP_A 0x00000004
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#define GC_HTP 0x00000006
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#define GC_HDB_HDP_A 0x00000008
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#define GC_HDP 0x00000008
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#define GC_HDB 0x0000000a
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#define GC_VSW_HSW_HSP_A 0x0000000c
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#define GC_HSP 0x0000000c
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#define GC_HSW 0x0000000e
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#define GC_VSW 0x0000000f
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#define GC_VTR_A 0x00000010
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#define GC_VTR 0x00000012
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#define GC_VDP_VSP_A 0x00000014
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#define GC_VSP 0x00000014
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#define GC_VDP 0x00000016
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#define GC_WY_WX 0x00000018
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#define GC_WH_WW 0x0000001c
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#define GC_L0M 0x00000020
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#define GC_L0OA0 0x00000024
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#define GC_L0DA0 0x00000028
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#define GC_L0DY_L0DX 0x0000002c
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#define GC_L2M 0x00000040
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#define GC_L2OA0 0x00000044
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#define GC_L2DA0 0x00000048
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#define GC_L2OA1 0x0000004c
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#define GC_L2DA1 0x00000050
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#define GC_L2DX 0x00000054
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#define GC_L2DY 0x00000056
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#define GC_DCM1 0x00000100
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#define GC_DCM2 0x00000104
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#define GC_DCM3 0x00000108
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#define GC_L0EM 0x00000110
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#define GC_L0WY_L0WX 0x00000114
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#define GC_L0WH_L0WW 0x00000118
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#define GC_L2EM 0x00000130
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#define GC_L2WX 0x00000134
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#define GC_L2WY 0x00000136
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#define GC_L2WW 0x00000138
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#define GC_L2WH 0x0000013a
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#define GC_L0PAL0 0x00000400
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/* Drawing registers */
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#define GC_CTR 0x00000400
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#define GC_IFCNT 0x00000408
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#define GC_FBR 0x00000440
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#define GC_XRES 0x00000444
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#define GC_CXMIN 0x00000454
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#define GC_CXMAX 0x00000458
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#define GC_CYMIN 0x0000045c
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#define GC_CYMAX 0x00000460
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#define GC_FC 0x00000480
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#define GC_BC 0x00000484
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#define GC_FIFO 0x000004a0
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#define GC_GEO_FIFO 0x00008400
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typedef struct {
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unsigned int index;
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unsigned int value;
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