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TI: Davinci: NAND Driver Cleanup

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Modified to use IO accessor routines consistently.  Eliminated volatile usage
to keep checkpatch.pl happy.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
This commit is contained in:
Cyril Chemparathy 2010-03-17 10:03:10 -04:00 committed by Scott Wood
parent 859500a2be
commit cc41a59a74
3 changed files with 106 additions and 101 deletions
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2
board/davinci/da830evm/da830evm.c
View File

@ -150,7 +150,7 @@ int board_init(void)
DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) | DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT), DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->AB2CR); &davinci_emif_regs->ab2cr);
#endif #endif
/* arch number of the board */ /* arch number of the board */

104
drivers/mtd/nand/davinci_nand.c
View File

@ -57,8 +57,6 @@
#define ECC_STATE_ERR_CORR_COMP_P 0x2 #define ECC_STATE_ERR_CORR_COMP_P 0x2
#define ECC_STATE_ERR_CORR_COMP_N 0x3 #define ECC_STATE_ERR_CORR_COMP_N 0x3
static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
/* /*
* Exploit the little endianness of the ARM to do multi-byte transfers * Exploit the little endianness of the ARM to do multi-byte transfers
* per device read. This can perform over twice as quickly as individual * per device read. This can perform over twice as quickly as individual
@ -93,7 +91,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
/* copy aligned data */ /* copy aligned data */
while (len >= 4) { while (len >= 4) {
*(u32 *)buf = readl(nand); *(u32 *)buf = __raw_readl(nand);
buf += 4; buf += 4;
len -= 4; len -= 4;
} }
@ -138,7 +136,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
/* copy aligned data */ /* copy aligned data */
while (len >= 4) { while (len >= 4) {
writel(*(u32 *)buf, nand); __raw_writel(*(u32 *)buf, nand);
buf += 4; buf += 4;
len -= 4; len -= 4;
} }
@ -156,7 +154,8 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
} }
} }
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
@ -181,24 +180,26 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{ {
u_int32_t val; u_int32_t val;
(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); (void)__raw_readl(&(davinci_emif_regs->nandfecc[
CONFIG_SYS_NAND_CS - 2]));
val = readl(&emif_regs->NANDFCR); val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
writel(val, &emif_regs->NANDFCR); __raw_writel(val, &davinci_emif_regs->nandfcr);
} }
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
{ {
u_int32_t ecc = 0; u_int32_t ecc = 0;
ecc = readl(&(emif_regs->NANDFECC[region - 1])); ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
return(ecc); return ecc;
} }
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{ {
u_int32_t tmp; u_int32_t tmp;
const int region = 1; const int region = 1;
@ -232,7 +233,8 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
return 0; return 0;
} }
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
@ -268,7 +270,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
return -1; return -1;
} }
} }
return(0); return 0;
} }
#endif /* CONFIG_SYS_NAND_HW_ECC */ #endif /* CONFIG_SYS_NAND_HW_ECC */
@ -315,15 +317,15 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
* Start a new ECC calculation for reading or writing 512 bytes * Start a new ECC calculation for reading or writing 512 bytes
* of data. * of data.
*/ */
val = readl(&emif_regs->NANDFCR); val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START; val |= DAVINCI_NANDFCR_4BIT_ECC_START;
writel(val, &emif_regs->NANDFCR); __raw_writel(val, &davinci_emif_regs->nandfcr);
break; break;
case NAND_ECC_READSYN: case NAND_ECC_READSYN:
val = emif_regs->NAND4BITECC1; val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
break; break;
default: default:
break; break;
@ -332,10 +334,12 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{ {
ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK; int i;
ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK; for (i = 0; i < 4; i++) {
ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK; ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
NAND_4BITECC_MASK;
}
return 0; return 0;
} }
@ -418,32 +422,36 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
*/ */
/*Take 2 bits from 8th byte and 8 bits from 9th byte */ /*Take 2 bits from 8th byte and 8 bits from 9th byte */
writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD); __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
&davinci_emif_regs->nand4biteccload);
/* Take 4 bits from 7th byte and 6 bits from 8th byte */ /* Take 4 bits from 7th byte and 6 bits from 8th byte */
writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
&emif_regs->NAND4BITECCLOAD); &davinci_emif_regs->nand4biteccload);
/* Take 6 bits from 6th byte and 4 bits from 7th byte */ /* Take 6 bits from 6th byte and 4 bits from 7th byte */
writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD); __raw_writel((ecc16[3] >> 2) & 0x3FF,
&davinci_emif_regs->nand4biteccload);
/* Take 8 bits from 5th byte and 2 bits from 6th byte */ /* Take 8 bits from 5th byte and 2 bits from 6th byte */
writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
&emif_regs->NAND4BITECCLOAD); &davinci_emif_regs->nand4biteccload);
/*Take 2 bits from 3rd byte and 8 bits from 4th byte */ /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
&emif_regs->NAND4BITECCLOAD); &davinci_emif_regs->nand4biteccload);
/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD); __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
&davinci_emif_regs->nand4biteccload);
/* Take 6 bits from 1st byte and 4 bits from 2nd byte */ /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
&emif_regs->NAND4BITECCLOAD); &davinci_emif_regs->nand4biteccload);
/* Take 10 bits from 0th and 1st bytes */ /* Take 10 bits from 0th and 1st bytes */
writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD); __raw_writel((ecc16[0]) & 0x3FF,
&davinci_emif_regs->nand4biteccload);
/* /*
* Perform a dummy read to the EMIF Revision Code and Status register. * Perform a dummy read to the EMIF Revision Code and Status register.
@ -451,7 +459,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
* writing the ECC values in previous step. * writing the ECC values in previous step.
*/ */
val = emif_regs->NANDFSR; val = __raw_readl(&davinci_emif_regs->nandfsr);
/* /*
* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
@ -467,13 +475,13 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
* Clear any previous address calculation by doing a dummy read of an * Clear any previous address calculation by doing a dummy read of an
* error address register. * error address register.
*/ */
val = emif_regs->NANDERRADD1; val = __raw_readl(&davinci_emif_regs->nanderradd1);
/* /*
* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
* register to 1. * register to 1.
*/ */
emif_regs->NANDFCR |= 1 << 13; __raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
/* /*
* Wait for the corr_state field (bits 8 to 11)in the * Wait for the corr_state field (bits 8 to 11)in the
@ -481,12 +489,12 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
*/ */
i = NAND_TIMEOUT; i = NAND_TIMEOUT;
do { do {
val = emif_regs->NANDFSR; val = __raw_readl(&davinci_emif_regs->nandfsr);
val &= 0xc00; val &= 0xc00;
i--; i--;
} while ((i > 0) && val); } while ((i > 0) && val);
iserror = emif_regs->NANDFSR; iserror = __raw_readl(&davinci_emif_regs->nandfsr);
iserror &= EMIF_NANDFSR_ECC_STATE_MASK; iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
iserror = iserror >> 8; iserror = iserror >> 8;
@ -501,32 +509,33 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
*/ */
if (iserror == ECC_STATE_NO_ERR) { if (iserror == ECC_STATE_NO_ERR) {
val = emif_regs->NANDERRVAL1; val = __raw_readl(&davinci_emif_regs->nanderrval1);
return 0; return 0;
} else if (iserror == ECC_STATE_TOO_MANY_ERRS) { } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
val = emif_regs->NANDERRVAL1; val = __raw_readl(&davinci_emif_regs->nanderrval1);
return -1; return -1;
} }
numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1; numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
& 0x3) + 1;
/* Read the error address, error value and correct */ /* Read the error address, error value and correct */
for (i = 0; i < numerrors; i++) { for (i = 0; i < numerrors; i++) {
if (i > 1) { if (i > 1) {
erroraddress = erroraddress =
((emif_regs->NANDERRADD2 >> ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
(16 * (i & 1))) & 0x3FF); (16 * (i & 1))) & 0x3FF);
erroraddress = ((512 + 7) - erroraddress); erroraddress = ((512 + 7) - erroraddress);
errorvalue = errorvalue =
((emif_regs->NANDERRVAL2 >> ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
(16 * (i & 1))) & 0xFF); (16 * (i & 1))) & 0xFF);
} else { } else {
erroraddress = erroraddress =
((emif_regs->NANDERRADD1 >> ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
(16 * (i & 1))) & 0x3FF); (16 * (i & 1))) & 0x3FF);
erroraddress = ((512 + 7) - erroraddress); erroraddress = ((512 + 7) - erroraddress);
errorvalue = errorvalue =
((emif_regs->NANDERRVAL1 >> ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
(16 * (i & 1))) & 0xFF); (16 * (i & 1))) & 0xFF);
} }
/* xor the corrupt data with error value */ /* xor the corrupt data with error value */
@ -540,7 +549,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
static int nand_davinci_dev_ready(struct mtd_info *mtd) static int nand_davinci_dev_ready(struct mtd_info *mtd)
{ {
return emif_regs->NANDFSR & 0x1; return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
} }
static void nand_flash_init(void) static void nand_flash_init(void)
@ -573,9 +582,10 @@ static void nand_flash_init(void)
| (0 << 0) /* asyncSize 8-bit bus */ | (0 << 0) /* asyncSize 8-bit bus */
; ;
emif_regs->AB1CR = acfg1; /* CS2 */ __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */ /* NAND flash on CS2 */
__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif #endif
} }

77
include/asm-arm/arch-davinci/emif_defs.h
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@ -24,47 +24,42 @@
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
typedef struct davinci_emif_regs { struct davinci_emif_regs {
dv_reg ERCSR; u_int32_t ercsr;
dv_reg AWCCR; u_int32_t awccr;
dv_reg SDBCR; u_int32_t sdbcr;
dv_reg SDRCR; u_int32_t sdrcr;
dv_reg AB1CR; u_int32_t ab1cr;
dv_reg AB2CR; u_int32_t ab2cr;
dv_reg AB3CR; u_int32_t ab3cr;
dv_reg AB4CR; u_int32_t ab4cr;
dv_reg SDTIMR; u_int32_t sdtimr;
dv_reg DDRSR; u_int32_t ddrsr;
dv_reg DDRPHYCR; u_int32_t ddrphycr;
dv_reg DDRPHYSR; u_int32_t ddrphysr;
dv_reg TOTAR; u_int32_t totar;
dv_reg TOTACTR; u_int32_t totactr;
dv_reg DDRPHYID_REV; u_int32_t ddrphyid_rev;
dv_reg SDSRETR; u_int32_t sdsretr;
dv_reg EIRR; u_int32_t eirr;
dv_reg EIMR; u_int32_t eimr;
dv_reg EIMSR; u_int32_t eimsr;
dv_reg EIMCR; u_int32_t eimcr;
dv_reg IOCTRLR; u_int32_t ioctrlr;
dv_reg IOSTATR; u_int32_t iostatr;
u_int8_t RSVD0[8]; u_int8_t rsvd0[8];
dv_reg NANDFCR; u_int32_t nandfcr;
dv_reg NANDFSR; u_int32_t nandfsr;
u_int8_t RSVD1[8]; u_int8_t rsvd1[8];
dv_reg NANDFECC[4]; u_int32_t nandfecc[4];
u_int8_t RSVD2[60]; u_int8_t rsvd2[60];
dv_reg NAND4BITECCLOAD; u_int32_t nand4biteccload;
dv_reg NAND4BITECC1; u_int32_t nand4bitecc[4];
dv_reg NAND4BITECC2; u_int32_t nanderradd1;
dv_reg NAND4BITECC3; u_int32_t nanderradd2;
dv_reg NAND4BITECC4; u_int32_t nanderrval1;
dv_reg NANDERRADD1; u_int32_t nanderrval2;
dv_reg NANDERRADD2; };
dv_reg NANDERRVAL1;
dv_reg NANDERRVAL2;
} emif_registers;
typedef emif_registers *emifregs;
#define davinci_emif_regs \ #define davinci_emif_regs \
((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)