x86: sound: Add support for broadwell I2S
I2S is used to send digital audio data to an audio codec. Add support for this on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
3f3411ebf8
commit
cbdfe59918
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@ -17,4 +17,5 @@ obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
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obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o
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obj-$(CONFIG_SOUND_INTEL_HDA) += hda_codec.o
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obj-$(CONFIG_SOUND_I8254) += i8254_beep.o
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obj-$(CONFIG_INTEL_BROADWELL) += broadwell_i2s.o
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obj-$(CONFIG_SOUND_IVYBRIDGE) += ivybridge_sound.o
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@ -0,0 +1,306 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Intel Broadwell I2S driver
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*
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* Copyright 2019 Google LLC
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*
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* Modified from dc i2s/broadwell/broadwell.c
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*/
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#define LOG_CATEGORY UCLASS_I2S
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#include <common.h>
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#include <dm.h>
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#include <i2s.h>
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#include <asm/io.h>
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#include "broadwell_i2s.h"
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enum {
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BDW_SHIM_START_ADDRESS = 0xfb000,
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BDW_SSP0_START_ADDRESS = 0xfc000,
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BDW_SSP1_START_ADDRESS = 0xfd000,
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};
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struct broadwell_i2s_priv {
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enum frame_sync_rel_timing_t rel_timing;
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enum frame_sync_pol_t sfrm_polarity;
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enum end_transfer_state_t end_transfer_state;
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enum clock_mode_t sclk_mode;
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uint sclk_dummy_stop; /* 0-31 */
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uint sclk_frame_width; /* 1-38 */
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struct i2s_shim_regs *shim;
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struct broadwell_i2s_regs *regs;
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};
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static void init_shim_csr(struct broadwell_i2s_priv *priv)
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{
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/*
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* Select SSP clock
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* Turn off low power clock
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* Set PIO mode
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* Stall DSP core
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*/
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clrsetbits_le32(&priv->shim->csr,
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SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK,
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SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ |
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SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 |
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SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL |
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SHIM_CS_DCS_DSP32_AF32);
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}
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static void init_shim_clkctl(struct i2s_uc_priv *uc_priv,
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struct broadwell_i2s_priv *priv)
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{
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u32 clkctl = readl(&priv->shim->clkctl);
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/* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */
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clkctl &= SHIM_CLKCTL_RESERVED;
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clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG;
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/* Enable requested SSP interface */
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if (uc_priv->id)
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clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD;
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else
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clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD;
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writel(clkctl, &priv->shim->clkctl);
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}
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static void init_sscr0(struct i2s_uc_priv *uc_priv,
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struct broadwell_i2s_priv *priv)
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{
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u32 sscr0;
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uint scale;
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/* Set data size based on BPS */
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if (uc_priv->bitspersample > 16)
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sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT
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| SSP_SSC0_EDSS;
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else
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sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT;
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/* Set network mode, Stereo PSP frame format */
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sscr0 |= SSP_SSC0_MODE_NETWORK |
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SSP_SSC0_FRDC_STEREO |
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SSP_SSC0_FRF_PSP |
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SSP_SSC0_TIM |
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SSP_SSC0_RIM |
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SSP_SSC0_ECS_PCH |
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SSP_SSC0_NCS_PCH |
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SSP_SSC0_ACS_PCH;
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/* Scale 24MHz MCLK */
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scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs;
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sscr0 |= scale << SSP_SSC0_SCR_SHIFT;
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writel(sscr0, &priv->regs->sscr0);
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}
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static void init_sscr1(struct broadwell_i2s_priv *priv)
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{
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u32 sscr1 = readl(&priv->regs->sscr1);
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sscr1 &= SSP_SSC1_RESERVED;
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/* Set as I2S master */
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sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER;
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/* Enable TXD tristate behavior for PCH */
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sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE;
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/* Disable DMA Tx/Rx service request */
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sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE;
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/* Clock on during transfer */
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sscr1 |= SSP_SSC1_SCFR;
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/* Set FIFO thresholds */
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sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT;
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sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT;
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/* Disable interrupts */
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sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE);
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sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT);
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writel(sscr1, &priv->regs->sscr1);
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}
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static void init_sspsp(struct broadwell_i2s_priv *priv)
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{
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u32 sspsp = readl(&priv->regs->sspsp);
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sspsp &= SSP_PSP_RESERVED;
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sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT;
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sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) &
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SSP_PSP_DMYSTOP_MASK;
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sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) &
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SSP_PSP_EDMYSTOP_MASK;
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sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT;
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/* Frame Sync Relative Timing */
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if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4)
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sspsp |= SSP_PSP_FSRT;
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else
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sspsp &= ~SSP_PSP_FSRT;
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/* Serial Frame Polarity */
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if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH)
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sspsp |= SSP_PSP_SFRMP;
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else
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sspsp &= ~SSP_PSP_SFRMP;
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/* End Data Transfer State */
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if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW)
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sspsp &= ~SSP_PSP_ETDS;
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else
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sspsp |= SSP_PSP_ETDS;
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writel(sspsp, &priv->regs->sspsp);
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}
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static void init_ssp_time_slot(struct broadwell_i2s_priv *priv)
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{
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writel(3, &priv->regs->sstsa);
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writel(3, &priv->regs->ssrsa);
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}
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static int bdw_i2s_init(struct udevice *dev)
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{
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struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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init_shim_csr(priv);
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init_shim_clkctl(uc_priv, priv);
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init_sscr0(uc_priv, priv);
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init_sscr1(priv);
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init_sspsp(priv);
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init_ssp_time_slot(priv);
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return 0;
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}
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static void bdw_i2s_enable(struct broadwell_i2s_priv *priv)
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{
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setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE);
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setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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}
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static void bdw_i2s_disable(struct broadwell_i2s_priv *priv)
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{
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clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
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}
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static int broadwell_i2s_tx_data(struct udevice *dev, void *data,
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uint data_size)
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{
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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u32 *ptr = data;
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log_debug("data=%p, data_size=%x\n", data, data_size);
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if (data_size < SSP_FIFO_SIZE) {
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log_err("Invalid I2S data size\n");
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return -ENODATA;
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}
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/* Enable I2S interface */
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bdw_i2s_enable(priv);
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/* Transfer data */
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while (data_size > 0) {
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ulong start = timer_get_us() + 100000;
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/* Write data if transmit FIFO has room */
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if (readl(&priv->regs->sssr) & SSP_SSS_TNF) {
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writel(*ptr++, &priv->regs->ssdr);
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data_size -= sizeof(*ptr);
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} else {
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if ((long)(timer_get_us() - start) > 0) {
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/* Disable I2S interface */
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bdw_i2s_disable(priv);
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log_debug("I2S Transfer Timeout\n");
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return -ETIMEDOUT;
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}
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}
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}
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/* Disable I2S interface */
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bdw_i2s_disable(priv);
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log_debug("done\n");
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return 0;
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}
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static int broadwell_i2s_probe(struct udevice *dev)
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{
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struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
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struct broadwell_i2s_priv *priv = dev_get_priv(dev);
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struct udevice *adsp = dev_get_parent(dev);
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u32 bar0, offset;
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int ret;
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bar0 = dm_pci_read_bar32(adsp, 0);
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if (!bar0) {
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log_debug("Cannot read adsp bar0\n");
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return -EINVAL;
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}
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offset = dev_read_addr_index(dev, 0);
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if (offset == FDT_ADDR_T_NONE) {
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log_debug("Cannot read address index 0\n");
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return -EINVAL;
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}
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uc_priv->base_address = bar0 + offset;
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/*
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* Hard-code these values. If other settings are required we can add
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* this to the device tree.
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*/
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uc_priv->rfs = 64;
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uc_priv->bfs = 32;
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uc_priv->audio_pll_clk = 24 * 1000 * 1000;
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uc_priv->samplingrate = 48000;
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uc_priv->bitspersample = 16;
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uc_priv->channels = 2;
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uc_priv->id = 0;
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priv->shim = (struct i2s_shim_regs *)uc_priv->base_address;
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priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW;
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priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW;
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priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL;
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priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM;
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priv->sclk_dummy_stop = 0;
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priv->sclk_frame_width = 31;
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offset = dev_read_addr_index(dev, 1 + uc_priv->id);
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if (offset == FDT_ADDR_T_NONE) {
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log_debug("Cannot read address index %d\n", 1 + uc_priv->id);
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return -EINVAL;
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}
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log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0,
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uc_priv->base_address, offset);
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priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset);
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ret = bdw_i2s_init(dev);
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if (ret)
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return ret;
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return 0;
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}
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static const struct i2s_ops broadwell_i2s_ops = {
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.tx_data = broadwell_i2s_tx_data,
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};
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static const struct udevice_id broadwell_i2s_ids[] = {
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{ .compatible = "intel,broadwell-i2s" },
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{ }
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};
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U_BOOT_DRIVER(broadwell_i2s) = {
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.name = "broadwell_i2s",
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.id = UCLASS_I2S,
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.of_match = broadwell_i2s_ids,
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.probe = broadwell_i2s_probe,
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.ops = &broadwell_i2s_ops,
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.priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
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};
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@ -0,0 +1,301 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Intel Broadwell I2S driver
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*
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* Copyright 2019 Google LLC
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*
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* Modified from dc i2s/broadwell/broadwell.h
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*/
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#ifndef __BROADWELL_I2S_H__
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#define __BROADWELL_I2S_H__
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enum {
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SSP_FIFO_SIZE = 7,
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};
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enum frame_sync_rel_timing_t {
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NEXT_FRMS_AFTER_END_OF_T4 = 0,
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NEXT_FRMS_WITH_LSB_PREVIOUS_FRM,
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};
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enum frame_sync_pol_t {
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SSP_FRMS_ACTIVE_LOW = 0,
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SSP_FRMS_ACTIVE_HIGH,
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};
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enum end_transfer_state_t {
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SSP_END_TRANSFER_STATE_LOW = 0,
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SSP_END_TRANSFER_STATE_PEVIOUS_BIT,
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};
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enum clock_mode_t {
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/* Data driven (falling), data sampled (rising), idle state (low) */
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SCLK_MODE_DDF_DSR_ISL,
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/* Data driven (rising), data sampled (falling), idle state (low) */
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SCLK_MODE_DDR_DSF_ISL,
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/* Data driven (rising), data sampled (falling), idle state (high) */
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SCLK_MODE_DDR_DSF_ISH,
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/* Data driven (falling), data sampled (rising), idle state (high) */
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SCLK_MODE_DDF_DSR_ISH,
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};
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struct i2s_shim_regs {
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u32 csr; /* 0x00 */
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u32 reserved0[29]; /* 0x14 - 0x77 */
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u32 clkctl; /* 0x78 */
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u32 reserved1; /* 0x7c */
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u32 cs2; /* 0x80 */
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};
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struct broadwell_i2s_regs {
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u32 sscr0; /* 0x00 */
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u32 sscr1; /* 0x04 */
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u32 sssr; /* 0x08 */
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u32 ssitr; /* 0x0c */
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u32 ssdr; /* 0x10 */
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u32 reserved0[5]; /* 0x14 - 0x27 */
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u32 ssto; /* 0x28 */
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u32 sspsp; /* 0x2c */
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u32 sstsa; /* 0x30 */
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u32 ssrsa; /* 0x34 */
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u32 sstss; /* 0x38 */
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u32 sscr2; /* 0x40 */
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u32 sspsp2; /* 0x44 */
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};
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/* SHIM Configuration & Status */
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enum {
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/* Low Power Clock Select */
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SHIM_CS_LPCS = 1 << 31,
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/* SSP Force Clock Running */
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SHIM_CS_SFCR_SSP1 = 1 << 28,
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SHIM_CS_SFCR_SSP0 = 1 << 27,
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/* SSP1 IO Clock Select */
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SHIM_CS_S1IOCS = 1 << 23,
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/* SSP0 IO Clock Select */
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SHIM_CS_S0IOCS = 1 << 21,
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/* Parity Check Enable */
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SHIM_CS_PCE = 1 << 15,
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/* SSP DMA or PIO Mode */
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SHIM_CS_SDPM_PIO_SSP1 = 1 << 12,
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SHIM_CS_SDPM_DMA_SSP1 = 0 << 12,
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SHIM_CS_SDPM_PIO_SSP0 = 1 << 11,
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SHIM_CS_SDPM_DMA_SSP0 = 0 << 11,
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/* Run / Stall */
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SHIM_CS_STALL = 1 << 10,
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/* DSP Clock Select */
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SHIM_CS_DCS_DSP320_AF80 = 0 << 4,
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SHIM_CS_DCS_DSP160_AF80 = 1 << 4,
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SHIM_CS_DCS_DSP80_AF80 = 2 << 4,
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SHIM_CS_DCS_DSP320_AF160 = 4 << 4,
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SHIM_CS_DCS_DSP160_AF160 = 5 << 4,
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SHIM_CS_DCS_DSP32_AF32 = 6 << 4,
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SHIM_CS_DCS_MASK = 7 << 4,
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/* SSP Base Clock Select */
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SHIM_CS_SBCS_SSP0_24MHZ = 1 << 3,
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SHIM_CS_SBCS_SSP0_32MHZ = 0 << 3,
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SHIM_CS_SBCS_SSP1_24MHZ = 1 << 2,
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SHIM_CS_SBCS_SSP1_32MHZ = 0 << 2,
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/* DSP Core Reset */
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SHIM_CS_RST = 1 << 1,
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};
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/* SHIM Clock Control */
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enum {
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/* Clock Frequency Change In Progress */
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SHIM_CLKCTL_CFCIP = 1 << 31,
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/* SSP MCLK Output Select */
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SHIM_CLKCTL_MCLK_MASK = 0x3,
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SHIM_CLKCTL_MCLK_SHIFT = 24,
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SHIM_CLKCTL_MCLK_DISABLED = 0 << 24,
|
||||
SHIM_CLKCTL_MCLK_6MHZ = 1 << 24,
|
||||
SHIM_CLKCTL_MCLK_12MHZ = 2 << 24,
|
||||
SHIM_CLKCTL_MCLK_24MHZ = 3 << 24,
|
||||
/* DSP Core Prevent Local Clock Gating */
|
||||
SHIM_CLKCTL_DCPLCG = 1 << 18,
|
||||
/* SSP Clock Output Enable */
|
||||
SHIM_CLKCTL_SCOE_SSP1 = 1 << 17,
|
||||
SHIM_CLKCTL_SCOE_SSP0 = 1 << 16,
|
||||
/* DMA Engine Force Local Clock Gating */
|
||||
SHIM_CLKCTL_DEFLCGB_DMA1_CGE = 0 << 6,
|
||||
SHIM_CLKCTL_DEFLCGB_DMA1_CGD = 1 << 6,
|
||||
SHIM_CLKCTL_DEFLCGB_DMA0_CGE = 0 << 5,
|
||||
SHIM_CLKCTL_DEFLCGB_DMA0_CGD = 1 << 5,
|
||||
/* SSP Force Local Clock Gating */
|
||||
SHIM_CLKCTL_SFLCGB_SSP1_CGE = 0 << 1,
|
||||
SHIM_CLKCTL_SFLCGB_SSP1_CGD = 1 << 1,
|
||||
SHIM_CLKCTL_SFLCGB_SSP0_CGE = 0 << 0,
|
||||
SHIM_CLKCTL_SFLCGB_SSP0_CGD = 1 << 0,
|
||||
|
||||
/* Reserved bits: 30:26, 23:19, 15:7, 4:2 */
|
||||
SHIM_CLKCTL_RESERVED = 0x1f << 26 | 0x1f << 19 | 0x1ff << 7 | 0x7 << 2,
|
||||
};
|
||||
|
||||
/* SSP Status */
|
||||
enum {
|
||||
/* Bit Count Error */
|
||||
SSP_SSS_BCE = 1 << 23,
|
||||
/* Clock Sync Statu s*/
|
||||
SSP_SSS_CSS = 1 << 22,
|
||||
/* Transmit FIFO Underrun */
|
||||
SSP_SSS_TUR = 1 << 21,
|
||||
/* End Of Chain */
|
||||
SSP_SSS_EOC = 1 << 20,
|
||||
/* Receiver Time-out Interrupt */
|
||||
SSP_SSS_TINT = 1 << 19,
|
||||
/* Peripheral Trailing Byte Interrupt */
|
||||
SSP_SSS_PINT = 1 << 18,
|
||||
/* Received FIFO Level */
|
||||
SSP_RFL_MASK = 0xf,
|
||||
SSP_RFL_SHIFT = 12,
|
||||
/* Transmit FIFO Level */
|
||||
SSP_TFL_MASK = 0xf,
|
||||
SSP_TFL_SHIFT = 8,
|
||||
/* Receive FIFO Overrun */
|
||||
SSP_SSS_ROR = 1 << 7,
|
||||
/* Receive FIFO Service Request */
|
||||
SSP_SSS_RFS = 1 << 6,
|
||||
/* Transmit FIFO Service Request */
|
||||
SSP_SSS_TFS = 1 << 5,
|
||||
/* SSP Busy */
|
||||
SSP_SSS_BSY = 1 << 4,
|
||||
/* Receive FIFO Not Empty */
|
||||
SSP_SSS_RNE = 1 << 3,
|
||||
/* Transmit FIFO Not Full */
|
||||
SSP_SSS_TNF = 1 << 2,
|
||||
};
|
||||
|
||||
/* SSP Control 0 */
|
||||
enum {
|
||||
/* Mode */
|
||||
SSP_SSC0_MODE_NORMAL = 0 << 31,
|
||||
SSP_SSC0_MODE_NETWORK = 1 << 31,
|
||||
/* Audio Clock Select */
|
||||
SSP_SSC0_ACS_PCH = 0 << 30,
|
||||
/* Frame Rate Divider Control (0-7) */
|
||||
SSP_SSC0_FRDC_MASK = 0x7,
|
||||
SSP_SSC0_FRDC_SHIFT = 24,
|
||||
SSP_SSC0_FRDC_STEREO = 1 << 24,
|
||||
/* Transmit FIFO Underrun Interrupt Mask */
|
||||
SSP_SSC0_TIM = 1 << 23,
|
||||
/* Receive FIFO Underrun Interrupt Mask */
|
||||
SSP_SSC0_RIM = 1 << 22,
|
||||
/* Network Clock Select */
|
||||
SSP_SSC0_NCS_PCH = 0 << 21,
|
||||
/* Extended Data Size Select */
|
||||
SSP_SSC0_EDSS = 1 << 20,
|
||||
/* Serial Clock Rate (0-4095) */
|
||||
SSP_SSC0_SCR_SHIFT = 8,
|
||||
SSP_SSC0_SCR_MASK = 0xfff << SSP_SSC0_SCR_SHIFT,
|
||||
/* Synchronous Serial Port Enable */
|
||||
SSP_SSC0_SSE = 1 << 7,
|
||||
/* External Clock Select */
|
||||
SSP_SSC0_ECS_PCH = 0 << 6,
|
||||
/* Frame Format */
|
||||
SSP_SSC0_FRF_MOTOROLA_SPI = 0 << 4,
|
||||
SSP_SSC0_FRF_TI_SSP = 1 << 4,
|
||||
SSP_SSC0_FRF_NS_MICROWIRE = 2 << 4,
|
||||
SSP_SSC0_FRF_PSP = 3 << 4,
|
||||
/* Data Size Select */
|
||||
SSP_SSC0_DSS_SHIFT = 0,
|
||||
SSP_SSC0_DSS_MASK = 0xf << SSP_SSC0_DSS_SHIFT,
|
||||
};
|
||||
|
||||
/* SSP Control 1 */
|
||||
enum {
|
||||
/* TXD Tristate Enable on Last Phase */
|
||||
SSP_SSC1_TTELP = 1 << 31,
|
||||
/* TXD Tristate Enable */
|
||||
SSP_SSC1_TTE = 1 << 30,
|
||||
/* Enable Bit Count Error Interrupt */
|
||||
SSP_SSC1_EBCEI = 1 << 29,
|
||||
/* Slave Clock Running */
|
||||
SSP_SSC1_SCFR = 1 << 28,
|
||||
/* Enable Clock Request A */
|
||||
SSP_SSC1_ECRA = 1 << 27,
|
||||
/* Enable Clock Request B */
|
||||
SSP_SSC1_ECRB = 1 << 26,
|
||||
/* SSPCLK Direction */
|
||||
SSP_SSC1_SCLKDIR_SLAVE = 1 << 25,
|
||||
SSP_SSC1_SCLKDIR_MASTER = 0 << 25,
|
||||
/* SSPFRM Direction */
|
||||
SSP_SSC1_SFRMDIR_SLAVE = 1 << 24,
|
||||
SSP_SSC1_SFRMDIR_MASTER = 0 << 24,
|
||||
/* Receive without Transmit */
|
||||
SSP_SSC1_RWOT = 1 << 23,
|
||||
/* Trailing Byte */
|
||||
SSP_SSC1_TRAIL = 1 << 22,
|
||||
/* DMA Tx Service Request Enable */
|
||||
SSP_SSC1_TSRE = 1 << 21,
|
||||
/* DMA Rx Service Request Enable */
|
||||
SSP_SSC1_RSRE = 1 << 20,
|
||||
/* Receiver Timeout Interrupt Enable */
|
||||
SSP_SSC1_TINTE = 1 << 19,
|
||||
/* Periph. Trailing Byte Int. Enable */
|
||||
SSP_SSC1_PINTE = 1 << 18,
|
||||
/* Invert Frame Signal */
|
||||
SSP_SSC1_IFS = 1 << 16,
|
||||
/* Select FIFO for EFWR: test mode */
|
||||
SSP_SSC1_STRF = 1 << 15,
|
||||
/* Enable FIFO Write/Read: test mode */
|
||||
SSP_SSC1_EFWR = 1 << 14,
|
||||
/* Receive FIFO Trigger Threshold */
|
||||
SSP_SSC1_RFT_SHIFT = 10,
|
||||
SSP_SSC1_RFT_MASK = 0xf << SSP_SSC1_RFT_SHIFT,
|
||||
/* Transmit FIFO Trigger Threshold */
|
||||
SSP_SSC1_TFT_SHIFT = 6,
|
||||
SSP_SSC1_TFT_MASK = 0xf << SSP_SSC1_TFT_SHIFT,
|
||||
/* Microwire Transmit Data Size */
|
||||
SSP_SSC1_MWDS = 1 << 5,
|
||||
/* Motorola SPI SSPSCLK Phase Setting*/
|
||||
SSP_SSC1_SPH = 1 << 4,
|
||||
/* Motorola SPI SSPSCLK Polarity */
|
||||
SSP_SSC1_SPO = 1 << 3,
|
||||
/* Loopback mode: test mode */
|
||||
SSP_SSC1_LBM = 1 << 2,
|
||||
/* Transmit FIFO Interrupt Enable */
|
||||
SSP_SSC1_TIE = 1 << 1,
|
||||
/* Receive FIFO Interrupt Enable */
|
||||
SSP_SSC1_RIE = 1 << 0,
|
||||
|
||||
SSP_SSC1_RESERVED = 17 << 1,
|
||||
};
|
||||
|
||||
/* SSP Programmable Serial Protocol */
|
||||
enum {
|
||||
/* Extended Dummy Stop (0-31) */
|
||||
SSP_PSP_EDYMSTOP_SHIFT = 26,
|
||||
SSP_PSP_EDMYSTOP_MASK = 0x7 << SSP_PSP_EDYMSTOP_SHIFT,
|
||||
/* Frame Sync Relative Timing */
|
||||
SSP_PSP_FSRT = 1 << 25,
|
||||
/* Dummy Stop low bits */
|
||||
SSP_PSP_DMYSTOP_SHIFT = 23,
|
||||
SSP_PSP_DMYSTOP_MASK = 0x3 << SSP_PSP_DMYSTOP_SHIFT,
|
||||
/* Serial Frame Width */
|
||||
SSP_PSP_SFRMWDTH_SHIFT = 16,
|
||||
SSP_PSP_SFRMWDTH_MASK = 0x3f << SSP_PSP_SFRMWDTH_SHIFT,
|
||||
/* Serial Frame Delay */
|
||||
SSP_PSP_SFRMDLY_MASK = 0x7f,
|
||||
SSP_PSP_SFRMDLY_SHIFT = 9,
|
||||
/* Start Delay */
|
||||
SSP_PSP_STRTDLY_MASK = 0x7,
|
||||
SSP_PSP_STRTDLY_SHIFT = 4,
|
||||
/* End of Transfer Data State */
|
||||
SSP_PSP_ETDS = 1 << 3,
|
||||
/* Serial Frame Polarity */
|
||||
SSP_PSP_SFRMP = 1 << 2,
|
||||
/* Serial Clock Mode */
|
||||
SSP_PSP_SCMODE_SHIFT = 0,
|
||||
SSP_PSP_SCMODE_MASK = 0x3 << SSP_PSP_SCMODE_SHIFT,
|
||||
|
||||
SSP_PSP_RESERVED = 1 << 22,
|
||||
};
|
||||
|
||||
/* SSP TX Time Slot Active */
|
||||
enum {
|
||||
SSP_SSTSA_EN = 1 << 8,
|
||||
SSP_SSTSA_MASK = 0xff,
|
||||
};
|
||||
|
||||
#endif /* __BROADWELL_I2S_H__ */
|
||||
Loading…
Reference in New Issue