arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Ryder Lee
Tom Rini
parent
d84982dbfa
commit
cbd2fba1ec
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@ -664,6 +664,20 @@ config ARCH_MESON
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targeted at media players and tablet computers. We currently
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support the S905 (GXBaby) 64-bit SoC.
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config ARCH_MEDIATEK
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bool "MediaTek SoCs"
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select BINMAN
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select DM
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select OF_CONTROL
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select SPL_DM if SPL
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select SPL_LIBCOMMON_SUPPORT if SPL
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select SPL_LIBGENERIC_SUPPORT if SPL
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select SPL_OF_CONTROL if SPL
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select SUPPORT_SPL
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help
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Support for the MediaTek SoCs family developed by MediaTek Inc.
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Please refer to doc/README.mediatek for more information.
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config ARCH_LPC32XX
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bool "NXP LPC32xx platform"
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select CPU_ARM926EJS
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@ -1449,6 +1463,8 @@ source "arch/arm/mach-rmobile/Kconfig"
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source "arch/arm/mach-meson/Kconfig"
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source "arch/arm/mach-mediatek/Kconfig"
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source "arch/arm/mach-qemu/Kconfig"
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source "arch/arm/mach-rockchip/Kconfig"
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@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3
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machine-$(CONFIG_ARCH_KEYSTONE) += keystone
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# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
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machine-$(CONFIG_KIRKWOOD) += kirkwood
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#ifndef __MEDIATEK_MISC_H_
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#define __MEDIATEK_MISC_H_
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#define VER_BASE 0x08000000
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#define VER_SIZE 0x10
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#define APHW_CODE 0x00
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#define APHW_SUBCODE 0x04
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#define APHW_VER 0x08
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#define APSW_VER 0x0c
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#endif /* __MEDIATEK_MISC_H_ */
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@ -0,0 +1,26 @@
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if ARCH_MEDIATEK
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config SYS_SOC
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default "mediatek"
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config SYS_VENDOR
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default "mediatek"
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choice
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prompt "MediaTek board select"
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config TARGET_MT7629
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bool "MediaTek MT7629 SoC"
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select CPU_V7A
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select SPL
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select ARCH_MISC_INIT
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help
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The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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endchoice
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source "board/mediatek/mt7629/Kconfig"
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endif
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <dm/uclass-internal.h>
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int arch_misc_init(void)
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{
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struct udevice *wdt;
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int ret;
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ret = uclass_first_device_err(UCLASS_WDT, &wdt);
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if (!ret)
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wdt_stop(wdt);
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return 0;
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}
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int arch_cpu_init(void)
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{
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icache_enable();
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return 0;
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}
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#ifndef __MEDIATEK_INIT_H_
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#define __MEDIATEK_INIT_H_
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extern int mtk_soc_early_init(void);
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#endif /* __MEDIATEK_INIT_H_ */
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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obj-y += lowlevel_init.o
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@ -0,0 +1,128 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <linux/io.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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#define L2_CFG_BASE 0x10200000
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#define L2_CFG_SIZE 0x1000
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#define L2_SHARE_CFG_MP0 0x7f0
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#define L2_SHARE_MODE_OFF BIT(8)
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DECLARE_GLOBAL_DATA_PTR;
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int mtk_pll_early_init(void)
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{
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unsigned long pll_rates[] = {
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[CLK_APMIXED_ARMPLL] = 1250000000,
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[CLK_APMIXED_MAINPLL] = 1120000000,
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[CLK_APMIXED_UNIV2PLL] = 1200000000,
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[CLK_APMIXED_ETH1PLL] = 500000000,
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[CLK_APMIXED_ETH2PLL] = 700000000,
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[CLK_APMIXED_SGMIPLL] = 650000000,
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};
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struct udevice *dev;
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
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if (ret)
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return ret;
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/* configure default rate then enable apmixedsys */
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for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
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struct clk clk = { .id = i, .dev = dev };
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ret = clk_set_rate(&clk, pll_rates[i]);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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/* setup mcu bus */
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ret = uclass_get_device_by_driver(UCLASS_SYSCON,
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DM_GET_DRIVER(mtk_mcucfg), &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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struct udevice *dev;
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int ret;
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/* initialize early clocks */
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ret = mtk_pll_early_init();
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if (ret)
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return ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mach_cpu_init(void)
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{
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void __iomem *base;
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base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
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/* disable L2C shared mode */
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writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
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return 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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ret = ram_get_info(dev, &ram);
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if (ret)
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return ret;
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debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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int print_cpuinfo(void)
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{
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void __iomem *chipid;
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u32 hwcode, swver;
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chipid = ioremap(VER_BASE, VER_SIZE);
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hwcode = readl(chipid + APHW_CODE);
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swver = readl(chipid + APSW_VER);
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printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
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return 0;
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}
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@ -0,0 +1,50 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <linux/linkage.h>
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ENTRY(lowlevel_init)
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#ifndef CONFIG_SPL_BUILD
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/* Return to U-Boot via saved link register */
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mov pc, lr
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#else
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/*
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* Arch timer :
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* set CNTFRQ = 20Mhz, set CNTVOFF = 0
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*/
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movw r0, #0x2d00
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movt r0, #0x131
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mcr p15, 0, r0, c14, c0, 0
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/* enable SMP bit */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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/* if MP core, handle secondary cores */
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mrc p15, 0, r0, c0, c0, 5
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ands r1, r0, #0x40000000
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bne go @ Go if UP
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ands r0, r0, #0x0f
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beq go @ Go if core0 on primary core tile
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b secondary
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go:
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/* master CPU */
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mov pc, lr
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secondary:
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/* read slave CPU number into r0 firstly */
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0x0f
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loop:
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dsb
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isb
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wfi @Zzz...
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b loop
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#endif
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ENDPROC(lowlevel_init)
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <spl.h>
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#include "init.h"
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret)
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hang();
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/* enable console uart printing */
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preloader_console_init();
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/* soc early initialization */
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ret = mtk_soc_early_init();
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if (ret)
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hang();
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}
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u32 spl_boot_device(void)
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{
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#if defined(CONFIG_SPL_SPI_SUPPORT)
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return BOOT_DEVICE_SPI;
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#elif defined(CONFIG_SPL_MMC_SUPPORT)
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return BOOT_DEVICE_MMC1;
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#elif defined(CONFIG_SPL_NAND_SUPPORT)
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return BOOT_DEVICE_NAND;
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#elif defined(CONFIG_SPL_NOR_SUPPORT)
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return BOOT_DEVICE_NOR;
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#else
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return BOOT_DEVICE_NONE;
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#endif
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}
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@ -0,0 +1,17 @@
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if TARGET_MT7629
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config SYS_BOARD
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default "mt7629"
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config SYS_CONFIG_NAME
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default "mt7629"
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config MTK_SPL_PAD_SIZE
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hex
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default 0x10000
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config MTK_BROM_HEADER_INFO
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string
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default "media=nor"
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endif
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@ -0,0 +1,7 @@
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MT7629
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M: Ryder Lee <ryder.lee@mediatek.com>
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M: Weijie Gao <weijie.gao@mediatek.com>
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S: Maintained
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F: board/mediatek/mt7629
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F: include/configs/mt7629.h
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F: configs/mt7629_rfb_defconfig
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += mt7629_rfb.o
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@ -0,0 +1,16 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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@ -0,0 +1,73 @@
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CONFIG_ARM=y
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CONFIG_SYS_THUMB_BUILD=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_SYS_TEXT_BASE=0x41e00000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_TARGET_MT7629=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_BOOTDELAY=3
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_DEFAULT_FDT_FILE="mt7629-rfb"
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_NOR_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="U-Boot> "
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CONFIG_CMD_BOOTMENU=y
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SF_TEST=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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# CONFIG_PARTITIONS is not set
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CONFIG_OF_EMBED=y
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CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb"
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents"
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_PINCTRL_MT7629=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_MTK_POWER_DOMAIN=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DM_SERIAL=y
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CONFIG_MTK_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_MTK_QSPI=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_WATCHDOG=y
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CONFIG_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_MTK_TIMER=y
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CONFIG_WDT_MTK=y
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CONFIG_LZMA=y
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# CONFIG_EFI_LOADER is not set
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@ -0,0 +1,57 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Configuration for MediaTek MT7629 SoC
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*
|
||||
* Copyright (C) 2018 MediaTek Inc.
|
||||
* Author: Ryder Lee <ryder.lee@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __MT7629_H
|
||||
#define __MT7629_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 8
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_64M
|
||||
#define CONFIG_SYS_CBSIZE SZ_1K
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_4M
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_SIZE SZ_4K
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_STACK 0x106000
|
||||
#define CONFIG_SPL_TEXT_BASE 0x201000
|
||||
#define CONFIG_SPL_MAX_SIZE SZ_64K
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K
|
||||
#define CONFIG_SPL_PAD_TO 0x10000
|
||||
|
||||
#define CONFIG_SPI_ADDR 0x30000000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
|
||||
|
||||
/* SPL -> Uboot */
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* UBoot -> Kernel */
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000
|
||||
#define CONFIG_LOADADDR 0x42007f1c
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* DRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue