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armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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#include <fsl_ddrc_version.h>
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#include <fsl_ddrc_version.h>
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#ifndef L1_CACHE_BYTES
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_SHIFT 6
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