mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Bin Meng
parent
e4f09f97c9
commit
c9cc37de2c
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@ -1001,4 +1001,12 @@ config PCIEX_LENGTH_128MB
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config PCIEX_LENGTH_64MB
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bool
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config INTEL_GMA_ACPI
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bool "Generate ACPI table for Intel GMA graphics"
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help
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The Intel GMA graphics driver in Linux expects an ACPI table
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which describes the layout of the registers and the display
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connected to the device. Enable this option to create this
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table so that graphics works correctly.
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endmenu
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@ -48,6 +48,7 @@ config INTEL_APOLLOLAKE
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imply CMD_CLK
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imply CLK_INTEL
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imply ACPI_GPE
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imply INTEL_GMA_ACPI
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if INTEL_APOLLOLAKE
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@ -9,6 +9,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
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obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
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endif
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
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endif
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ifdef CONFIG_INTEL_CAR_CQOS
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obj-$(CONFIG_TPL_BUILD) += car2.o
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ifndef CONFIG_SPL_BUILD
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168
arch/x86/cpu/intel_common/intel_opregion.c
Normal file
168
arch/x86/cpu/intel_common/intel_opregion.c
Normal file
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@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Writing IntelGraphicsMem table for ACPI
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*
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* Copyright 2019 Google LLC
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* Modified from coreboot src/soc/intel/gma/opregion.c
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*/
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#include <common.h>
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#include <binman.h>
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#include <bloblist.h>
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#include <dm.h>
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#include <spi_flash.h>
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#include <asm/intel_opregion.h>
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static char vbt_data[8 << 10];
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static int locate_vbt(char **vbtp, int *sizep)
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{
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struct binman_entry vbt;
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struct udevice *dev;
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u32 vbtsig = 0;
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int size;
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int ret;
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ret = binman_entry_find("intel-vbt", &vbt);
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if (ret)
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return log_msg_ret("find VBT", ret);
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ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
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if (ret)
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return log_msg_ret("find flash", ret);
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size = vbt.size;
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if (size > sizeof(vbt_data))
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return log_msg_ret("vbt", -E2BIG);
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ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
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if (ret)
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return log_msg_ret("read", ret);
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memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
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if (vbtsig != VBT_SIGNATURE) {
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log_err("Missing/invalid signature in VBT data file!\n");
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return -EINVAL;
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}
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log_info("Found a VBT of %u bytes\n", size);
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*sizep = size;
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*vbtp = vbt_data;
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return 0;
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}
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/* Write ASLS PCI register and prepare SWSCI register */
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static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
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{
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int sci_reg;
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if (!device_active(dev))
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return -ENOENT;
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/*
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* Intel BIOS Specification
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* Chapter 5.3.7 "Initialise Hardware State"
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*/
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dm_pci_write_config32(dev, ASLS, opregion);
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/*
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* Atom-based platforms use a combined SMI/SCI register,
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* whereas non-Atom platforms use a separate SCI register
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*/
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if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
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sci_reg = SWSMISCI;
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else
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sci_reg = SWSCI;
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/*
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* Intel's Windows driver relies on this:
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* Intel BIOS Specification
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* Chapter 5.4 "ASL Software SCI Handler"
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*/
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dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
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return 0;
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}
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int intel_gma_init_igd_opregion(struct udevice *dev,
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struct igd_opregion *opregion)
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{
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struct optionrom_vbt *vbt = NULL;
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char *vbt_buf;
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int vbt_size;
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int ret;
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ret = locate_vbt(&vbt_buf, &vbt_size);
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if (ret) {
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log_err("GMA: VBT couldn't be found\n");
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return log_msg_ret("find vbt", ret);
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}
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vbt = (struct optionrom_vbt *)vbt_buf;
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memset(opregion, '\0', sizeof(struct igd_opregion));
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(opregion->header.signature));
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
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ARRAY_SIZE(vbt->coreblock_biosbuild));
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/* Extended VBT support */
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if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
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struct optionrom_vbt *ext_vbt;
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ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT,
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vbt->hdr_vbt_size,
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(void **)&ext_vbt);
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if (ret) {
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log_err("GMA: Unable to add Ext VBT to bloblist\n");
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return log_msg_ret("blob", ret);
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}
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memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
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opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
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opregion->mailbox3.rvds = vbt->hdr_vbt_size;
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} else {
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/* Raw VBT size which can fit in gvd1 */
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printf("copy to %p\n", opregion->vbt.gvd1);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
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}
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/* 8kb */
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opregion->header.size = sizeof(struct igd_opregion) / 1024;
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/*
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* Left-shift version field to accommodate Intel Windows driver quirk
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* when not using a VBIOS.
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* Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
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*
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* No adverse effects when using VBIOS or booting Linux.
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*/
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opregion->header.version = IGD_OPREGION_VERSION << 24;
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/* We just assume we're mobile for now */
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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/* Initialise Mailbox 1 */
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opregion->mailbox1.clid = 1;
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/* Initialise Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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/* Write ASLS PCI register and prepare SWSCI register */
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ret = intel_gma_opregion_register(dev, (ulong)opregion);
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if (ret)
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return log_msg_ret("write asls", ret);
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return 0;
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}
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247
arch/x86/include/asm/intel_opregion.h
Normal file
247
arch/x86/include/asm/intel_opregion.h
Normal file
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@ -0,0 +1,247 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Writing IntelGraphicsMem table for ACPI
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*
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* Copyright 2019 Google LLC
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* Modified from coreboot src/soc/intel/gma/opregion.h
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*/
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#ifndef _ASM_INTEL_OPREGION_H_
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#define _ASM_INTEL_OPREGION_H_
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#define VBT_SIGNATURE 0x54425624
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/* IGD PCI Configuration register */
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#define ASLS 0xfc /* OpRegion Base */
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#define SWSCI 0xe8 /* SWSCI Register */
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#define SWSMISCI 0xe0 /* SWSMISCI Register */
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#define GSSCIE BIT(0) /* SCI Event trigger */
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#define SMISCISEL BIT(15) /* Select SMI or SCI event source */
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/* mailbox 0: header */
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struct __packed opregion_header {
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u8 signature[16]; /* Offset 0 OpRegion signature */
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u32 size; /* Offset 16 OpRegion size */
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u32 version; /* Offset 20 OpRegion structure version */
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u8 sbios_version[32]; /* Offset 24 System BIOS build version */
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u8 vbios_version[16]; /* Offset 56 Video BIOS build version */
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u8 driver_version[16]; /* Offset 72 Graphic drvr build version */
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u32 mailboxes; /* Offset 88 Mailboxes supported */
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u32 dmod; /* Offset 92 Driver Model */
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u32 pcon; /* Offset 96 Platform Capabilities */
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u16 dver[16]; /* Offset 100 GOP Version */
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u8 reserved[124]; /* Offset 132 Reserved */
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};
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#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
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#define IGD_OPREGION_VERSION 2
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#define IGD_MBOX1 BIT(0)
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#define IGD_MBOX2 BIT(1)
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#define IGD_MBOX3 BIT(2)
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#define IGD_MBOX4 BIT(3)
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#define IGD_MBOX5 BIT(4)
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#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
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IGD_MBOX4 | IGD_MBOX5)
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#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
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#define SBIOS_VERSION_SIZE 32
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/* mailbox 1: public ACPI methods */
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struct __packed opregion_mailbox1 {
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u32 drdy; /* Offset 0 Driver readiness */
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u32 csts; /* Offset 4 Status */
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u32 cevt; /* Offset 8 Current event */
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u8 reserved[20]; /* Offset 12 Reserved */
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u32 didl; /* Offset 32 Supported display device 1 */
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u32 ddl2; /* Offset 36 Supported display device 2 */
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u32 ddl3; /* Offset 40 Supported display device 3 */
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u32 ddl4; /* Offset 44 Supported display device 4 */
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u32 ddl5; /* Offset 48 Supported display device 5 */
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u32 ddl6; /* Offset 52 Supported display device 6 */
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u32 ddl7; /* Offset 56 Supported display device 7 */
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u32 ddl8; /* Offset 60 Supported display device 8 */
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u32 cpdl; /* Offset 64 Currently present display device 1 */
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u32 cpl2; /* Offset 68 Currently present display device 2 */
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u32 cpl3; /* Offset 72 Currently present display device 3 */
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u32 cpl4; /* Offset 76 Currently present display device 4 */
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u32 cpl5; /* Offset 80 Currently present display device 5 */
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u32 cpl6; /* Offset 84 Currently present display device 6 */
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u32 cpl7; /* Offset 88 Currently present display device 7 */
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u32 cpl8; /* Offset 92 Currently present display device 8 */
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u32 cadl; /* Offset 96 Currently active display device 1 */
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u32 cal2; /* Offset 100 Currently active display device 2 */
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u32 cal3; /* Offset 104 Currently active display device 3 */
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u32 cal4; /* Offset 108 Currently active display device 4 */
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u32 cal5; /* Offset 112 Currently active display device 5 */
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u32 cal6; /* Offset 116 Currently active display device 6 */
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u32 cal7; /* Offset 120 Currently active display device 7 */
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u32 cal8; /* Offset 124 Currently active display device 8 */
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u32 nadl; /* Offset 128 Next active device 1 */
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u32 ndl2; /* Offset 132 Next active device 2 */
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u32 ndl3; /* Offset 136 Next active device 3 */
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u32 ndl4; /* Offset 140 Next active device 4 */
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u32 ndl5; /* Offset 144 Next active device 5 */
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u32 ndl6; /* Offset 148 Next active device 6 */
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u32 ndl7; /* Offset 152 Next active device 7 */
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u32 ndl8; /* Offset 156 Next active device 8 */
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u32 aslp; /* Offset 160 ASL sleep timeout */
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u32 tidx; /* Offset 164 Toggle table index */
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u32 chpd; /* Offset 168 Current hot plug enable indicator */
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u32 clid; /* Offset 172 Current lid state indicator */
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u32 cdck; /* Offset 176 Current docking state indicator */
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u32 sxsw; /* Offset 180 Display Switch notification on Sx State
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* resume
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*/
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u32 evts; /* Offset 184 Events supported by ASL */
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u32 cnot; /* Offset 188 Current OS Notification */
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u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */
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u32 ddl9; /* Offset 196 Extended Supported display device 1 */
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u32 dd10; /* Offset 200 Extended Supported display device 2 */
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u32 dd11; /* Offset 204 Extended Supported display device 3 */
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u32 dd12; /* Offset 208 Extended Supported display device 4 */
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u32 dd13; /* Offset 212 Extended Supported display device 5 */
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u32 dd14; /* Offset 216 Extended Supported display device 6 */
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u32 dd15; /* Offset 220 Extended Supported display device 7 */
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u32 cpl9; /* Offset 224 Extended Currently present device 1 */
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u32 cp10; /* Offset 228 Extended Currently present device 2 */
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u32 cp11; /* Offset 232 Extended Currently present device 3 */
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u32 cp12; /* Offset 236 Extended Currently present device 4 */
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u32 cp13; /* Offset 240 Extended Currently present device 5 */
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u32 cp14; /* Offset 244 Extended Currently present device 6 */
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u32 cp15; /* Offset 248 Extended Currently present device 7 */
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u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */
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};
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/* mailbox 2: software sci interface */
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struct __packed opregion_mailbox2 {
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u32 scic; /* Offset 0 Software SCI function number parameters */
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u32 parm; /* Offset 4 Software SCI function number parameters */
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u32 dslp; /* Offset 8 Driver sleep timeout */
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u8 reserved[244]; /* Offset 12 Reserved */
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};
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/* mailbox 3: power conservation */
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struct __packed opregion_mailbox3 {
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u32 ardy; /* Offset 0 Driver readiness */
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u32 aslc; /* Offset 4 ASLE interrupt command / status */
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u32 tche; /* Offset 8 Technology enabled indicator */
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u32 alsi; /* Offset 12 Current ALS illuminance reading */
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u32 bclp; /* Offset 16 Backlight britness to set */
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u32 pfit; /* Offset 20 Panel fitting Request */
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u32 cblv; /* Offset 24 Brightness Current State */
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/* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */
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u16 bclm[20];
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u32 cpfm; /* Offset 68 Panel Fitting Current Mode */
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u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */
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u8 plut[74]; /* Offset 76 Panel Look Up Table */
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/* Offset 150 PWM Frequency and Minimum Brightness */
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u32 pfmb;
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u32 ccdv; /* Offset 154 Color Correction Default Values */
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u32 pcft; /* Offset 158 Power Conservation Features */
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u32 srot; /* Offset 162 Supported Rotation angle */
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u32 iuer; /* Offset 166 Intel Ultrabook Event Register */
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u64 fdsp; /* Offset 170 FFS Display Physical address */
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u32 fdss; /* Offset 178 FFS Display Size */
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u32 stat; /* Offset 182 State Indicator */
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/*
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* Offset 186 (Igd opregion offset 0x3BAh)
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* Physical address of Raw VBT data
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*/
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u64 rvda;
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/* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
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u32 rvds;
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u8 reserved[58]; /* Offset 198 Reserved */
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};
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#define IGD_BACKLIGHT_BRIGHTNESS 0xff
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#define IGD_INITIAL_BRIGHTNESS 0x64
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#define IGD_FIELD_VALID BIT(31)
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#define IGD_WORD_FIELD_VALID BIT(15)
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#define IGD_PFIT_STRETCH 6
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/* mailbox 4: vbt */
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struct __packed opregion_vbt {
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u8 gvd1[6 << 10];
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};
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/* Mailbox 5: BIOS to Driver Notification Extension */
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struct __packed opregion_mailbox5 {
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u32 phed; /* Offset 7168 Panel Header */
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u8 bddc[256]; /* Offset 7172 Panel EDID */
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u8 reserved[764]; /* Offset 7428 764 bytes */
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};
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/* IGD OpRegion */
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struct __packed igd_opregion {
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struct opregion_header header;
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struct opregion_mailbox1 mailbox1;
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struct opregion_mailbox2 mailbox2;
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struct opregion_mailbox3 mailbox3;
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struct opregion_vbt vbt;
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struct opregion_mailbox5 mailbox5;
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};
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/* Intel Video BIOS (Option ROM) */
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struct __packed optionrom_header {
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u16 signature;
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u8 size;
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u8 reserved[21];
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u16 pcir_offset;
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u16 vbt_offset;
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};
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#define OPROM_SIGNATURE 0xaa55
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struct __packed optionrom_pcir {
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u32 signature;
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u16 vendor;
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u16 device;
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u16 reserved1;
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u16 length;
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u8 revision;
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u8 classcode[3];
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u16 imagelength;
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u16 coderevision;
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u8 codetype;
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u8 indicator;
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u16 reserved2;
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};
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struct __packed optionrom_vbt {
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u8 hdr_signature[20];
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u16 hdr_version;
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u16 hdr_size;
|
||||
u16 hdr_vbt_size;
|
||||
u8 hdr_vbt_checksum;
|
||||
u8 hdr_reserved;
|
||||
u32 hdr_vbt_datablock;
|
||||
u32 hdr_aim[4];
|
||||
u8 datahdr_signature[16];
|
||||
u16 datahdr_version;
|
||||
u16 datahdr_size;
|
||||
u16 datahdr_datablocksize;
|
||||
u8 coreblock_id;
|
||||
u16 coreblock_size;
|
||||
u16 coreblock_biossize;
|
||||
u8 coreblock_biostype;
|
||||
u8 coreblock_releasestatus;
|
||||
u8 coreblock_hwsupported;
|
||||
u8 coreblock_integratedhw;
|
||||
u8 coreblock_biosbuild[4];
|
||||
u8 coreblock_biossignon[155];
|
||||
};
|
||||
|
||||
/**
|
||||
* intel_gma_init_igd_opregion() - Initialise IGD OpRegion
|
||||
*
|
||||
* This is called from ACPI code and OS drivers
|
||||
*
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int intel_gma_init_igd_opregion(struct udevice *dev,
|
||||
struct igd_opregion *opregion);
|
||||
|
||||
#endif /* _ASM_INTEL_OPREGION_H_ */
|
||||
|
|
@ -3,14 +3,19 @@
|
|||
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY UCLASS_VIDEO
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <vbe.h>
|
||||
#include <video.h>
|
||||
#include <acpi/acpi_table.h>
|
||||
#include <asm/fsp/fsp_support.h>
|
||||
#include <asm/intel_opregion.h>
|
||||
#include <asm/mtrr.h>
|
||||
#include <dm/acpi.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -127,6 +132,32 @@ static int fsp_video_bind(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_INTEL_GMA_ACPI
|
||||
static int fsp_video_acpi_write_tables(const struct udevice *dev,
|
||||
struct acpi_ctx *ctx)
|
||||
{
|
||||
struct igd_opregion *opregion;
|
||||
int ret;
|
||||
|
||||
printf("ACPI: * IGD OpRegion\n");
|
||||
opregion = (struct igd_opregion *)ctx->current;
|
||||
|
||||
ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
acpi_inc_align(ctx, sizeof(struct igd_opregion));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
struct acpi_ops fsp_video_acpi_ops = {
|
||||
#ifdef CONFIG_INTEL_GMA_ACPI
|
||||
.write_tables = fsp_video_acpi_write_tables,
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct udevice_id fsp_video_ids[] = {
|
||||
{ .compatible = "fsp-fb" },
|
||||
{ }
|
||||
|
|
@ -139,6 +170,7 @@ U_BOOT_DRIVER(fsp_video) = {
|
|||
.bind = fsp_video_bind,
|
||||
.probe = fsp_video_probe,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
ACPI_OPS_PTR(&fsp_video_acpi_ops)
|
||||
};
|
||||
|
||||
static struct pci_device_id fsp_video_supported[] = {
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ enum bloblist_tag_t {
|
|||
* Sleeping table. This forms part of the ACPI tables passed to Linux.
|
||||
*/
|
||||
BLOBLISTT_ACPI_GNVS,
|
||||
BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user