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- Convert to DM:

Browse Source 
- bx50v3, mx53ppd, novena, mx6sabresd
 - Fixes for Xea Board
 - Toradex im8m Verdin
 - Cleanup (warp7, mx6sxsabresd)
 
 Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/648131788
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Merge tag 'u-boot-imx-20200210' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

- Convert to DM:
	- bx50v3, mx53ppd, novena, mx6sabresd
- Fixes for Xea Board
- Toradex im8m Verdin
- Cleanup (warp7, mx6sxsabresd)

Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/648131788
This commit is contained in:
Tom Rini 2020-02-10 09:04:11 -05:00
commit c998cbea87
98 changed files with 4107 additions and 921 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -3025,7 +3025,7 @@ Low Level (hardware related) configuration options:
Add the "loopw" memory command. This only takes effect if
the memory commands are activated globally (CONFIG_CMD_MEMORY).
- CONFIG_MX_CYCLIC
- CONFIG_CMD_MX_CYCLIC
Add the "mdc" and "mwc" memory commands. These are cyclic
"md/mw" commands.
Examples:

1
arch/arm/dts/Makefile
View File

@ -718,6 +718,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-verdin.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mp-evk.dtb

2
arch/arm/dts/imx28-xea.dts
View File

@ -38,6 +38,8 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};

46
arch/arm/dts/imx53-ppd-uboot.dtsi
View File

@ -9,4 +9,50 @@
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
bootcount {
compatible = "u-boot,bootcount-i2c-eeprom";
i2c-eeprom = <&bootcount>;
};
panel-lvds0 {
compatible = "simple-panel";
backlight = <&pwm_bl>;
};
};
&eeprom {
partitions {
compatible = "fixed-partitions";
vpd {
offset = <0>;
size = <1022>;
};
bootcount: bootcount {
offset = <1022>;
size = <2>;
};
};
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio4 {
u-boot,dm-pre-reloc;
};
&gpio5 {
u-boot,dm-pre-reloc;
};

5
arch/arm/dts/imx53-ppd.dts
View File

@ -43,7 +43,6 @@
/dts-v1/;
#include "imx53.dtsi"
#include "imx53-ppd-uboot.dtsi"
#include <dt-bindings/input/input.h>
/ {
@ -490,7 +489,7 @@
reg = <1>;
rtc@30 {
compatible = "sii,s35390a";
compatible = "sii,s35392a-rtc";
reg = <0x30>;
};
@ -1084,3 +1083,5 @@
>;
};
};
#include "imx53-ppd-uboot.dtsi"

2
arch/arm/dts/imx6q-b450v3.dts
View File

@ -158,3 +158,5 @@
};
};
};
#include "imx6q-bx50v3-uboot.dtsi"

2
arch/arm/dts/imx6q-b650v3.dts
View File

@ -157,3 +157,5 @@
};
};
};
#include "imx6q-bx50v3-uboot.dtsi"

2
arch/arm/dts/imx6q-b850v3.dts
View File

@ -300,3 +300,5 @@
phy-handle = <&switchphy4>;
};
};
#include "imx6q-bx50v3-uboot.dtsi"

25
arch/arm/dts/imx6q-bx50v3-uboot.dtsi
View File

@ -5,8 +5,33 @@
*/
/ {
bootcount {
compatible = "u-boot,bootcount-i2c-eeprom";
i2c-eeprom = <&bootcount>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
panel-lvds0 {
compatible = "simple-panel";
};
};
&eeprom {
partitions {
compatible = "fixed-partitions";
vpd {
offset = <0>;
size = <1022>;
};
bootcount: bootcount {
offset = <1022>;
size = <2>;
};
};
};

3
arch/arm/dts/imx6q-bx50v3.dtsi
View File

@ -42,7 +42,6 @@
*/
#include "imx6q-ba16.dtsi"
#include "imx6q-bx50v3-uboot.dtsi"
/ {
mclk: clock-mclk {
@ -379,3 +378,5 @@
#interrupt-cells = <1>;
};
};
#include "imx6q-bx50v3-uboot.dtsi"

4
arch/arm/dts/imx7d-sdb-u-boot.dtsi
View File

@ -1,3 +1,7 @@
&fec2 {
status = "disable";
};
&usbotg1 {
dr_mode = "peripheral";
};

10
arch/arm/dts/imx7s-warp-u-boot.dtsi Normal file
View File

@ -0,0 +1,10 @@
/ {
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
};

9
arch/arm/dts/imx7s-warp.dts
View File

@ -17,15 +17,6 @@
reg = <0x80000000 0x20000000>;
};
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio>;

20
arch/arm/dts/imx8mm-pinfunc.h
View File

@ -430,18 +430,26 @@
#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3
#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2
#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3
#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
@ -462,23 +470,31 @@
#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2
#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3
#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0

103
arch/arm/dts/imx8mm-verdin-u-boot.dtsi Normal file
View File

@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2020 Toradex
*/
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&uart1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};

1007
arch/arm/dts/imx8mm-verdin.dts Normal file
View File

File diff suppressed because it is too large Load Diff

7
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -50,11 +50,18 @@ config TARGET_IMX8MP_EVK
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
endif

9
arch/arm/mach-imx/mx6/Kconfig
View File

@ -259,7 +259,16 @@ config TARGET_GW_VENTANA
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
select DM_ETH
select DM_GPIO
select DM_MMC
select DM_PCI
select DM_SCSI
select DM_USB
select DM_VIDEO
select OF_CONTROL
select SUPPORT_SPL
imply CMD_DM
config TARGET_MCCMON6
bool "mccmon6"

2
board/aristainetos/aristainetos.c
View File

@ -521,7 +521,7 @@ struct display_info_t const displays[] = {
};
size_t display_count = ARRAY_SIZE(displays);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),

2
board/freescale/imx8mm_evk/README
View File

@ -3,7 +3,7 @@ U-Boot for the NXP i.MX8MM EVK board
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr fimware
- Get ddr firmware
- Build U-Boot
- Boot

11
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -231,16 +231,6 @@ static void setup_spi(void)
SETUP_IOMUX_PADS(ecspi1_pads);
}
iomux_v3_cfg_t const pcie_pads[] = {
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
};
static void setup_pcie(void)
{
SETUP_IOMUX_PADS(pcie_pads);
}
iomux_v3_cfg_t const di0_pads[] = {
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
@ -508,7 +498,6 @@ int overwrite_console(void)
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_pcie();
return cpu_eth_init(bis);
}

1
board/freescale/mx6sxsabresd/MAINTAINERS
View File

@ -4,4 +4,3 @@ S: Maintained
F: board/freescale/mx6sxsabresd/
F: include/configs/mx6sxsabresd.h
F: configs/mx6sxsabresd_defconfig
F: configs/mx6sxsabresd_spl_defconfig

236
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -321,239 +321,3 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD pin */
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* RST_B, used for power reset cycle */
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_mmc_init(bd_t *bis)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
if ((val & 0xc0) != 0x40) {
printf("Not boot from USDHC!\n");
return -EINVAL;
}
port = (val >> 11) & 0x3;
printf("port %d\n", port);
switch (port) {
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
break;
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = 1; /* Assume uSDHC2 is always present */
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
break;
}
return ret;
}
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_dqm2 = 0x00000028,
.dram_dqm3 = 0x00000028,
.dram_ras = 0x00000020,
.dram_cas = 0x00000020,
.dram_odt0 = 0x00000020,
.dram_odt1 = 0x00000020,
.dram_sdba2 = 0x00000000,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdclk_0 = 0x00000030,
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_sdqs2 = 0x00000028,
.dram_sdqs3 = 0x00000028,
.dram_reset = 0x00000020,
};
const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000020,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_ctlds = 0x00000020,
.grp_ddr_type = 0x000c0000,
.grp_b2ds = 0x00000028,
.grp_b3ds = 0x00000028,
};
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00290025,
.p0_mpwldectrl1 = 0x00220022,
.p0_mpdgctrl0 = 0x41480144,
.p0_mpdgctrl1 = 0x01340130,
.p0_mprddlctl = 0x3C3E4244,
.p0_mpwrdlctl = 0x34363638,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
.density = 4,
.width = 32,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
.dsize = mem_ddr.width/32,
.cs_density = 24,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 2, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

9
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
View File

@ -384,6 +384,15 @@ int checkboard(void)
return 0;
}
/*
* Backlight off and reset LCD before OS handover
*/
void board_preboot_os(void)
{
gpio_set_value(IMX_GPIO_NR(1, 8), 0);
gpio_set_value(IMX_GPIO_NR(5, 9), 0);
}
#ifdef CONFIG_SPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>

2
board/ge/bx50v3/Kconfig
View File

@ -15,6 +15,4 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ge_bx50v3"
source "board/ge/common/Kconfig"
endif

217
board/ge/bx50v3/bx50v3.c
View File

@ -14,7 +14,6 @@
#include <linux/errno.h>
#include <linux/libfdt.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
@ -27,7 +26,8 @@
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <power/regulator.h>
#include <power/da9063_pmic.h>
#include <input.h>
#include <pwm.h>
#include <version.h>
@ -37,6 +37,7 @@
#include "../common/vpd_reader.h"
#include "../../../drivers/net/e1000.h"
#include <pci.h>
#include <panel.h>
DECLARE_GLOBAL_DATA_PTR;
@ -47,10 +48,6 @@ static struct vpd_cache vpd;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
@ -73,63 +70,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
.gp = IMX_GPIO_NR(5, 26)
}
};
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info i2c_pad_info3 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 6)
}
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
@ -163,16 +103,20 @@ int board_phy_config(struct phy_device *phydev)
}
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Power for LVDS Display */
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
/* Backlight enable for LVDS display */
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
/* backlight PWM brightness control */
MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void do_enable_backlight(struct display_info_t const *dev)
{
struct udevice *panel;
int ret;
ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
if (ret) {
printf("Could not find panel: %d\n", ret);
return;
}
panel_set_backlight(panel, 100);
panel_enable_backlight(panel);
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
@ -194,7 +138,7 @@ struct display_info_t const displays[] = {{
.addr = -1,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_lcd,
.enable = NULL,
.enable = do_enable_backlight,
.mode = {
.name = "G121X1-L03",
.refresh = 60,
@ -353,12 +297,6 @@ static void setup_display_bx50v3(void)
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
gpio_request(LVDS_POWER_GP, "lvds_power");
gpio_direction_input(LVDS_POWER_GP);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@ -465,8 +403,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(misc_pads,
ARRAY_SIZE(misc_pads));
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
/* Set LDB clock to Video PLL */
select_ldb_di_clock_source(MXC_PLL5_CLK);
@ -491,10 +427,6 @@ static void set_confidx(const struct vpd_cache* vpd)
int board_init(void)
{
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
if (!read_vpd(&vpd, vpd_callback)) {
int ret, rescan;
@ -519,9 +451,6 @@ int board_init(void)
setup_display_b850v3();
else
setup_display_bx50v3();
gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight");
gpio_direction_input(LVDS_BACKLIGHT_GP);
#endif
/* address of boot parameters */
@ -541,53 +470,26 @@ static const struct boot_mode board_boot_modes[] = {
void pmic_init(void)
{
#define I2C_PMIC 0x2
#define DA9063_I2C_ADDR 0x58
#define DA9063_REG_BCORE2_CFG 0x9D
#define DA9063_REG_BCORE1_CFG 0x9E
#define DA9063_REG_BPRO_CFG 0x9F
#define DA9063_REG_BIO_CFG 0xA0
#define DA9063_REG_BMEM_CFG 0xA1
#define DA9063_REG_BPERI_CFG 0xA2
#define DA9063_BUCK_MODE_MASK 0xC0
#define DA9063_BUCK_MODE_MANUAL 0x00
#define DA9063_BUCK_MODE_SLEEP 0x40
#define DA9063_BUCK_MODE_SYNC 0x80
#define DA9063_BUCK_MODE_AUTO 0xC0
struct udevice *reg;
int ret, i;
static const char * const bucks[] = {
"bcore1",
"bcore2",
"bpro",
"bmem",
"bio",
"bperi",
};
uchar val;
i2c_set_bus_num(I2C_PMIC);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
val &= ~DA9063_BUCK_MODE_MASK;
val |= DA9063_BUCK_MODE_SYNC;
i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
for (i = 0; i < ARRAY_SIZE(bucks); i++) {
ret = regulator_get_by_devname(bucks[i], &reg);
if (reg < 0) {
printf("%s(): Unable to get regulator %s: %d\n",
__func__, bucks[i], ret);
continue;
}
regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
}
}
int board_late_init(void)
@ -660,51 +562,6 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if CONFIG_IS_ENABLED(DM_VIDEO)
int ret;
struct udevice *dev;
#ifdef CONFIG_VIDEO_IPUV3
if (!is_b850v3()) {
gpio_direction_output(LVDS_POWER_GP, 1);
/* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI
*/
mdelay(250);
/* enable backlight PWM 1 */
pwm_init(0, 0, 0);
/* duty cycle 5000000ns, period: 5000000ns */
pwm_config(0, 5000000, 5000000);
/* Backlight Power */
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
pwm_enable(0);
}
#endif
/* Probe, to find a video device to be used to show a message on
* the vidconsole.
*/
ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
if (ret)
return ret;
#endif
return 0;
}
U_BOOT_CMD(
bx50_backlight_enable, 1, 1, do_backlight_enable,
"enable Bx50 backlight",
""
);
int board_fit_config_name_match(const char *name)
{
if (!vpd.is_read)

14
board/ge/common/Kconfig
View File

@ -1,14 +0,0 @@
config SYS_VPD_EEPROM_I2C_ADDR
hex "I2C address of the EEPROM device used for VPD"
help
VPD = Vital Product Data
config SYS_VPD_EEPROM_I2C_BUS
int "I2C bus of the EEPROM device used for VPD."
config SYS_VPD_EEPROM_SIZE
int "Size in bytes of the EEPROM device used for VPD"
config SYS_VPD_EEPROM_I2C_ADDR_LEN
int "Number of bytes to use for VPD EEPROM address"
default 1

17
board/ge/common/ge_common.c
View File

@ -5,27 +5,24 @@
#include <common.h>
#include <env.h>
#include <i2c.h>
#include <dm/uclass.h>
#include <rtc.h>
void check_time(void)
{
struct udevice *dev;
int ret, i;
struct rtc_time tm;
u8 retry = 3;
unsigned int current_i2c_bus = i2c_get_bus_num();
ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
if (ret < 0) {
ret = uclass_get_device(UCLASS_RTC, 0, &dev);
if (ret) {
env_set("rtc_status", "FAIL");
return;
}
rtc_init();
for (i = 0; i < retry; i++) {
ret = rtc_get(&tm);
ret = dm_rtc_get(dev, &tm);
if (!ret || ret == -EINVAL)
break;
}
@ -40,7 +37,7 @@ void check_time(void)
tm.tm_year = 2036;
for (i = 0; i < retry; i++) {
ret = rtc_set(&tm);
ret = dm_rtc_set(dev, &tm);
if (!ret)
break;
}
@ -55,7 +52,5 @@ void check_time(void)
env_set("rtc_status", "2038");
else
env_set("rtc_status", "OK");
i2c_set_bus_num(current_i2c_bus);
}

37
board/ge/common/vpd_reader.c
View File

@ -8,6 +8,9 @@
#include <i2c.h>
#include <linux/bch.h>
#include <stdlib.h>
#include <dm/uclass.h>
#include <i2c_eeprom.h>
#include <hexdump.h>
/* BCH configuration */
@ -200,28 +203,34 @@ int read_vpd(struct vpd_cache *cache,
int (*process_block)(struct vpd_cache *, u8 id, u8 version,
u8 type, size_t size, u8 const *data))
{
static const size_t size = CONFIG_SYS_VPD_EEPROM_SIZE;
int res;
struct udevice *dev;
int ret;
u8 *data;
unsigned int current_i2c_bus = i2c_get_bus_num();
int size;
res = i2c_set_bus_num(CONFIG_SYS_VPD_EEPROM_I2C_BUS);
if (res < 0)
return res;
ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev);
if (ret)
return ret;
size = i2c_eeprom_size(dev);
if (size < 0) {
printf("Unable to get size of eeprom: %d\n", ret);
return ret;
}
data = malloc(size);
if (!data)
return -ENOMEM;
res = i2c_read(CONFIG_SYS_VPD_EEPROM_I2C_ADDR, 0,
CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN,
data, size);
if (res == 0)
res = vpd_reader(size, data, cache, process_block);
ret = i2c_eeprom_read(dev, 0, data, size);
if (ret) {
free(data);
return ret;
}
ret = vpd_reader(size, data, cache, process_block);
free(data);
i2c_set_bus_num(current_i2c_bus);
return res;
return ret;
}

2
board/ge/mx53ppd/Kconfig
View File

@ -13,6 +13,4 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "mx53ppd"
source "board/ge/common/Kconfig"
endif

2
board/ge/mx53ppd/Makefile
View File

@ -7,4 +7,4 @@
# Jason Liu <r64343@freescale.com>
obj-y += mx53ppd.o
obj-$(CONFIG_VIDEO) += mx53ppd_video.o
obj-$(CONFIG_DM_VIDEO) += mx53ppd_video.o

67
board/ge/mx53ppd/mx53ppd.c
View File

@ -39,8 +39,6 @@
#include "../../ge/common/ge_common.h"
#include "../../ge/common/vpd_reader.h"
#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
DECLARE_GLOBAL_DATA_PTR;
static u32 mx53_dram_size[2];
@ -87,9 +85,6 @@ u32 get_board_rev(void)
return get_cpu_rev() & ~(0xF << 8);
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
@ -100,59 +95,6 @@ int board_ehci_hcd_init(int port)
}
#endif
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
PAD_CTL_ODE),
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
PAD_CTL_HYS | PAD_CTL_PKE),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
.gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
.gp = IMX_GPIO_NR(3, 28)
},
.sda = {
.i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
.gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
.gp = IMX_GPIO_NR(3, 21)
}
};
static int clock_1GHz(void)
{
int ret;
@ -182,14 +124,14 @@ void ppd_gpio_init(void)
int i;
imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) {
gpio_request(ppd_gpios[i].gpio, "request");
gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
}
}
int board_early_init_f(void)
{
setup_iomux_fec();
setup_iomux_lcd();
ppd_gpio_init();
return 0;
@ -256,9 +198,6 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
mxc_set_sata_internal_clock();
setup_iomux_i2c();
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
return 0;
}

127
board/ge/mx53ppd/mx53ppd_video.c
View File

@ -9,69 +9,20 @@
*/
#include <common.h>
#include <dm.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/video.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <pwm.h>
#include "ppd_gpio.h"
#include <panel.h>
#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
static struct fb_videomode const nv_spwg = {
.name = "NV-SPWGRGB888",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 15384,
.left_margin = 16,
.right_margin = 210,
.upper_margin = 10,
.lower_margin = 22,
.hsync_len = 30,
.vsync_len = 13,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
};
void setup_iomux_lcd(void)
static int detect_lcd(struct display_info_t const *dev)
{
static const iomux_v3_cfg_t lcd_pads[] = {
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
};
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
return 1;
}
static void lcd_enable(void)
@ -96,39 +47,49 @@ static void lcd_enable(void)
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
&iomux->gpr[2]);
/* Enable backlights */
pwm_init(1, 0, 0);
/* duty cycle 5000000ns, period: 5000000ns */
pwm_config(1, 5000000, 5000000);
/* Backlight Power */
gpio_direction_output(BACKLIGHT_ENABLE, 1);
pwm_enable(1);
}
static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
lcd_enable();
return 0;
}
U_BOOT_CMD(
ppd_lcd_enable, 1, 1, do_lcd_enable,
"enable PPD LCD",
"no parameters"
);
int board_video_skip(void)
static void do_enable_backlight(struct display_info_t const *dev)
{
struct udevice *panel;
int ret;
ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
if (ret)
printf("Display cannot be configured: %d\n", ret);
lcd_enable();
return ret;
ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
if (ret) {
printf("Could not find panel: %d\n", ret);
return;
}
panel_set_backlight(panel, 100);
panel_enable_backlight(panel);
}
struct display_info_t const displays[] = {
{
.bus = -1,
.addr = -1,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_lcd,
.enable = do_enable_backlight,
.mode = {
.name = "NV-SPWGRGB888",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 15384,
.left_margin = 16,
.right_margin = 210,
.upper_margin = 10,
.lower_margin = 22,
.hsync_len = 30,
.vsync_len = 13,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
}
};
size_t display_count = ARRAY_SIZE(displays);

8
board/ge/mx53ppd/ppd_gpio.h
View File

@ -9,15 +9,9 @@
#include <asm/arch/iomux-mx53.h>
#include <asm/gpio.h>
#define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
static const iomux_v3_cfg_t ppd_pads[] = {
/* FEC */
MX53_PAD_EIM_A22__GPIO2_16,
/* UART */
NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL),
/* Video */
MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
@ -57,7 +51,6 @@ struct gpio_cfg {
#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29)
#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
#define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
#define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
@ -87,7 +80,6 @@ static const struct gpio_cfg ppd_gpios[] = {
{ POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
{ POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
{ ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
{ BACKLIGHT_ENABLE, 0 },
{ RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
{ ECSPI1_CS0, 1 },
{ ECSPI1_CS1, 1 },

49
board/liebherr/xea/xea.c
View File

@ -64,9 +64,24 @@ static int boot_tiva0, boot_tiva1;
/* Check if TIVAs request booting via U-Boot proper */
void spl_board_init(void)
{
struct gpio_desc btiva0, btiva1;
struct gpio_desc btiva0, btiva1, en_3_3v;
int ret;
/*
* Setup GPIO0_0 (TIVA power enable pin) to be output high
* to allow TIVA startup.
*/
ret = dm_gpio_lookup_name("GPIO0_0", &en_3_3v);
if (ret)
printf("Cannot get GPIO0_0\n");
ret = dm_gpio_request(&en_3_3v, "pwr_3_3v");
if (ret)
printf("Cannot request GPIO0_0\n");
/* Set GPIO0_0 to HIGH */
dm_gpio_set_dir_flags(&en_3_3v, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
if (ret)
printf("Cannot get GPIO0_23\n");
@ -150,4 +165,36 @@ int dram_init(void)
return mxs_dram_init();
}
#ifdef CONFIG_OF_BOARD_SETUP
static int fdt_fixup_l2switch(void *blob)
{
u8 ethaddr[6];
int ret;
if (eth_env_get_enetaddr("ethaddr", ethaddr)) {
ret = fdt_find_and_setprop(blob,
"/ahb@80080000/switch@800f0000",
"local-mac-address", ethaddr, 6, 1);
if (ret < 0)
printf("%s: can't find usbether@1 node: %d\n",
__func__, ret);
}
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
/*
* i.MX28 L2 switch needs manual update (fixup) of eth MAC address
* (in 'local-mac-address' property) as it uses "switch@800f0000"
* node, not set by default FIT image handling code in
* "ethernet@800f0000"
*/
fdt_fixup_l2switch(blob);
return 0;
}
#endif
#endif /* CONFIG_SPL_BUILD */

39
board/toradex/common/tdx-cfg-block.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2016-2019 Toradex, Inc.
* Copyright (c) 2016-2020 Toradex
*/
#include <common.h>
@ -8,8 +8,11 @@
#if defined(CONFIG_TARGET_APALIS_IMX6) || \
defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX8X)
defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
defined(CONFIG_TARGET_VERDIN_IMX8MN)
#include <asm/arch/sys_proto.h>
#else
#define is_cpu_type(cpu) (0)
@ -112,6 +115,11 @@ const char * const toradex_modules[] = {
[50] = "Colibri iMX8 QuadXPlus 2GB IT",
[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
[52] = "Colibri iMX8 DualX 1GB",
[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
[54] = "Apalis iMX8 DualXPlus 1GB",
[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
[56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */
[57] = "Verdin iMX8M Mini DualLite 1GB",
};
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
@ -294,19 +302,27 @@ static int get_cfgblock_interactive(void)
char *soc;
char it = 'n';
char wb = 'n';
int len;
int len = 0;
/* Unknown module by default */
tdx_hw_tag.prodid = 0;
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN)
else
sprintf(message, "Is the module an IT version? [y/N] ");
len = cli_readline(message);
it = console_buffer[0];
#else
else
it = 'y';
#endif
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
defined(CONFIG_TARGET_COLIBRI_IMX8X)
sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
@ -357,6 +373,12 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_IMX7D;
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
else if (is_cpu_type(MXC_CPU_IMX8MM))
tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
else if (is_cpu_type(MXC_CPU_IMX8MMDL))
tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
else if (is_cpu_type(MXC_CPU_IMX8MN))
tdx_hw_tag.prodid = VERDIN_IMX8MNSL;
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
@ -370,6 +392,16 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = APALIS_IMX8QP;
}
} else if (is_cpu_type(MXC_CPU_IMX8QXP)) {
#ifdef CONFIG_TARGET_APALIS_IMX8X
if (it == 'y' || it == 'Y' || wb == 'y' || wb == 'Y') {
tdx_hw_tag.prodid = APALIS_IMX8QXP_WIFI_BT_IT;
} else {
if (gd->ram_size == 0x40000000)
tdx_hw_tag.prodid = APALIS_IMX8DXP;
else
tdx_hw_tag.prodid = APALIS_IMX8QXP;
}
#elif CONFIG_TARGET_COLIBRI_IMX8X
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
@ -381,6 +413,7 @@ static int get_cfgblock_interactive(void)
else
tdx_hw_tag.prodid = COLIBRI_IMX8DX;
}
#endif
} else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)

7
board/toradex/common/tdx-cfg-block.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2016 Toradex, Inc.
* Copyright (c) 2016-2020 Toradex
*/
#ifndef _TDX_CFG_BLOCK_H
@ -73,6 +73,11 @@ enum {
COLIBRI_IMX8QXP_IT, /* 50 */
COLIBRI_IMX8DX_WIFI_BT,
COLIBRI_IMX8DX,
APALIS_IMX8QXP,
APALIS_IMX8DXP,
VERDIN_IMX8MMQ_WIFI_BT_IT,
VERDIN_IMX8MNSL,
VERDIN_IMX8MMDL,
};
extern const char * const toradex_modules[];

30
board/toradex/verdin-imx8mm/Kconfig Normal file
View File

@ -0,0 +1,30 @@
if TARGET_VERDIN_IMX8MM
config SYS_BOARD
default "verdin-imx8mm"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "verdin-imx8mm"
config TDX_CFG_BLOCK
default y
config TDX_HAVE_MMC
default y
config TDX_CFG_BLOCK_DEV
default "0"
config TDX_CFG_BLOCK_PART
default "1"
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
source "board/toradex/common/Kconfig"
endif

9
board/toradex/verdin-imx8mm/MAINTAINERS Normal file
View File

@ -0,0 +1,9 @@
Verdin iMX8M Mini
M: Igor Opaniuk <igor.opaniuk@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin.dts
F: arch/arm/dts/imx8mm-verdin-u-boot.dtsi
F: board/toradex/verdin-imx8mm/
F: configs/verdin-imx8mm_defconfig
F: include/configs/verdin-imx8mm.h

11
board/toradex/verdin-imx8mm/Makefile Normal file
View File

@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2020 Toradex
#
obj-y += verdin-imx8mm.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

88
board/toradex/verdin-imx8mm/README Normal file
View File

@ -0,0 +1,88 @@
U-Boot for the Toradex Verdin iMX8M Mini Module
Quick Start
===========
- Build the ARM trusted firmware binary
- Get the DDR firmware
- Build U-Boot
- Flash to eMMC
- Boot
Get and Build the ARM Trusted Firmware (Trusted Firmware A)
===========================================================
$ echo "Downloading and building TF-A..."
$ git clone -b imx_4.14.98_2.3.0 https://source.codeaurora.org/external/imx/imx-atf
$ cd imx-atf
Please edit `plat/imx/imx8mm/include/platform_def.h` so it contains proper
values for UART configuration and BL31 base address (correct values listed
below):
#define BL31_BASE 0x910000
#define IMX_BOOT_UART_BASE 0x30860000
#define DEBUG_CONSOLE 1
Then build ATF (TF-A):
$ make PLAT=imx8mm bl31
Get the DDR Firmware
====================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
$ chmod +x firmware-imx-8.4.1.bin
$ ./firmware-imx-8.4.1.bin
$ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
Build U-Boot
============
$ export CROSS_COMPILE=aarch64-linux-gnu-
$ make verdin-imx8mm_defconfig
$ make flash.bin
Flash to eMMC
=============
> tftpboot ${loadaddr} flash.bin
> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
> mmc dev 0 1 && mmc write ${loadaddr} 0x2 ${blkcnt}
As a convenience, instead of the last two commands one may also use the update
U-Boot wrapper:
> run update_uboot
Boot
====
ATF, U-boot proper and u-boot.dtb images are packed into FIT image,
which is loaded and parsed by SPL.
Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper
Output:
U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
Normal Boot
Trying to boot from MMC1
NOTICE: Configuring TZASC380
NOTICE: RDC off
NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
NOTICE: BL31: Built : 01:11:41, Jan 25 2020
NOTICE: sip svc init
U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
Reset cause: POR
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149
Net: eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
Verdin iMX8MM #

16
board/toradex/verdin-imx8mm/imximage.cfg Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Toradex
*/
#define __ASSEMBLY__
FIT
BOOT_FROM emmc_fastboot
LOADER spl/u-boot-spl-ddr.bin 0x7E1000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
DDR_FW lpddr4_pmu_train_1d_imem.bin
DDR_FW lpddr4_pmu_train_1d_dmem.bin
DDR_FW lpddr4_pmu_train_2d_imem.bin
DDR_FW lpddr4_pmu_train_2d_dmem.bin

1850
board/toradex/verdin-imx8mm/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

180
board/toradex/verdin-imx8mm/spl.c Normal file
View File

@ -0,0 +1,180 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Toradex
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <cpu_func.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <hang.h>
#include <power/bd71837.h>
#include <power/pmic.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC1;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
default:
return BOOT_DEVICE_NONE;
}
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
/* Serial download mode */
if (is_usb_boot()) {
puts("Back to ROM, SDP\n");
restore_boot_params();
}
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/* Verdin UART_3, Console/Debug UART */
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@4b", &dev);
if (ret == -ENODEV) {
puts("No pmic\n");
return 0;
}
if (ret != 0)
return ret;
/* decrease RESET key long push time from the default 10s to 10ms */
pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
/* unlock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
/* increase VDD_SOC to typical value 0.85v before first DRAM access */
pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
#ifndef CONFIG_IMX8M_LPDDR4
/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
#endif
/* lock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
arch_cpu_init();
init_uart_clk(0);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
enable_tzc380();
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
puts("resetting ...\n");
reset_cpu(WDOG1_BASE_ADDR);
return 0;
}

73
board/toradex/verdin-imx8mm/verdin-imx8mm.c Normal file
View File

@ -0,0 +1,73 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Toradex
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
#if IS_ENABLED(CONFIG_FEC_MXC)
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif

2
board/warp7/warp7.c
View File

@ -67,7 +67,7 @@ int power_init_board(void)
struct udevice *dev;
int ret, dev_id, rev_id;
ret = pmic_get("pfuze3000", &dev);
ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)

8
cmd/Kconfig
View File

@ -702,7 +702,7 @@ config CMD_MEMORY
base - print or set address offset
loop - initialize loop on address range
config MX_CYCLIC
config CMD_MX_CYCLIC
bool "Enable cyclic md/mw commands"
depends on CMD_MEMORY
help
@ -737,12 +737,6 @@ config SYS_ALT_MEMTEST
endif
config CMD_MX_CYCLIC
bool "mdc, mwc"
help
mdc - memory display cyclic
mwc - memory write cyclic
config CMD_SHA1SUM
bool "sha1sum"
select SHA1

8
cmd/mem.c
View File

@ -165,7 +165,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#ifdef CONFIG_MX_CYCLIC
#ifdef CONFIG_CMD_MX_CYCLIC
static int do_mem_mdc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
@ -219,7 +219,7 @@ static int do_mem_mwc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#endif /* CONFIG_MX_CYCLIC */
#endif /* CONFIG_CMD_MX_CYCLIC */
static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -1270,7 +1270,7 @@ U_BOOT_CMD(
);
#endif /* CONFIG_CMD_MEMTEST */
#ifdef CONFIG_MX_CYCLIC
#ifdef CONFIG_CMD_MX_CYCLIC
U_BOOT_CMD(
mdc, 4, 1, do_mem_mdc,
"memory display cyclic",
@ -1290,7 +1290,7 @@ U_BOOT_CMD(
"[.b, .w, .l] address value delay(ms)"
#endif
);
#endif /* CONFIG_MX_CYCLIC */
#endif /* CONFIG_CMD_MX_CYCLIC */
#ifdef CONFIG_CMD_MEMINFO
U_BOOT_CMD(

2
configs/M5249EVB_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_IMLS=y
CONFIG_LOOPW=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"

2
configs/amcore_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_SYS_PROMPT="amcore $ "
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
CONFIG_LOOPW=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y

2
configs/bcm11130_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

2
configs/bcm11130_nand_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y

2
configs/bcm23550_w1d_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

2
configs/bcm28155_ap_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

2
configs/bcm28155_w1d_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

2
configs/bcm911360_entphn-ns_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm911360_entphn_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm911360k_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm958300k-ns_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm958300k_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm958305k_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y

2
configs/bcm958622hr_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y

2
configs/da850evm_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set

2
configs/da850evm_direct_nor_defconfig
View File

@ -24,7 +24,7 @@ CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_BOOTZ is not set
CONFIG_CMD_IMLS=y
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_GPT is not set
# CONFIG_CMD_MMC is not set

2
configs/da850evm_nand_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set

27
configs/ge_bx50v3_defconfig
View File

@ -2,16 +2,12 @@ CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
CONFIG_SYS_VPD_EEPROM_I2C_BUS=4
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_TARGET_GE_BX50V3=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
@ -33,7 +29,9 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_CLS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@ -48,9 +46,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
@ -71,6 +75,17 @@ CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_PWM_IMX=y
CONFIG_DM_PWM=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_DA9063=y
CONFIG_DM_RTC=y
CONFIG_RTC_RX8010SJ=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y

3
configs/imx28_xea_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0x1000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@ -67,6 +68,8 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=40000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y

2
configs/k2e_evm_defconfig
View File

@ -25,7 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2e_hs_evm_defconfig
View File

@ -17,7 +17,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2g_evm_defconfig
View File

@ -24,7 +24,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2g_hs_evm_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2hk_evm_defconfig
View File

@ -25,7 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2hk_hs_evm_defconfig
View File

@ -17,7 +17,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2l_evm_defconfig
View File

@ -25,7 +25,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/k2l_hs_evm_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set

2
configs/legoev3_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_AUTOBOOT_STOP_STR="l"
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y

31
configs/mx53ppd_defconfig
View File

@ -2,13 +2,9 @@ CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
CONFIG_TARGET_MX53PPD=y
CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
CONFIG_SYS_VPD_EEPROM_I2C_BUS=2
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_ENV_SIZE=0x2800
CONFIG_ENV_OFFSET=0xC0000
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
@ -26,8 +22,10 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CLS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@ -39,24 +37,43 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_IMX=y
CONFIG_DM_RTC=y
CONFIG_RTC_S35392A=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_VIDEO_IPUV3=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
CONFIG_IMX_WATCHDOG=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_DM_PWM=y
CONFIG_VIDEO_BPP16=y

1
configs/mx6sabresd_defconfig
View File

@ -83,6 +83,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y

69
configs/mx6sxsabresd_spl_defconfig
View File

@ -1,69 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DM_GPIO=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y

1
configs/mx6ul_14x14_evk_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y

12
configs/novena_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DM_GPIO=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
@ -33,7 +32,6 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -44,7 +42,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@ -52,19 +49,19 @@ CONFIG_ENV_OFFSET_REDUND=0x84000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SCSI=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
@ -74,7 +71,6 @@ CONFIG_USB_ETH_CDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y

2
configs/omapl138_lcdk_defconfig
View File

@ -30,7 +30,7 @@ CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y

98
configs/verdin-imx8mm_defconfig Normal file
View File

@ -0,0 +1,98 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
CONFIG_TARGET_VERDIN_IMX8MM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg"
CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_LOG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SYS_PROMPT="Verdin iMX8MM # "
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_DM_THERMAL=y

2
configs/x600_defconfig
View File

@ -27,7 +27,7 @@ CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_LOOPW=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y

2
configs/xtfpga_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_MX_CYCLIC=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_SAVES=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y

4
drivers/gpio/Makefile
View File

@ -6,13 +6,11 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
endif
obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o
obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o
ifdef CONFIG_$(SPL_TPL_)GPIO
obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o

35
drivers/misc/i2c_eeprom.c
View File

@ -15,6 +15,8 @@
struct i2c_eeprom_drv_data {
u32 size; /* size in bytes */
u32 pagewidth; /* pagesize = 2^pagewidth */
u32 addr_offset_mask; /* bits in addr used for offset overflow */
u32 offset_len; /* size in bytes of offset */
};
int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size)
@ -140,6 +142,11 @@ static int i2c_eeprom_std_probe(struct udevice *dev)
{
u8 test_byte;
int ret;
struct i2c_eeprom_drv_data *data =
(struct i2c_eeprom_drv_data *)dev_get_driver_data(dev);
i2c_set_chip_offset_len(dev, data->offset_len);
i2c_set_chip_addr_offset_mask(dev, data->addr_offset_mask);
/* Verify that the chip is functional */
ret = i2c_eeprom_read(dev, 0, &test_byte, 1);
@ -152,71 +159,99 @@ static int i2c_eeprom_std_probe(struct udevice *dev)
static const struct i2c_eeprom_drv_data eeprom_data = {
.size = 0,
.pagewidth = 0,
.addr_offset_mask = 0,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data mc24aa02e48_data = {
.size = 256,
.pagewidth = 3,
.addr_offset_mask = 0,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c01a_data = {
.size = 128,
.pagewidth = 3,
.addr_offset_mask = 0,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c02_data = {
.size = 256,
.pagewidth = 3,
.addr_offset_mask = 0,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c04_data = {
.size = 512,
.pagewidth = 4,
.addr_offset_mask = 0x1,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c08_data = {
.size = 1024,
.pagewidth = 4,
.addr_offset_mask = 0x3,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c08a_data = {
.size = 1024,
.pagewidth = 4,
.addr_offset_mask = 0x3,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c16a_data = {
.size = 2048,
.pagewidth = 4,
.addr_offset_mask = 0x7,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24mac402_data = {
.size = 256,
.pagewidth = 4,
.addr_offset_mask = 0,
.offset_len = 1,
};
static const struct i2c_eeprom_drv_data atmel24c32_data = {
.size = 4096,
.pagewidth = 5,
.addr_offset_mask = 0,
.offset_len = 2,
};
static const struct i2c_eeprom_drv_data atmel24c64_data = {
.size = 8192,
.pagewidth = 5,
.addr_offset_mask = 0,
.offset_len = 2,
};
static const struct i2c_eeprom_drv_data atmel24c128_data = {
.size = 16384,
.pagewidth = 6,
.addr_offset_mask = 0,
.offset_len = 2,
};
static const struct i2c_eeprom_drv_data atmel24c256_data = {
.size = 32768,
.pagewidth = 6,
.addr_offset_mask = 0,
.offset_len = 2,
};
static const struct i2c_eeprom_drv_data atmel24c512_data = {
.size = 65536,
.pagewidth = 6,
.addr_offset_mask = 0,
.offset_len = 2,
};
static const struct udevice_id i2c_eeprom_std_ids[] = {

49
include/configs/ge_bx50v3.h
View File

@ -16,9 +16,6 @@
#define CONFIG_BOARD_NAME "General Electric Bx50v3"
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONSOLE_DEV "ttymxc2"
#include "mx6_common.h"
#include <linux/sizes.h>
@ -28,8 +25,6 @@
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_MXC_UART
/* SATA Configs */
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
@ -64,7 +59,7 @@
"setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \
"setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \
"setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \
"setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \
"setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \
"setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \
"setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \
"networkboot=" \
@ -84,34 +79,29 @@
NETWORKBOOT \
"bootcause=POR\0" \
"image=/boot/fitImage\0" \
"fdt_high=0xffffffff\0" \
"dev=mmc\0" \
"devnum=2\0" \
"rootdev=mmcblk0p\0" \
"quiet=quiet loglevel=0\0" \
"console=" CONSOLE_DEV "\0" \
"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
"ro rootwait cma=128M " \
"bootcause=${bootcause} " \
"${quiet} console=${console} " \
"${quiet} " \
"${videoargs}" "\0" \
"doquiet=" \
"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
"then setenv quiet; fi\0" \
"hasfirstboot=" \
"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
"/boot/bootcause/firstboot\0" \
"test -e ${dev} ${devnum}:${partnum} /boot/bootcause/firstboot\0" \
"swappartitions=" \
"setexpr partnum 3 - ${partnum}\0" \
"failbootcmd=" \
"echo reached failbootcmd; " \
"bx50_backlight_enable; " \
"cls; " \
"setcurs 5 4; " \
"lcdputs \"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
"mw.b 0x7000A000 0xbc; " \
"mw.b 0x7000A001 0x00; " \
"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
"bootcount reset; \0" \
"altbootcmd=" \
"run doquiet; " \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
@ -163,6 +153,8 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
@ -189,33 +181,6 @@
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
#define CONFIG_RTC_RX8010SJ
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_NUM_I2C_BUSES 11
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{1, {I2C_NULL_HOP} }, \
{2, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
}
#define CONFIG_BCH
#endif /* __GE_BX50V3_CONFIG_H */

76
include/configs/mx53ppd.h
View File

@ -11,8 +11,6 @@
#include <asm/arch/imx-regs.h>
#define CONSOLE_DEV "ttymxc0"
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@ -25,15 +23,6 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* Eth Configs */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
@ -43,33 +32,12 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR 0x30
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/* Command definition */
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define PPD_CONFIG_NFS \
@ -92,34 +60,26 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
PPD_CONFIG_NFS \
"image=/boot/fitImage\0" \
"fdt_high=0xffffffff\0" \
"dev=mmc\0" \
"devnum=2\0" \
"rootdev=mmcblk0p\0" \
"quiet=quiet loglevel=0\0" \
"console=" CONSOLE_DEV "\0" \
"lvds=ldb\0" \
"setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
"vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
"console=${console}\0" \
"vt.global_cursor_default=0 bootcause=${bootcause} ${quiet}\0" \
"bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
"rootwait ${bootargs}\0" \
"doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
"then setenv quiet; fi\0" \
"hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
"/boot/bootcause/firstboot\0" \
"hasfirstboot=" \
"test -e ${dev} ${devnum}:${partnum} /boot/bootcause/firstboot\0" \
"swappartitions=setexpr partnum 3 - ${partnum}\0" \
"failbootcmd=" \
"ppd_lcd_enable; " \
"msg=\"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
"echo $msg; " \
"setenv stdout vga; " \
"echo \"\n\n\n\n \" $msg; " \
"setenv stdout serial; " \
"mw.b 0x7000A000 0xbc; " \
"mw.b 0x7000A001 0x00; " \
"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
"cls; " \
"setcurs 5 4; " \
"lcdputs \"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
"bootcount reset; \0" \
"altbootcmd=" \
"run doquiet; " \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
@ -166,6 +126,8 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
@ -188,25 +150,11 @@
#define CONFIG_CMD_FUSE
#define CONFIG_FSL_IIM
#define CONFIG_SYS_I2C_SPEED 100000
/* I2C1 */
#define CONFIG_SYS_NUM_I2C_BUSES 9
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
}
#define CONFIG_BCH
/* Backlight Control */
#define CONFIG_IMX6_PWM_PER_CLK 66666000
#define CONFIG_IMX_VIDEO_SKIP
#endif /* __CONFIG_H */

8
include/configs/mx6sabre_common.h
View File

@ -20,14 +20,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV \
"emmcdev=2\0" \

8
include/configs/mx6sabreauto.h
View File

@ -75,4 +75,12 @@
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHY_ATHEROS
#endif /* __MX6SABREAUTO_CONFIG_H */

9
include/configs/mx6sabresd.h
View File

@ -62,4 +62,13 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHY_ATHEROS
#endif /* __MX6SABRESD_CONFIG_H */

5
include/configs/mx6ul_14x14_evk.h
View File

@ -44,11 +44,6 @@
#define CONFIG_SYS_I2C_SPEED 100000
#endif
/* Note: This is incorrect and should move to Kconfig / defconfig */
#ifdef CONFIG_DM_GPIO
#define CONFIG_DM_74X164
#endif
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \

4
include/configs/mx7ulp_com.h
View File

@ -14,10 +14,6 @@
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define SRC_BASE_ADDR CMC1_RBASE
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
/*
* Detect overlap between U-Boot image and environment area in build-time
*

9
include/configs/novena.h
View File

@ -53,13 +53,8 @@
#include "imx6_spl.h" /* common IMX6 SPL configuration */
/* Ethernet Configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x7
#define CONFIG_ARP_TIMEOUT 200UL
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_ETH
#endif
/* I2C */

128
include/configs/verdin-imx8mm.h Normal file
View File

@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Toradex
*/
#ifndef __VERDIN_IMX8MM_H
#define __VERDIN_IMX8MM_H
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE SZ_8K
#endif
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x920000
#define CONFIG_SPL_BSS_START_ADDR 0x910000
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x44000000\0" \
"kernel_addr_r=0x42000000\0" \
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef CONFIG_ISO_PARTITION
#else
#define BOOTENV
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"bootcmd_mfg=fastboot 0\0" \
"console=ttymxc0\0" \
"fdt_addr=0x43000000\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_image=Image\0" \
"setup=setenv setupargs console=${console},${baudrate} " \
"console=tty1 consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
"${blkcnt}; fi\0"
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_ENV_IS_IN_MMC)
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */
#define CONFIG_SYS_MMC_ENV_PART 1
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SYS_I2C_SPEED 100000
/* ENET */
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 7
#define FEC_QUIRK_ENET_MAC
#define IMX_FEC_BASE 0x30BE0000
#endif /*_VERDIN_IMX8MM_H */

4
include/configs/warp7.h
View File

@ -149,12 +149,8 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
#define CONFIG_IMX_THERMAL

6
tools/imx8m_image.sh
View File

@ -14,10 +14,8 @@ for f in $blobs; do
continue
fi
if [ -f $f ]; then
continue
else
echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2
if [ ! -f $f ]; then
echo "WARNING '$f' not found, resulting binary is not-functional" >&2
exit 1
fi
done