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https://github.com/brain-hackers/u-boot-brain
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mmc: am654_sdhci: Add support for input tap delay
DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. Therefore, move all dll configurations to their own functions and gate it with 50 MHz speed and a minimum mode. If both these conditions are not satisfied then configure delay chain modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This commit is contained in:
Faiz Abbas
Lokesh Vutla
parent
8c32b5f370
commit
c964447ea3
@ -62,6 +62,16 @@
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#define CALDONE_MASK BIT(CALDONE_SHIFT)
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#define RETRIM_SHIFT 17
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#define RETRIM_MASK BIT(RETRIM_SHIFT)
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#define SELDLYTXCLK_SHIFT 17
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#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
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#define SELDLYRXCLK_SHIFT 16
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#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
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#define ITAPDLYSEL_SHIFT 0
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#define ITAPDLYSEL_MASK GENMASK(4, 0)
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#define ITAPDLYENA_SHIFT 8
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#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
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#define ITAPCHGWIN_SHIFT 9
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#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
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#define DRIVER_STRENGTH_50_OHM 0x0
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#define DRIVER_STRENGTH_33_OHM 0x1
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@ -70,6 +80,7 @@
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#define DRIVER_STRENGTH_40_OHM 0x4
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#define AM654_SDHCI_MIN_FREQ 400000
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#define CLOCK_TOO_SLOW_HZ 50000000
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struct am654_sdhci_plat {
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struct mmc_config cfg;
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@ -77,6 +88,7 @@ struct am654_sdhci_plat {
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struct regmap *base;
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bool non_removable;
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u32 otap_del_sel[MMC_MODES_END];
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u32 itap_del_sel[MMC_MODES_END];
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u32 trm_icp;
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u32 drv_strength;
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u32 strb_sel;
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@ -89,22 +101,45 @@ struct am654_sdhci_plat {
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};
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struct timing_data {
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const char *binding;
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const char *otap_binding;
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const char *itap_binding;
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u32 capability;
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};
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static const struct timing_data td[] = {
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[MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
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[MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
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[SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
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[UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
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[UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
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[UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
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[UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
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[UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
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[MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
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[MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
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[MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
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[MMC_LEGACY] = {"ti,otap-del-sel-legacy",
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"ti,itap-del-sel-legacy",
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0},
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[MMC_HS] = {"ti,otap-del-sel-mmc-hs",
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"ti,itap-del-sel-mms-hs",
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MMC_CAP(MMC_HS)},
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[SD_HS] = {"ti,otap-del-sel-sd-hs",
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"ti,itap-del-sel-sd-hs",
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MMC_CAP(SD_HS)},
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[UHS_SDR12] = {"ti,otap-del-sel-sdr12",
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"ti,itap-del-sel-sdr12",
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MMC_CAP(UHS_SDR12)},
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[UHS_SDR25] = {"ti,otap-del-sel-sdr25",
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"ti,itap-del-sel-sdr25",
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MMC_CAP(UHS_SDR25)},
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[UHS_SDR50] = {"ti,otap-del-sel-sdr50",
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NULL,
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MMC_CAP(UHS_SDR50)},
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[UHS_SDR104] = {"ti,otap-del-sel-sdr104",
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NULL,
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MMC_CAP(UHS_SDR104)},
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[UHS_DDR50] = {"ti,otap-del-sel-ddr50",
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NULL,
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MMC_CAP(UHS_DDR50)},
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[MMC_DDR_52] = {"ti,otap-del-sel-ddr52",
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"ti,itap-del-sel-ddr52",
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MMC_CAP(MMC_DDR_52)},
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[MMC_HS_200] = {"ti,otap-del-sel-hs200",
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NULL,
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MMC_CAP(MMC_HS_200)},
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[MMC_HS_400] = {"ti,otap-del-sel-hs400",
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NULL,
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MMC_CAP(MMC_HS_400)},
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};
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struct am654_driver_data {
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@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host *host)
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sdhci_set_uhs_timing(host);
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}
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static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
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unsigned int speed)
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{
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int sel50, sel100, freqsel;
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u32 mask, val;
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int ret;
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/* Disable delay chain mode */
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regmap_update_bits(plat->base, PHY_CTRL5,
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SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
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if (plat->flags & FREQSEL_2_BIT) {
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switch (speed) {
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case 200000000:
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sel50 = 0;
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sel100 = 0;
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break;
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case 100000000:
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sel50 = 0;
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sel100 = 1;
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break;
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default:
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sel50 = 1;
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sel100 = 0;
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}
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/* Configure PHY DLL frequency */
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mask = SEL50_MASK | SEL100_MASK;
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val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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} else {
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switch (speed) {
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case 200000000:
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freqsel = 0x0;
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break;
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default:
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freqsel = 0x4;
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}
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regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
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freqsel << FREQSEL_SHIFT);
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}
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/* Configure DLL TRIM */
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mask = DLL_TRIM_ICP_MASK;
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val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
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/* Configure DLL driver strength */
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mask |= DR_TY_MASK;
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val |= plat->drv_strength << DR_TY_SHIFT;
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regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
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/* Enable DLL */
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
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0x1 << ENDLL_SHIFT);
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/*
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* Poll for DLL ready. Use a one second timeout.
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* Works in all experiments done so far
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*/
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
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val & DLLRDY_MASK, 1000, 1000000);
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return ret;
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}
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static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
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u32 itapdly)
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{
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/* Set ITAPCHGWIN before writing to ITAPDLY */
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
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1 << ITAPCHGWIN_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK,
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itapdly << ITAPDLYSEL_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
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}
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static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,
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int mode)
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{
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u32 mask, val;
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val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
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mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);
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}
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static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_plat(dev);
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unsigned int speed = host->mmc->clock;
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int sel50, sel100, freqsel;
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int mode = host->mmc->selected_mode;
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u32 otap_del_sel;
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u32 mask, val;
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int ret;
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@ -148,75 +270,29 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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sdhci_set_clock(host->mmc, speed);
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/* switch phy back on */
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if (speed > AM654_SDHCI_MIN_FREQ) {
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otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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otap_del_sel = plat->otap_del_sel[mode];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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/* Write to STRBSEL for HS400 speed mode */
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if (host->mmc->selected_mode == MMC_HS_400) {
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if (plat->flags & STRBSEL_4_BIT)
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mask |= STRBSEL_4BIT_MASK;
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else
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mask |= STRBSEL_8BIT_MASK;
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/* Write to STRBSEL for HS400 speed mode */
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if (host->mmc->selected_mode == MMC_HS_400) {
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if (plat->flags & STRBSEL_4_BIT)
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mask |= STRBSEL_4BIT_MASK;
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else
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mask |= STRBSEL_8BIT_MASK;
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val |= plat->strb_sel << STRBSEL_SHIFT;
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}
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val |= plat->strb_sel << STRBSEL_SHIFT;
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}
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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if (plat->flags & FREQSEL_2_BIT) {
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switch (speed) {
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case 200000000:
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sel50 = 0;
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sel100 = 0;
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break;
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case 100000000:
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sel50 = 0;
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sel100 = 1;
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break;
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default:
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sel50 = 1;
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sel100 = 0;
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}
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/* Configure PHY DLL frequency */
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mask = SEL50_MASK | SEL100_MASK;
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val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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} else {
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switch (speed) {
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case 200000000:
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freqsel = 0x0;
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break;
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default:
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freqsel = 0x4;
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}
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regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
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freqsel << FREQSEL_SHIFT);
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}
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/* Configure DLL TRIM */
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mask = DLL_TRIM_ICP_MASK;
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val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
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/* Configure DLL driver strength */
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mask |= DR_TY_MASK;
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val |= plat->drv_strength << DR_TY_SHIFT;
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regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
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/* Enable DLL */
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
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0x1 << ENDLL_SHIFT);
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/*
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* Poll for DLL ready. Use a one second timeout.
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* Works in all experiments done so far
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*/
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
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val & DLLRDY_MASK, 1000, 1000000);
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if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
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ret = am654_sdhci_setup_dll(plat, speed);
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if (ret)
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return ret;
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} else {
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am654_sdhci_setup_delay_chain(plat, mode);
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}
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return 0;
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@ -354,15 +430,20 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,
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* value is not found
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*/
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for (i = MMC_HS; i <= MMC_HS_400; i++) {
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ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
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ret = dev_read_u32(dev, td[i].otap_binding,
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&plat->otap_del_sel[i]);
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if (ret) {
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dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
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dev_dbg(dev, "Couldn't find %s\n", td[i].otap_binding);
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/*
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* Remove the corresponding capability
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* if an otap-del-sel value is not found
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*/
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cfg->host_caps &= ~td[i].capability;
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}
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if (td[i].itap_binding)
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dev_read_u32(dev, td[i].itap_binding,
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&plat->itap_del_sel[i]);
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}
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return 0;
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