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board: ns3: define ddr memory layout
Add both DRAM banks memory information and the corresponding MMU page table mappings. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -5,6 +5,29 @@
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/dts-v1/;
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/dts-v1/;
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#include <dt-bindings/memory/bcm-ns3-mc.h>
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/*
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* Single mem reserve region which includes the following:
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* Components name Start Addr Size
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* ------------------------------------------------
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* GIC LPI tables 0x8ad7_0000 0x0009_0000
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* Nitro FW 0x8ae0_0000 0x0020_0000
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* Nitro Crash dump 0x8b00_0000 0x0200_0000
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* OPTEE OS 0x8d00_0000 0x0200_0000
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* BL31 services 0x8f00_0000 0x0010_0000
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* Tmon 0x8f10_0000 0x0000_1000
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* LPM/reserved 0x8f10_1000 0x0000_1000
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* ATF to Bl33 info 0x8f10_2000 0x0000_1000
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* ATF error logs 0x8f10_3000 0x0001_0000
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* Error log parser 0x8f11_3000 0x0010_0000
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*/
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/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
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/* CRMU page tables */
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/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
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#include "ns3.dtsi"
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#include "ns3.dtsi"
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/ {
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/ {
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@ -5,15 +5,41 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/gic-v3.h>
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#include <asm/gic-v3.h>
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#include <asm/system.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/armv8/mmu.h>
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#include <asm/arch-bcmns3/bl33_info.h>
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#include <asm/arch-bcmns3/bl33_info.h>
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#include <dt-bindings/memory/bcm-ns3-mc.h>
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/* Default reset-level = 3 and strap-val = 0 */
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/* Default reset-level = 3 and strap-val = 0 */
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#define L3_RESET 30
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#define L3_RESET 30
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#define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
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/*
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* ns3_dram_bank - DDR bank details
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*
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* @start: DDR bank start address
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* @len: DDR bank length
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*/
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struct ns3_dram_bank {
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u64 start[BCM_NS3_MAX_NR_BANKS];
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u64 len[BCM_NS3_MAX_NR_BANKS];
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};
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/*
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* ns3_dram_hdr - DDR header info
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*
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* @sig: DDR info signature
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* @bank: DDR bank details
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*/
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struct ns3_dram_hdr {
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u32 sig;
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struct ns3_dram_bank bank;
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};
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static struct mm_region ns3_mem_map[] = {
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static struct mm_region ns3_mem_map[] = {
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{
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{
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.virt = 0x0UL,
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.virt = 0x0UL,
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@ -23,9 +49,15 @@ static struct mm_region ns3_mem_map[] = {
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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}, {
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.virt = 0x80000000UL,
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.virt = BCM_NS3_MEM_START,
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.phys = 0x80000000UL,
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.phys = BCM_NS3_MEM_START,
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.size = 0x80000000UL,
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.size = BCM_NS3_MEM_LEN,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = BCM_NS3_BANK_1_MEM_START,
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.phys = BCM_NS3_BANK_1_MEM_START,
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.size = BCM_NS3_BANK_1_MEM_LEN,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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PTE_BLOCK_INNER_SHARE
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}, {
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}, {
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@ -44,6 +76,72 @@ DECLARE_GLOBAL_DATA_PTR;
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*/
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*/
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struct bl33_info *bl33_info __section(".data");
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struct bl33_info *bl33_info __section(".data");
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/*
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* Run modulo 256 checksum calculation and return the calculated checksum
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*/
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static u8 checksum_calc(u8 *p, unsigned int len)
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{
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unsigned int i;
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u8 chksum = 0;
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for (i = 0; i < len; i++)
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chksum += p[i];
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return chksum;
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}
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/*
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* This function parses the memory layout information from a reserved area in
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* DDR, and then fix up the FDT before passing it to Linux.
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*
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* In the case of error, do nothing and the default memory layout in DT will
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* be used
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*/
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static int mem_info_parse_fixup(void *fdt)
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{
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struct ns3_dram_hdr hdr;
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u32 *p32, i, nr_banks;
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u64 *p64;
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/* validate signature */
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p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
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hdr.sig = *p32;
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if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
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printf("DDR info signature 0x%x invalid\n", hdr.sig);
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return -EINVAL;
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}
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/* run checksum test to validate data */
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if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
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printf("Checksum on DDR info failed\n");
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return -EINVAL;
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}
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/* parse information for each bank */
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nr_banks = 0;
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for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
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/* skip banks with a length of zero */
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p64 = (u64 *)BANK_OFFSET(i);
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if (*(p64 + 1) == 0)
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continue;
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hdr.bank.start[i] = *p64;
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hdr.bank.len[i] = *(p64 + 1);
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printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
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hdr.bank.start[i] + hdr.bank.len[i] - 1);
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nr_banks++;
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}
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if (!nr_banks) {
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printf("No DDR banks detected\n");
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return -ENOMEM;
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}
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return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
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nr_banks);
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}
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int board_init(void)
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int board_init(void)
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{
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{
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if (bl33_info->version != BL33_INFO_VERSION)
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if (bl33_info->version != BL33_INFO_VERSION)
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@ -98,6 +196,6 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
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{
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{
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gic_lpi_tables_init();
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gic_lpi_tables_init();
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return 0;
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return mem_info_parse_fixup(fdt);
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}
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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#endif /* CONFIG_OF_BOARD_SETUP */
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@ -4,6 +4,7 @@ CONFIG_TARGET_BCMNS3=y
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CONFIG_SYS_TEXT_BASE=0xFF000000
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CONFIG_SYS_TEXT_BASE=0xFF000000
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CONFIG_ENV_SIZE=0x80000
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CONFIG_ENV_SIZE=0x80000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_LOGLEVEL=7
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CONFIG_LOGLEVEL=7
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CONFIG_SILENT_CONSOLE=y
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CONFIG_SILENT_CONSOLE=y
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CONFIG_SILENT_U_BOOT_ONLY=y
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CONFIG_SILENT_U_BOOT_ONLY=y
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@ -21,3 +22,4 @@ CONFIG_CLK=y
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CONFIG_CLK_CCF=y
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CONFIG_CLK_CCF=y
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPL_OF_LIBFDT=y
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