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https://github.com/brain-hackers/u-boot-brain
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sh: ap325rxa: Remove the board
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
52883bac27
commit
c81b1a8a71
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@ -21,10 +21,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_AP325RXA
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bool "Renesas AP-325RXA"
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select CPU_SH4
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config TARGET_MIGOR
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bool "Migo-R"
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select CPU_SH4
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@ -68,7 +64,6 @@ config SYS_CPU
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source "arch/sh/lib/Kconfig"
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source "board/renesas/MigoR/Kconfig"
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source "board/renesas/ap325rxa/Kconfig"
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source "board/renesas/r0p7734/Kconfig"
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source "board/renesas/r2dplus/Kconfig"
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source "board/renesas/r7780mp/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_AP325RXA
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config SYS_BOARD
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default "ap325rxa"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "ap325rxa"
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endif
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@ -1,7 +0,0 @@
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AP325RXA BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/renesas/ap325rxa/
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F: include/configs/ap325rxa.h
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F: configs/ap325rxa_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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######################################################################### Copyright (C) 2008 Renesas Solutions Corp.
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# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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#
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# board/ap325rxa/Makefile
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#
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#
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obj-y := ap325rxa.o cpld-ap325rxa.o
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extra-y += lowlevel_init.o
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@ -1,148 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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/* PRI control register */
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#define PRPRICR5 0xFF800048 /* LMB */
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#define PRPRICR5_D 0x2a
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/* FPGA control */
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#define FPGA_NAND_CTL 0xB410020C
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#define FPGA_NAND_RST 0x0008
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#define FPGA_NAND_INIT 0x0000
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#define FPGA_NAND_RST_WAIT 10000
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/* I/O port data */
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#define PACR_D 0x0000
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#define PBCR_D 0x0000
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#define PCCR_D 0x1000
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#define PDCR_D 0x0000
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#define PECR_D 0x0410
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#define PFCR_D 0xffff
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#define PGCR_D 0x0000
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#define PHCR_D 0x5011
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#define PJCR_D 0x4400
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#define PKCR_D 0x7c00
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#define PLCR_D 0x0000
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#define PMCR_D 0x0000
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#define PNCR_D 0x0000
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#define PQCR_D 0x0000
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#define PRCR_D 0x0000
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#define PSCR_D 0x0000
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#define PTCR_D 0x0010
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#define PUCR_D 0x0fff
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#define PVCR_D 0xffff
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#define PWCR_D 0x0000
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#define PXCR_D 0x7500
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#define PYCR_D 0x0000
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#define PZCR_D 0x5540
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/* Pin Function Controler data */
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#define PSELA_D 0x1410
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#define PSELB_D 0x0140
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#define PSELC_D 0x0000
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#define PSELD_D 0x0400
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/* I/O Buffer Hi-Z data */
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#define HIZCRA_D 0x0000
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#define HIZCRB_D 0x1000
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#define HIZCRC_D 0x0000
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#define HIZCRD_D 0x0000
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/* Module select reg data */
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#define MSELCRA_D 0x0014
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#define MSELCRB_D 0x0018
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/* Module Stop reg Data */
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#define MSTPCR2_D 0xFFD9F280
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/* CPLD loader */
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extern void init_cpld(void);
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int checkboard(void)
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{
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puts("BOARD: AP325RXA\n");
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return 0;
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}
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int board_init(void)
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{
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/* Pin Function Controler Init */
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outw(PSELA_D, PSELA);
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outw(PSELB_D, PSELB);
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outw(PSELC_D, PSELC);
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outw(PSELD_D, PSELD);
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/* I/O Buffer Hi-Z Init */
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outw(HIZCRA_D, HIZCRA);
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outw(HIZCRB_D, HIZCRB);
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outw(HIZCRC_D, HIZCRC);
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outw(HIZCRD_D, HIZCRD);
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/* Module select reg Init */
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outw(MSELCRA_D, MSELCRA);
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outw(MSELCRB_D, MSELCRB);
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/* Module Stop reg Init */
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outl(MSTPCR2_D, MSTPCR2);
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/* I/O ports */
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outw(PACR_D, PACR);
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outw(PBCR_D, PBCR);
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outw(PCCR_D, PCCR);
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outw(PDCR_D, PDCR);
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outw(PECR_D, PECR);
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outw(PFCR_D, PFCR);
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outw(PGCR_D, PGCR);
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outw(PHCR_D, PHCR);
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outw(PJCR_D, PJCR);
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outw(PKCR_D, PKCR);
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outw(PLCR_D, PLCR);
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outw(PMCR_D, PMCR);
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outw(PNCR_D, PNCR);
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outw(PQCR_D, PQCR);
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outw(PRCR_D, PRCR);
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outw(PSCR_D, PSCR);
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outw(PTCR_D, PTCR);
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outw(PUCR_D, PUCR);
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outw(PVCR_D, PVCR);
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outw(PWCR_D, PWCR);
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outw(PXCR_D, PXCR);
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outw(PYCR_D, PYCR);
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outw(PZCR_D, PZCR);
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/* PRI control register Init */
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outl(PRPRICR5_D, PRPRICR5);
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/* cpld init */
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init_cpld();
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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void ide_set_reset(int idereset)
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{
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outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
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udelay(FPGA_NAND_RST_WAIT);
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outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -1,204 +0,0 @@
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/***************************************************************
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* Project:
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* CPLD SlaveSerial Configuration via embedded microprocessor.
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*
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* Copyright info:
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*
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* This is free software; you can redistribute it and/or modify
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* it as you like.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Description:
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*
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* This is the main source file that will allow a microprocessor
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* to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
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* and Spartan-II devices via the SlaveSerial Configuration Mode.
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* This code is discussed in Xilinx Application Note, XAPP502.
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*
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* History:
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* 3-October-2001 MN/MP - Created
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* 20-August-2008 Renesas Solutions - Modified to SH7723
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****************************************************************/
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#include <common.h>
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/* Serial */
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#define SCIF_BASE 0xffe00000 /* SCIF0 */
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#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
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#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
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#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
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#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
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#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define RFCR (vu_long *)0xFE400020
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#define SCSCR_INIT 0x0038
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#define SCSCR_CLR 0x0000
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#define SCFCR_INIT 0x0006
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#define SCSMR_INIT 0x0080
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#define RFCR_CLR 0xA400
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#define SCI_TD_E 0x0020
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#define SCI_TDRE_CLEAR 0x00df
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#define BPS_SETTING_VALUE 1 /* 12.5MHz */
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#define WAIT_RFCR_COUNTER 500
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/* CPLD data size */
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#define CPLD_DATA_SIZE 169216
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/* out */
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#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
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#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
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#define CPLD_PROG_DAT 0x80
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/* in */
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#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
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#define CPLD_INIT_DAT 0x40
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#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
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#define CPLD_DONE_DAT 0x20
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/* data */
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#define CPLD_NOMAL_START 0xA0A80000
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#define CPLD_SAFE_START 0xA0AC0000
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#define MODE_SW (vu_char *)0xA405012A
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static void init_cpld_loader(void)
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{
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*SCSCR = SCSCR_CLR;
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*SCFCR = SCFCR_INIT;
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*SCSMR = SCSMR_INIT;
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*SCBRR = BPS_SETTING_VALUE;
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*RFCR = RFCR_CLR; /* Refresh counter clear */
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while (*RFCR < WAIT_RFCR_COUNTER)
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;
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*SCFCR = 0x0; /* RTRG=00, TTRG=00 */
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/* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
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*SCSCR = SCSCR_INIT;
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}
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static int check_write_ready(void)
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{
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u16 status = *SC_SR;
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return status & SCI_TD_E;
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}
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static void write_cpld_data(char ch)
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{
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while (!check_write_ready())
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;
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*SC_TDR = ch;
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*SC_SR;
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*SC_SR = SCI_TDRE_CLEAR;
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}
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static int delay(void)
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{
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int i;
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int c = 0;
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for (i = 0; i < 200; i++) {
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c = *(volatile int *)0xa0000000;
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}
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return c;
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}
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/***********************************************************************
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*
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* Function: slave_serial
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*
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* Description: Initiates SlaveSerial Configuration.
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* Calls ShiftDataOut() to output serial data
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*
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***********************************************************************/
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static void slave_serial(void)
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{
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int i;
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unsigned char *flash;
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*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
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delay();
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/*
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* Toggle Program Pin by Toggling Program_OE bit
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* This is accomplished by writing to the Program Register in the CPLD
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*
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* NOTE: The Program_OE bit should be driven high to bring the Virtex
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* Program Pin low. Likewise, it should be driven low
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* to bring the Virtex Program Pin to High-Z
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*/
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*CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
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delay();
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/*
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* Bring Program High-Z
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* (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
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*/
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/* Program_OE bit Low brings the Virtex Program Pin to High Z: */
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*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
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while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
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delay();
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/* Begin Slave-Serial Configuration */
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flash = (unsigned char *)CPLD_NOMAL_START;
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for (i = 0; i < CPLD_DATA_SIZE; i++)
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write_cpld_data(*flash++);
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}
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/***********************************************************************
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*
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* Function: check_done_bit
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*
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* Description: This function takes monitors the CPLD Input Register
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* by checking the status of the DONE bit in that Register.
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* By doing so, it monitors the Xilinx Virtex device's DONE
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* Pin to see if configuration bitstream has been properly
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* loaded
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*
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***********************************************************************/
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static void check_done_bit(void)
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{
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while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
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;
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}
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/***********************************************************************
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*
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* Function: init_cpld
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*
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* Description: Begins Slave Serial configuration of Xilinx FPGA
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*
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***********************************************************************/
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void init_cpld(void)
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{
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/* Init serial device */
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init_cpld_loader();
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if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
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return;
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*((vu_short *)HIZCRB) = 0x0000;
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*CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
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/* write CPLD data from NOR flash to device */
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slave_serial();
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/*
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* Monitor the DONE bit in the CPLD Input Register to see if
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* configuration successful
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*/
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check_done_bit();
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}
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@ -1,170 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* board/ap325rxa/lowlevel_init.S
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write16 DRVCRA_A, DRVCRA_D
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write16 DRVCRB_A, DRVCRB_D
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write16 RWTCSR_A, RWTCSR_D1
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write16 RWTCNT_A, RWTCNT_D
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write16 RWTCSR_A, RWTCSR_D2
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write32 FRQCR_A, FRQCR_D
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write32 CMNCR_A, CMNCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5ABCR_A, CS5ABCR_D
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write32 CS5BBCR_A, CS5BBCR_D
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write32 CS6ABCR_A, CS6ABCR_D
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write32 CS6BBCR_A, CS6BBCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5AWCR_A, CS5AWCR_D
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write32 CS5BWCR_A, CS5BWCR_D
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write32 CS6AWCR_A, CS6AWCR_D
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write32 CS6BWCR_A, CS6BWCR_D
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write32 SBSC_SDCR_A, SBSC_SDCR_D1
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write32 SBSC_SDWCR_A, SBSC_SDWCR_D
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write32 SBSC_SDPCR_A, SBSC_SDPCR_D
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write32 SBSC_RTCSR_A, SBSC_RTCSR_D
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|
||||
write32 SBSC_RTCNT_A, SBSC_RTCNT_D
|
||||
|
||||
write32 SBSC_RTCOR_A, SBSC_RTCOR_D
|
||||
|
||||
write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
|
||||
|
||||
write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
|
||||
|
||||
mov.l SLEEP_CNT, r1
|
||||
2: tst r1, r1
|
||||
nop
|
||||
bf/s 2b
|
||||
dt r1
|
||||
|
||||
write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
|
||||
|
||||
write32 SBSC_SDCR_A, SBSC_SDCR_D2
|
||||
|
||||
write32 CCR_A, CCR_D
|
||||
|
||||
! BL bit off (init = ON) (?!?)
|
||||
|
||||
stc sr, r0 ! BL bit off(init=ON)
|
||||
mov.l SR_MASK_D, r1
|
||||
and r1, r0
|
||||
ldc r0, sr
|
||||
|
||||
rts
|
||||
mov #0, r0
|
||||
|
||||
.align 2
|
||||
|
||||
DRVCRA_A: .long DRVCRA
|
||||
DRVCRB_A: .long DRVCRB
|
||||
DRVCRA_D: .word 0x4555
|
||||
DRVCRB_D: .word 0x0005
|
||||
|
||||
RWTCSR_A: .long RWTCSR
|
||||
RWTCNT_A: .long RWTCNT
|
||||
FRQCR_A: .long FRQCR
|
||||
RWTCSR_D1: .word 0xa507
|
||||
RWTCSR_D2: .word 0xa504
|
||||
RWTCNT_D: .word 0x5a00
|
||||
.align 2
|
||||
FRQCR_D: .long 0x0b04474a
|
||||
|
||||
SBSC_SDCR_A: .long SBSC_SDCR
|
||||
SBSC_SDWCR_A: .long SBSC_SDWCR
|
||||
SBSC_SDPCR_A: .long SBSC_SDPCR
|
||||
SBSC_RTCSR_A: .long SBSC_RTCSR
|
||||
SBSC_RTCNT_A: .long SBSC_RTCNT
|
||||
SBSC_RTCOR_A: .long SBSC_RTCOR
|
||||
SBSC_SDMR3_A1: .long 0xfe510000
|
||||
SBSC_SDMR3_A2: .long 0xfe500242
|
||||
SBSC_SDMR3_A3: .long 0xfe5c0042
|
||||
|
||||
SBSC_SDCR_D1: .long 0x92810112
|
||||
SBSC_SDCR_D2: .long 0x92810912
|
||||
SBSC_SDWCR_D: .long 0x05162482
|
||||
SBSC_SDPCR_D: .long 0x00300087
|
||||
SBSC_RTCSR_D: .long 0xa55a0212
|
||||
SBSC_RTCNT_D: .long 0xa55a0000
|
||||
SBSC_RTCOR_D: .long 0xa55a0040
|
||||
SBSC_SDMR3_D: .long 0x00
|
||||
|
||||
CMNCR_A: .long CMNCR
|
||||
CS0BCR_A: .long CS0BCR
|
||||
CS4BCR_A: .long CS4BCR
|
||||
CS5ABCR_A: .long CS5ABCR
|
||||
CS5BBCR_A: .long CS5BBCR
|
||||
CS6ABCR_A: .long CS6ABCR
|
||||
CS6BBCR_A: .long CS6BBCR
|
||||
CS0WCR_A: .long CS0WCR
|
||||
CS4WCR_A: .long CS4WCR
|
||||
CS5AWCR_A: .long CS5AWCR
|
||||
CS5BWCR_A: .long CS5BWCR
|
||||
CS6AWCR_A: .long CS6AWCR
|
||||
CS6BWCR_A: .long CS6BWCR
|
||||
|
||||
CMNCR_D: .long 0x00000013
|
||||
CS0BCR_D: .long 0x24920400
|
||||
CS4BCR_D: .long 0x24920400
|
||||
CS5ABCR_D: .long 0x24920400
|
||||
CS5BBCR_D: .long 0x7fff0600
|
||||
CS6ABCR_D: .long 0x24920400
|
||||
CS6BBCR_D: .long 0x24920600
|
||||
CS0WCR_D: .long 0x00000480
|
||||
CS4WCR_D: .long 0x00000480
|
||||
CS5AWCR_D: .long 0x00000380
|
||||
CS5BWCR_D: .long 0x00000080
|
||||
CS6AWCR_D: .long 0x00000300
|
||||
CS6BWCR_D: .long 0x00000540
|
||||
|
||||
CCR_A: .long 0xff00001c
|
||||
CCR_D: .long 0x0000090d
|
||||
|
||||
SLEEP_CNT: .long 0x00000800
|
||||
SR_MASK_D: .long 0xEFFFFF0F
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
CONFIG_SH=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8FFC0000
|
||||
CONFIG_TARGET_AP325RXA=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttySC2,38400"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_CMDLINE_EDITING is not set
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_RUN is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
CONFIG_CMD_IDE=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SOURCE is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMC911X_BASE=0xB6080000
|
||||
CONFIG_SMC911X_32_BIT=y
|
||||
CONFIG_BAUDRATE=38400
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuation settings for the Renesas Solutions AP-325RXA board
|
||||
*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef __AP325RXA_H
|
||||
#define __AP325RXA_H
|
||||
|
||||
#define CONFIG_CPU_SH7723 1
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#define AP325RXA_SDRAM_BASE (0x88000000)
|
||||
#define AP325RXA_FLASH_BASE_1 (0xA0000000)
|
||||
#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
|
||||
|
||||
/* undef to save memory */
|
||||
/* Monitor Command Prompt */
|
||||
/* Buffer size for Console output */
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
/* List of legal baudrate settings for this board */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
|
||||
#define CONFIG_CONS_SCIF5 1
|
||||
|
||||
/* Suppress display of console information at boot */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
|
||||
|
||||
/* Enable alternate, more extensive, memory test */
|
||||
/* Scratch address used by the alternate memory test */
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
|
||||
/* Enable temporary baudrate change while serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
|
||||
/* maybe more, but if so u-boot doesn't know about it... */
|
||||
#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
|
||||
/* default load address for scripts ?!? */
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
|
||||
|
||||
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
|
||||
#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
|
||||
/* Monitor size */
|
||||
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
/* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
/* Physical start address of Flash memory */
|
||||
#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
|
||||
/* Max number of sectors on each Flash chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
/*
|
||||
* IDE support
|
||||
*/
|
||||
#define CONFIG_IDE_RESET 1
|
||||
#define CONFIG_SYS_PIO_MODE 1
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
|
||||
#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
|
||||
#define CONFIG_IDE_SWAP_IO
|
||||
|
||||
/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
|
||||
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
|
||||
/*
|
||||
* Use hardware flash sectors protection instead
|
||||
* of U-Boot software protection
|
||||
*/
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
#endif /* __AP325RXA_H */
|
||||
Loading…
Reference in New Issue
Block a user