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https://github.com/brain-hackers/u-boot-brain
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board: atmel: sama5d2_wlsom1_ek: add SPL support
Add support for SPL for this board: DRAM initialization, PMC initialization, MMC boot. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This commit is contained in:
Eugen Hristev
parent
a34ae7cb46
commit
c721c22a03
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@ -189,6 +189,7 @@ config TARGET_SAMA5D27_WLSOM1_EK
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select CPU_V7A
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select SUPPORT_SPL
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help
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The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package),
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a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless
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@ -78,3 +78,150 @@ int dram_init(void)
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SD_BOOT
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void spl_mmc_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
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at91_periph_clk_enable(ATMEL_ID_SDMMC0);
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}
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#endif
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void spl_board_init(void)
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{
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#ifdef CONFIG_SD_BOOT
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spl_mmc_init();
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#endif
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}
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void spl_display_print(void)
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{
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_ZQ_SHORT |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
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/*
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* The AD220032D average time between REFRESH commands (Trefi): 3.9us
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* 3.9us * 164MHz = 639.6 = 0x27F.
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*/
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ddrc->rtr = 0x27f;
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/* Enable Adjust Refresh Rate */
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ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
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ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
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(11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
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(5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
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ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
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(23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
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ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
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(10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
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ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
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/*
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* According to the sama5d2 datasheet and the following values:
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* T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
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* Warning: note that the values T driftrate and V driftrate are dependent on
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* the application environment.
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* ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
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* If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
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* this timer to 0xFFFE.
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*/
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ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
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/*
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* MR4 Read interval is dependent on the application environment.
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* Here, we want to maximize this value as temperature is supposed
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* to vary slowly in the application chosen.
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* If Trefi is 3.9us, we have:
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* (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
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*/
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ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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struct atmel_mpddrc_config ddrc_config;
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u32 reg;
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(AT91_PMC_DDR, &pmc->scer);
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ddrc_conf(&ddrc_config);
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reg = readl(&mpddrc->io_calibr);
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
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reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
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reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
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writel(reg, &mpddrc->io_calibr);
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writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
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&mpddrc->rd_data_path);
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lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
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}
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void at91_pmc_init(void)
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{
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u32 tmp;
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/*
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* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
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* so we need to slow down and configure MCKR accordingly.
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* This is why we have a special flavor of the switching function.
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*/
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tmp = AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_MAIN;
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at91_mck_init_down(tmp);
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(40) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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tmp = AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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@ -2,12 +2,20 @@ CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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CONFIG_SYS_TEXT_BASE=0x26f00000
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CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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CONFIG_ENV_SIZE=0x4000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0xf801c000
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CONFIG_DEBUG_UART_CLOCK=82000000
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CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
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CONFIG_SPL_FS_FAT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_DEBUG_UART=y
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CONFIG_ENV_VARS_UBOOT_CONFIG=y
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CONFIG_FIT=y
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@ -15,9 +23,13 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
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CONFIG_SD_BOOT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
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CONFIG_MISC_INIT_R=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_TEXT_BASE=0x200000
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CONFIG_SPL_SEPARATE_BSS=y
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CONFIG_SPL_DISPLAY_PRINT=y
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# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_FLASH is not set
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@ -31,9 +43,15 @@ CONFIG_CMD_PING=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
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CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
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CONFIG_ENV_IS_IN_FAT=y
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CONFIG_DM=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_CLK_AT91=y
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CONFIG_AT91_UTMI=y
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CONFIG_AT91_H32MX=y
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@ -56,6 +74,7 @@ CONFIG_PHY_MICREL=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_AT91PIO4=y
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CONFIG_DM_SERIAL=y
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CONFIG_DEBUG_UART_ATMEL=y
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@ -64,9 +83,11 @@ CONFIG_ATMEL_USART=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_ATMEL_PIT_TIMER=y
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CONFIG_W1=y
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CONFIG_W1_GPIO=y
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CONFIG_W1_EEPROM=y
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CONFIG_W1_EEPROM_DS24XXX=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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# CONFIG_EFI_LOADER_HII is not set
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@ -19,16 +19,28 @@
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x218000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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/* NAND flash */
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#undef CONFIG_CMD_NAND
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x200000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#endif
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#endif
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