From c6d99986f025f1e79b8377ec6bd39131cf2f2b0e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Feb 2018 10:35:15 +0100 Subject: [PATCH] clk: renesas: Add R8A77965 M3N entries Add entries for the R8A77965 M3N SoC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index fb811e943e..48f19b138f 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -323,11 +323,30 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .get_pll_config = r8a7796_get_pll_config, }; +static const struct cpg_mssr_info r8a77965_cpg_mssr_info = { + .core_clk = r8a7796_core_clks, + .core_clk_size = ARRAY_SIZE(r8a7796_core_clks), + .mod_clk = r8a7796_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks), + .mstp_table = r8a7796_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table), + .reset_node = "renesas,r8a77965-rst", + .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a7796_get_pll_config, +}; + static const struct udevice_id r8a7796_clk_ids[] = { { .compatible = "renesas,r8a7796-cpg-mssr", .data = (ulong)&r8a7796_cpg_mssr_info, }, + { + .compatible = "renesas,r8a77965-cpg-mssr", + .data = (ulong)&r8a77965_cpg_mssr_info, + }, { } };