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tegra: fdt: Add NAND controller binding and definitions
Add a NAND controller along with a bindings file for review. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -204,4 +204,11 @@
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compatible = "nvidia,tegra20-kbc";
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compatible = "nvidia,tegra20-kbc";
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reg = <0x7000e200 0x0078>;
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reg = <0x7000e200 0x0078>;
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};
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};
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nand: nand-controller@70008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-nand";
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reg = <0x70008000 0x100>;
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};
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};
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};
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53
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
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53
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
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NAND Flash
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----------
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(there isn't yet a generic binding in Linux, so this describes what is in
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U-Boot. There should not be Linux-specific or U-Boot specific binding, just
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a binding that describes this hardware. But agreeing a binding in Linux in
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the absence of a driver may be beyond my powers.)
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The device node for a NAND flash device is as follows:
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Required properties :
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- compatible : Should be "manufacturer,device", "nand-flash"
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This node should sit inside its controller.
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Nvidia NAND Controller
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----------------------
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The device node for a NAND flash controller is as follows:
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Optional properties:
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nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
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phandle, parameter, flags
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nvidia,nand-width : bus width of the NAND device in bits
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- nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
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Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
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TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
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MAX_TRP_TREA is:
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non-EDO mode: Max(tRP, tREA) + 6ns
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EDO mode: tRP timing
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The 'reg' property should provide the chip select used by the flash chip.
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Example
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-------
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nand-controller@0x70008000 {
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compatible = "nvidia,tegra20-nand";
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#address-cells = <1>;
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#size-cells = <0>;
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nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
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nvidia,nand-width = <8>;
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nvidia,timing = <26 100 20 80 20 10 12 10 70>;
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nand@0 {
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reg = <0>;
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compatible = "hynix,hy27uf4g2b", "nand-flash";
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};
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};
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