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board: colibri_imx7: reserve DDR memory for Cortex-M4
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Use the linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
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@ -153,6 +153,8 @@ void init_src(void);
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void init_snvs(void);
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void imx_wdog_disable_powerdown(void);
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int arch_auxiliary_core_check_up(u32 core_id);
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int board_mmc_get_env_dev(int devno);
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int nxp_board_rev(void);
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@ -333,6 +333,43 @@ int checkboard(void)
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
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int up;
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up = arch_auxiliary_core_check_up(0);
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if (up) {
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int ret;
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int areas = 1;
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u64 start[2], size[2];
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/*
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* Reserve 1MB of memory for M4 (1MiB is also the minimum
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* alignment for Linux due to MMU section size restrictions).
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*/
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start[0] = gd->bd->bi_dram[0].start;
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size[0] = SZ_256M - SZ_1M;
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/* If needed, create a second entry for memory beyond 256M */
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if (gd->bd->bi_dram[0].size > SZ_256M) {
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start[1] = gd->bd->bi_dram[0].start + SZ_256M;
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size[1] = gd->bd->bi_dram[0].size - SZ_256M;
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areas = 2;
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}
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ret = fdt_set_usable_memory(blob, start, size, areas);
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if (ret) {
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eprintf("Cannot set usable memory\n");
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return ret;
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}
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} else {
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int off;
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off = fdt_node_offset_by_compatible(blob, -1,
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"fsl,imx7d-rpmsg");
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if (off > 0)
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fdt_status_disabled(blob, off);
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}
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#endif
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#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
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static const struct node_info nodes[] = {
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{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
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