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https://github.com/brain-hackers/u-boot-brain
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ddr: altera: Clean up scc_set_bypass_mode()
The mode argument of this function is not used at all, zap it. Signed-off-by: Marek Vasut <marex@denx.de>
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5e83789634
commit
c5c5f5378f
@ -503,12 +503,15 @@ static void scc_mgr_zero_all(void)
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writel(0, &sdr_scc_mgr->update);
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writel(0, &sdr_scc_mgr->update);
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}
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}
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static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
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/**
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* scc_set_bypass_mode() - Set bypass mode and trigger SCC update
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* @write_group: Write group
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*
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* Set bypass mode and trigger SCC update.
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*/
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static void scc_set_bypass_mode(const u32 write_group)
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{
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{
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/* mode = 0 : Do NOT bypass - Half Rate Mode */
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/* Only needed once to set all groups, pins, DQ, DQS, DM. */
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/* mode = 1 : Bypass - Full Rate Mode */
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/* only need to set once for all groups, pins, dq, dqs, dm */
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if (write_group == 0) {
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if (write_group == 0) {
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debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
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debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
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__LINE__);
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__LINE__);
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@ -516,17 +519,18 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
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debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
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debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
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__func__, __LINE__);
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__func__, __LINE__);
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}
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}
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/* multicast to all DQ enables */
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/* Multicast to all DQ enables. */
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writel(0xff, &sdr_scc_mgr->dq_ena);
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writel(0xff, &sdr_scc_mgr->dq_ena);
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writel(0xff, &sdr_scc_mgr->dm_ena);
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writel(0xff, &sdr_scc_mgr->dm_ena);
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/* update current DQS IO enable */
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/* Update current DQS IO enable. */
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writel(0, &sdr_scc_mgr->dqs_io_ena);
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writel(0, &sdr_scc_mgr->dqs_io_ena);
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/* update the DQS logic */
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/* Update the DQS logic. */
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writel(write_group, &sdr_scc_mgr->dqs_ena);
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writel(write_group, &sdr_scc_mgr->dqs_ena);
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/* hit update */
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/* Hit update. */
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writel(0, &sdr_scc_mgr->update);
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writel(0, &sdr_scc_mgr->update);
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}
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}
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@ -3314,11 +3318,10 @@ static uint32_t mem_calibrate(void)
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mem_config();
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mem_config();
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uint32_t bypass_mode = 0x1;
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for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
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for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
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writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
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writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
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SCC_MGR_GROUP_COUNTER_OFFSET);
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SCC_MGR_GROUP_COUNTER_OFFSET);
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scc_set_bypass_mode(i, bypass_mode);
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scc_set_bypass_mode(i);
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}
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}
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if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
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if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
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