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clk: mediatek: add pciesys support for MT7622 SoC
This patch adds pciesys support in clock driver for MediaTek MT7622 SoC. Signed-off-by: Henry Yen <henry.yen@mediatek.com> Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
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@ -453,6 +453,41 @@ static const struct mtk_gate peri_cgs[] = {
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GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
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GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
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};
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};
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/* pciesys */
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static const struct mtk_gate_regs pcie_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x30,
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.sta_ofs = 0x30,
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};
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#define GATE_PCIE(_id, _parent, _shift) { \
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.id = _id, \
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.parent = _parent, \
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.regs = &pcie_cg_regs, \
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.shift = _shift, \
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.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
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}
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static const struct mtk_gate pcie_cgs[] = {
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GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
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GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
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GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
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GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
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GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
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GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
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GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
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GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
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GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
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GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
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GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
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GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
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GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
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GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
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GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
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GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
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GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
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};
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/* ethsys */
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/* ethsys */
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static const struct mtk_gate_regs eth_cg_regs = {
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static const struct mtk_gate_regs eth_cg_regs = {
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.sta_ofs = 0x30,
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.sta_ofs = 0x30,
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@ -554,6 +589,11 @@ static int mt7622_pericfg_probe(struct udevice *dev)
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
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}
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}
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static int mt7622_pciesys_probe(struct udevice *dev)
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{
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
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}
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static int mt7622_ethsys_probe(struct udevice *dev)
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static int mt7622_ethsys_probe(struct udevice *dev)
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{
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{
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
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@ -597,6 +637,11 @@ static const struct udevice_id mt7622_pericfg_compat[] = {
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{ }
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{ }
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};
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};
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static const struct udevice_id mt7622_pciesys_compat[] = {
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{ .compatible = "mediatek,mt7622-pciesys", },
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{ }
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};
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static const struct udevice_id mt7622_ethsys_compat[] = {
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static const struct udevice_id mt7622_ethsys_compat[] = {
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{ .compatible = "mediatek,mt7622-ethsys", },
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{ .compatible = "mediatek,mt7622-ethsys", },
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{ }
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{ }
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@ -660,6 +705,15 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
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.flags = DM_FLAG_PRE_RELOC,
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.flags = DM_FLAG_PRE_RELOC,
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};
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};
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U_BOOT_DRIVER(mtk_clk_pciesys) = {
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.name = "mt7622-clock-pciesys",
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.id = UCLASS_CLK,
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.of_match = mt7622_pciesys_compat,
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.probe = mt7622_pciesys_probe,
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.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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U_BOOT_DRIVER(mtk_clk_ethsys) = {
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U_BOOT_DRIVER(mtk_clk_ethsys) = {
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.name = "mt7622-clock-ethsys",
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.name = "mt7622-clock-ethsys",
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.id = UCLASS_CLK,
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.id = UCLASS_CLK,
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