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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 15:40:29 +09:00
ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This commit is contained in:
parent
dbe10b6274
commit
c37d59a170
@ -12,7 +12,7 @@
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/clk/at91.h>
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/{
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/{
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model = "Microchip SAM9X60 SoC";
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model = "Microchip SAM9X60 SoC";
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@ -33,6 +33,12 @@
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clock-frequency = <18500>;
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clock-frequency = <18500>;
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};
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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@ -53,8 +59,11 @@
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sdhci0: sdhci-host@80000000 {
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sdhci0: sdhci-host@80000000 {
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compatible = "microchip,sam9x60-sdhci";
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compatible = "microchip,sam9x60-sdhci";
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reg = <0x80000000 0x300>;
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reg = <0x80000000 0x300>;
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clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
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clock-names = "hclock", "multclk", "baseclk";
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
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assigned-clock-rates = <100000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
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bus-width = <4>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0>;
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pinctrl-0 = <&pinctrl_sdhci0>;
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@ -70,7 +79,7 @@
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compatible = "microchip,sam9x60-qspi";
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compatible = "microchip,sam9x60-qspi";
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reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
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reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&qspi_clk>, <&qspick>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
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clock-names = "pclk", "qspick";
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clock-names = "pclk", "qspick";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -80,7 +89,7 @@
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flx0: flexcom@f801c600 {
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flx0: flexcom@f801c600 {
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compatible = "atmel,sama5d2-flexcom";
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xf801c000 0x200>;
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reg = <0xf801c000 0x200>;
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clocks = <&flx0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xf801c000 0x800>;
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ranges = <0x0 0xf801c000 0x800>;
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@ -93,7 +102,7 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii>;
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pinctrl-0 = <&pinctrl_macb0_rmii>;
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clock-names = "hclk", "pclk";
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clock-names = "hclk", "pclk";
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clocks = <&macb0_clk>, <&macb0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -102,7 +111,7 @@
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reg = <0xfffff200 0x200>;
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reg = <0xfffff200 0x200>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dbgu>;
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pinctrl-0 = <&pinctrl_dbgu>;
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clocks = <&dbgu_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
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clock-names = "usart";
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clock-names = "usart";
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};
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};
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@ -159,7 +168,7 @@
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reg = <0xfffff400 0x200>;
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reg = <0xfffff400 0x200>;
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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clocks = <&pioA_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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};
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};
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pioB: gpio@fffff600 {
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pioB: gpio@fffff600 {
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@ -167,7 +176,7 @@
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reg = <0xfffff600 0x200>;
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reg = <0xfffff600 0x200>;
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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clocks = <&pioB_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
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};
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};
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pioD: gpio@fffffa00 {
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pioD: gpio@fffffa00 {
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@ -175,114 +184,22 @@
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reg = <0xfffffa00 0x200>;
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reg = <0xfffffa00 0x200>;
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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clocks = <&pioD_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
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};
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};
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pmc: pmc@fffffc00 {
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91sam9x5-pmc";
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compatible = "microchip,sam9x60-pmc";
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reg = <0xfffffc00 0x200>;
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reg = <0xfffffc00 0x200>;
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#address-cells = <1>;
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#clock-cells = <2>;
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#size-cells = <0>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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main: mainck {
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status = "okay";
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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};
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plla: pllack {
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compatible = "microchip,sam9x60-clk-pll";
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <8000000 24000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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clocks = <&clk32 0>, <&main>, <&plla>;
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atmel,clk-output-range = <140000000 200000000>;
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atmel,clk-divisors = <1 2 4 6>;
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};
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system: systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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qspick: qspick {
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#clock-cells = <0>;
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reg = <19>;
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clocks = <&mck>;
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};
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};
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periph: periphck {
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compatible = "microchip,sam9x60-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mck>;
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pioA_clk: pioA_clk {
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#clock-cells = <0>;
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reg = <2>;
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};
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pioB_clk: pioB_clk {
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#clock-cells = <0>;
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reg = <3>;
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};
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flx0_clk: flx0_clk {
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#clock-cells = <0>;
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reg = <5>;
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};
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pioD_clk: pioD_clk {
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#clock-cells = <0>;
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reg = <44>;
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};
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sdhci0_clk: sdhci0_clk {
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#clock-cells = <0>;
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reg = <12>;
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};
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dbgu_clk: dbgu_clk {
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#clock-cells = <0>;
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reg = <47>;
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};
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macb0_clk: macb0_clk {
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#clock-cells = <0>;
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reg = <24>;
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};
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qspi_clk: qspi_clk {
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#clock-cells = <0>;
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reg = <35>;
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};
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};
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generic: gck {
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compatible = "microchip,sam9x60-clk-generated";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk32 0>, <&clk32 1>, <&main>, <&mck>, <&plla>;
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sdhci0_gclk: sdhci0_gclk {
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#clock-cells = <0>;
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reg = <12>;
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};
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};
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};
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};
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pit: timer@fffffe40 {
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pit: timer@fffffe40 {
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compatible = "atmel,at91sam9260-pit";
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe40 0x10>;
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reg = <0xfffffe40 0x10>;
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clocks = <&mck>;
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clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
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};
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};
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clk32: sckc@fffffe50 {
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clk32: sckc@fffffe50 {
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@ -47,6 +47,14 @@
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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&main_rc {
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u-boot,dm-pre-reloc;
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};
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&main_xtal {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_dbgu {
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&pinctrl_dbgu {
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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@ -71,59 +79,3 @@
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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&main {
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u-boot,dm-pre-reloc;
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};
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&plla {
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u-boot,dm-pre-reloc;
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};
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&main_xtal {
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u-boot,dm-pre-reloc;
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};
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&mck {
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u-boot,dm-pre-reloc;
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};
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&system {
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u-boot,dm-pre-reloc;
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};
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&qspick {
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u-boot,dm-pre-reloc;
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};
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&periph {
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u-boot,dm-pre-reloc;
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};
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&pioA_clk {
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u-boot,dm-pre-reloc;
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};
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&pioB_clk {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_clk {
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u-boot,dm-pre-reloc;
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};
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&dbgu_clk {
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u-boot,dm-pre-reloc;
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};
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&qspi_clk {
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u-boot,dm-pre-reloc;
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};
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&generic {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_gclk {
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u-boot,dm-pre-reloc;
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};
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@ -67,7 +67,7 @@
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pinctrl-0 = <&pinctrl_flx0>;
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pinctrl-0 = <&pinctrl_flx0>;
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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clocks = <&flx0_clk>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
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status = "okay";
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status = "okay";
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eeprom@53 {
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eeprom@53 {
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