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Merge branch '2021-02-25-remove-platforms'

Browse Source 
- Remove various older platforms that are missing DM migrations and have
  had their removal ack'd.
This commit is contained in:
Tom Rini 2021-02-25 13:18:27 -05:00
commit c28d5d704d
57 changed files with 4 additions and 4225 deletions
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7
arch/arm/mach-imx/mx2/Kconfig
View File

@ -8,12 +8,6 @@ choice
prompt "MX25 board select"
optional
config TARGET_MX25PDK
bool "Support mx25pdk"
select BOARD_LATE_INIT
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
@ -24,7 +18,6 @@ endchoice
config SYS_SOC
default "mx25"
source "board/freescale/mx25pdk/Kconfig"
source "board/syteco/zmx25/Kconfig"
endif

10
arch/arm/mach-imx/mx5/Kconfig
View File

@ -44,10 +44,6 @@ config TARGET_MX51EVK
select BOARD_LATE_INIT
select MX51
config TARGET_MX53ARD
bool "Support mx53ard"
select MX53
config TARGET_MX53CX9020
bool "Support CX9020"
select BOARD_LATE_INIT
@ -72,10 +68,6 @@ config TARGET_MX53PPD
help
Enable support for the GE Healthcare PPD.
config TARGET_MX53SMD
bool "Support mx53smd"
select MX53
config TARGET_TS4800
bool "Support TS4800"
select MX51
@ -91,10 +83,8 @@ config SYS_SOC
source "board/beckhoff/mx53cx9020/Kconfig"
source "board/freescale/mx51evk/Kconfig"
source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/k+p/kp_imx53/Kconfig"

6
arch/arm/mach-imx/mx6/Kconfig
View File

@ -554,11 +554,6 @@ config TARGET_PCL063_ULL
config TARGET_SECOMX6
bool "secomx6 boards"
config TARGET_SKSIMX6
bool "sks-imx6"
depends on MX6QDL
select SUPPORT_SPL
config TARGET_SOMLABS_VISIONSOM_6ULL
bool "visionsom-6ull"
depends on MX6ULL
@ -737,7 +732,6 @@ source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"

22
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -64,10 +64,6 @@ config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
select ARCH_MPC8568
config TARGET_MPC8569MDS
bool "Support MPC8569MDS"
select ARCH_MPC8569
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@ -473,19 +469,6 @@ config ARCH_MPC8568
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select FSL_ELBC
imply CMD_NAND
config ARCH_MPC8572
bool
select FSL_LAW
@ -1102,7 +1085,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8555 || \
ARCH_MPC8560 || \
ARCH_MPC8568 || \
ARCH_MPC8569 || \
ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
@ -1335,8 +1317,7 @@ config SYS_FSL_NUM_LAWS
ARCH_P2020
default 10 if ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8568 || \
ARCH_MPC8569
ARCH_MPC8568
default 8 if ARCH_MPC8540 || \
ARCH_MPC8541 || \
ARCH_MPC8555 || \
@ -1433,7 +1414,6 @@ source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"

1
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -65,7 +65,6 @@ obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o

67
arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
View File

@ -1,67 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x0] = {PCIE1, NONE, NONE, NONE},
[0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
[0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
[0x3] = {SRIO1, SRIO2, NONE, NONE},
[0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
[0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x6] = {PCIE1, NONE, SRIO1, SRIO2},
[0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
[0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
if (!(serdes1_prtcl_map & (1 << NONE)))
fsl_serdes_init();
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
if (serdes1_prtcl_map & (1 << NONE))
return;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
/* Set the first bit to indicate serdes has been initialized */
serdes1_prtcl_map |= (1 << NONE);
}

2
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -630,7 +630,7 @@ int get_clocks(void)
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
#if defined(CONFIG_ARCH_P1010)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;

33
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -344,39 +344,6 @@ l2_disabled:
mtspr DBCR0,r0
#endif
#ifdef CONFIG_ARCH_MPC8569
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
* use address space which is more than 12bits, and it must be done in
* the 4K boot page. So we set this bit here.
*/
/* create a temp mapping TLB0[0] for LBCR */
create_tlb0_entry 0, \
0, BOOKE_PAGESZ_4K, \
CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
0, r6
/* Set LBCR register */
lis r4,CONFIG_SYS_LBCR_ADDR@h
ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
lis r5,CONFIG_SYS_LBC_LBCR@h
ori r5,r5,CONFIG_SYS_LBC_LBCR@l
stw r5,0(r4)
isync
/* invalidate this temp TLB */
lis r4,CONFIG_SYS_LBC_ADDR@h
ori r4,r4,CONFIG_SYS_LBC_ADDR@l
tlbivax 0,r4
isync
#endif /* CONFIG_ARCH_MPC8569 */
/*
* Search for the TLB that covers the code we're executing, and shrink it
* so that it covers only this 4K page. That will ensure that any other

10
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -38,16 +38,6 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2

9
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2204,15 +2204,8 @@ typedef struct ccsr_gur {
u32 gpiocr; /* GPIO control */
#endif
u8 res3[12];
#if defined(CONFIG_ARCH_MPC8569)
u32 plppar1; /* Platform port pin assignment 1 */
u32 plppar2; /* Platform port pin assignment 2 */
u32 plpdir1; /* Platform port pin direction 1 */
u32 plpdir2; /* Platform port pin direction 2 */
#else
u32 gpoutdr; /* General-purpose output data */
u8 res4[12];
#endif
u32 gpindr; /* General-purpose input data */
u8 res5[12];
u32 pmuxcr; /* Alt. function signal multiplex control */
@ -2478,7 +2471,7 @@ typedef struct ccsr_gur {
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
#if defined(CONFIG_ARCH_MPC8568)
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];

15
board/freescale/common/pq-mds-pib.c
View File

@ -63,20 +63,7 @@ int pib_init(void)
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
#if defined(CONFIG_TARGET_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
val8 = 0xdf;
i2c_write(0x20, 0x2, 1, &val8, 1);
val8 = 0xf7;
i2c_write(0x20, 0x3, 1, &val8, 1);
eieio();
printf("QOC3 ATM card on PMC0\n");
#elif defined(CONFIG_TARGET_MPC832XEMDS)
#if defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;

12
board/freescale/mpc8569mds/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_MPC8569MDS
config SYS_BOARD
default "mpc8569mds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8569MDS"
endif

7
board/freescale/mpc8569mds/MAINTAINERS
View File

@ -1,7 +0,0 @@
MPC8569MDS BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8569mds/
F: include/configs/MPC8569MDS.h
F: configs/MPC8569MDS_defconfig
F: configs/MPC8569MDS_ATM_defconfig

11
board/freescale/mpc8569mds/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2004-2009 Freescale Semiconductor.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mpc8569mds.o
obj-y += bcsr.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

77
board/freescale/mpc8569mds/README
View File

@ -1,77 +0,0 @@
Overview
--------
MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
Building U-Boot
-----------
make MPC8569MDS_config
make
Memory Map
----------
0x0000_0000 0x7fff_ffff DDR 2G
0xa000_0000 0xbfff_ffff PCIe MEM 512MB
0xe000_0000 0xe00f_ffff CCSRBAR 1M
0xe280_0000 0xe2ff_ffff PCIe I/O 8M
0xc000_0000 0xdfff_ffff SRIO 512MB
0xf000_0000 0xf3ff_ffff SDRAM 64MB
0xf800_0000 0xf800_7fff BCSR 32KB
0xf800_8000 0xf800_ffff PIB (CS4) 32KB
0xf801_0000 0xf801_7fff PIB (CS5) 32KB
0xfe00_0000 0xffff_ffff Flash 32MB
Flashing U-Boot Images
---------------
Use the following commands to program U-Boot image into flash:
=> tftp 1000000 u-boot.bin
=> protect off all
=> erase fff80000 ffffffff
=> cp.b 1000000 fff80000 80000
Setting the correct MAC addresses
-----------------------
The command - "mac", is introduced to set on-board system EEPROM in the format
defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
we first get the board. The commands are as follows:
=> mac i NXID /* Set NXID to this EEPROM */
=> mac e 01 /* Set Errata, this value is not defined by hardware
designer, we can set whatever we want */
=> mac n a0 /* Set Serial Number. This is not defined by hardware
designer, we can set whatever we want */
=> mac date 090512080000 /* Set the date in YYMMDDhhmmss format */
=> mac p 8 /* Set the number of mac ports, it should be 8 */
=> mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac
address, you can refer to the value on
the sticker of the rear side of the board
*/
.....
=> mac 7 xx:xx:xx:xx:xx:xx
=> mac read
=> mac save
After resetting the board, the ethxaddrs will be filled with the mac addresses
if such environment variables are blank(never been set before). If the ethxaddr
has been set but we want to update it, we can use the following commands:
=> setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */
=> save
=> reset
Programming the ucode to flash
---------------------------------
MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
IRAM so that the QE can work. The ucode binary can be downloaded from
http://opensource.freescale.com/firmware/, and it must be programmed to
the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
hangs at "Net:"
Please note the above two steps(setting mac addresses and programming ucode) are
very important to get the board booting up and working properly.

50
board/freescale/mpc8569mds/bcsr.c
View File

@ -1,50 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <flash.h>
#include <asm/io.h>
#include "bcsr.h"
void enable_8569mds_flash_write(void)
{
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
void disable_8569mds_flash_write(void)
{
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
void enable_8569mds_qe_uec(void)
{
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
/* Set UCC1-4 working at RMII mode */
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
#endif
}
void disable_8569mds_brd_eeprom_write_protect(void)
{
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
}

71
board/freescale/mpc8569mds/bcsr.h
View File

@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2009 Freescale Semiconductor, Inc.
*/
#ifndef __BCSR_H_
#define __BCSR_H_
#include <common.h>
/* BCSR Bit definitions*/
/****************************************/
/* BCSR defines */
/****************************************/
#define BCSR6_UPC1_EN 0x80
#define BCSR6_UPC1_POS_EN 0x40
#define BCSR6_UPC1_ADDR_EN 0x20
#define BCSR6_UPC1_DEV2 0x10
#define BCSR6_SD_CARD_1BIT 0x08
#define BCSR6_SD_CARD_4BITS 0x04
#define BCSR6_TDM2G_EN 0x02
#define BCSR6_UCC7_RMII_EN 0x01
#define BCSR7_UCC1_GETH_EN 0x80
#define BCSR7_UCC1_RGMII_EN 0x40
#define BCSR7_UCC1_RTBI_EN 0x20
#define BCSR7_GETHRST_MRVL 0x04
#define BCSR7_BRD_WRT_PROTECT 0x02
#define BCSR8_UCC2_GETH_EN 0x80
#define BCSR8_UCC2_RGMII_EN 0x40
#define BCSR8_UCC2_RTBI_EN 0x20
#define BCSR8_UEM_MARVEL_RESET 0x02
#define BCSR9_UCC3_GETH_EN 0x80
#define BCSR9_UCC3_RGMII_EN 0x40
#define BCSR9_UCC3_RTBI_EN 0x20
#define BCSR9_UCC3_RMII_EN 0x10
#define BCSR9_UCC3_UEM_MICREL 0x01
#define BCSR10_UCC4_GETH_EN 0x80
#define BCSR10_UCC4_RGMII_EN 0x40
#define BCSR10_UCC4_RTBI_EN 0x20
#define BCSR11_LED0 0x40
#define BCSR11_LED1 0x20
#define BCSR11_LED2 0x10
#define BCSR12_UCC6_RMII_EN 0x20
#define BCSR12_UCC8_RMII_EN 0x20
#define BCSR15_SMII6_DIS 0x08
#define BCSR15_SMII8_DIS 0x04
#define BCSR15_QEUART_EN 0x01
#define BCSR16_UPC1_DEV2 0x02
#define BCSR17_nUSBEN 0x80
#define BCSR17_nUSBLOWSPD 0x40
#define BCSR17_USBVCC 0x20
#define BCSR17_USBMODE 0x10
#define BCSR17_FLASH_nWP 0x01
/*BCSR Utils functions*/
void enable_8569mds_flash_write(void);
void disable_8569mds_flash_write(void);
void enable_8569mds_qe_uec(void);
void disable_8569mds_brd_eeprom_write_protect(void);
#endif /* __BCSR_H_ */

63
board/freescale/mpc8569mds/ddr.c
View File

@ -1,63 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts->clk_adjust = 4;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts->cpo_override = 0xff;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts->write_data_delay = 2;
/*
* Enable half drive strength
*/
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xa;
popts->wrlvl_start = 0x4;
/* Rtt and Rtt_W override */
popts->rtt_override = 1;
popts->rtt_override_value = DDR3_RTT_60_OHM;
popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}

40
board/freescale/mpc8569mds/law.c
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@ -1,40 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
*0) 0x0000_0000 0x7fff_ffff DDR 2G
*1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
*-) 0xe000_0000 0xe00f_ffff CCSR 1M
*2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
*3) 0xc000_0000 0xdfff_ffff SRIO 512MB
*4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
*4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
*4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
*4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
*4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
*
*Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*
*/
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
#endif
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

590
board/freescale/mpc8569mds/mpc8569mds.c
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@ -1,590 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2010 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*/
#include <common.h>
#include <console.h>
#include <flash.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <phy.h>
#include "bcsr.h"
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDC */
{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
/* QE_MUX_MDIO */
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
/* UCC_1_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
/* UCC_2_RGMII */
{2, 16, 2, 0, 3}, /* CLK17 */
{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
/* UCC_3_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
/* UCC_4_RGMII */
{2, 16, 2, 0, 3}, /* CLK17 */
{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
/* UCC_1_RMII */
{2, 15, 2, 0, 1}, /* CLK16 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
/* UCC_2_RMII */
{2, 15, 2, 0, 1}, /* CLK16 */
{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
/* UCC_3_RMII */
{2, 15, 2, 0, 1}, /* CLK16 */
{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
/* UCC_4_RMII */
{2, 15, 2, 0, 1}, /* CLK16 */
{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
#endif
/* UART1 is muxed with QE PortF bit [9-12].*/
{5, 12, 2, 0, 3}, /* UART1_SIN */
{5, 9, 1, 0, 3}, /* UART1_SOUT */
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
/* QE UART */
{0, 19, 1, 0, 2}, /* QEUART_TX */
{1, 17, 2, 0, 3}, /* QEUART_RX */
{0, 25, 1, 0, 1}, /* QEUART_RTS */
{1, 23, 2, 0, 1}, /* QEUART_CTS */
/* QE USB */
{5, 3, 1, 0, 1}, /* USB_OE */
{5, 4, 1, 0, 2}, /* USB_TP */
{5, 5, 1, 0, 2}, /* USB_TN */
{5, 6, 2, 0, 2}, /* USB_RP */
{5, 7, 2, 0, 1}, /* USB_RX */
{5, 8, 2, 0, 1}, /* USB_RN */
{2, 4, 2, 0, 2}, /* CLK5 */
/* SPI Flash, M25P40 */
{4, 27, 3, 0, 1}, /* SPI_MOSI */
{4, 28, 3, 0, 1}, /* SPI_MISO */
{4, 29, 3, 0, 1}, /* SPI_CLK */
{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
void local_bus_init(void);
int board_early_init_f (void)
{
/*
* Initialize local bus.
*/
local_bus_init ();
enable_8569mds_flash_write();
#ifdef CONFIG_QE
enable_8569mds_qe_uec();
#endif
#if CONFIG_SYS_I2C2_OFFSET
/* Enable I2C2 signals instead of SD signals */
volatile struct ccsr_gur *gur;
gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
gur->plppar1 |= PLPPAR1_I2C2_VAL;
gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
gur->plpdir1 |= PLPDIR1_I2C2_VAL;
disable_8569mds_brd_eeprom_write_protect();
#endif
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
const u8 flash_esel = 0;
/*
* Remap Boot flash to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, /* ts, esel */
BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
return 0;
}
int checkboard (void)
{
printf ("Board: 8569 MDS\n");
return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
#if defined (CONFIG_DDR_ECC)
out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
#endif
udelay(500);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
debug("DDR - 1st controller: memory initializing\n");
/*
* Poll until memory is initialized.
* 512 Meg at 400 might hit this 200 times or so.
*/
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
udelay(1000);
}
debug("DDR: memory initialized\n\n");
udelay(500);
#endif
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16)
out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
else if (clkdiv == 8)
out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
else if (clkdiv == 4)
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}
static void fdt_board_disable_serial(void *blob, struct bd_info *bd,
const char *alias)
{
const char *status = "disabled";
int off;
int err;
off = fdt_path_offset(blob, alias);
if (off < 0) {
printf("WARNING: could not find %s alias: %s.\n", alias,
fdt_strerror(off));
return;
}
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
if (err) {
printf("WARNING: could not set status for serial0: %s.\n",
fdt_strerror(err));
return;
}
}
/*
* Because of an erratum in prototype boards it is impossible to use eSDHC
* without disabling UART0 (which makes it quite easy to 'brick' the board
* by simply issung 'setenv hwconfig esdhc', and not able to interact with
* U-Boot anylonger).
*
* So, but default we assume that the board is a prototype, which is a most
* safe assumption. There is no way to determine board revision from a
* register, so we use hwconfig.
*/
static int prototype_board(void)
{
if (hwconfig_subarg("board", "rev", NULL))
return hwconfig_subarg_cmp("board", "rev", "prototype");
return 1;
}
static int esdhc_disables_uart0(void)
{
return prototype_board() ||
hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
}
static void fdt_board_fixup_qe_uart(void *blob, struct bd_info *bd)
{
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
const char *devtype = "serial";
const char *compat = "ucc_uart";
const char *clk = "brg9";
u32 portnum = 0;
int off = -1;
if (!hwconfig("qe_uart"))
return;
if (hwconfig("esdhc") && esdhc_disables_uart0()) {
printf("QE UART: won't enable with esdhc.\n");
return;
}
fdt_board_disable_serial(blob, bd, "serial1");
while (1) {
const u32 *idx;
int len;
off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
if (off < 0) {
printf("WARNING: unable to fixup device tree for "
"QE UART\n");
return;
}
idx = fdt_getprop(blob, off, "cell-index", &len);
if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
continue;
break;
}
fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
setbits_8(&bcsr[15], BCSR15_QEUART_EN);
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(struct bd_info *bd)
{
struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
u8 bcsr6 = BCSR6_SD_CARD_1BIT;
if (!hwconfig("esdhc"))
return 0;
printf("Enabling eSDHC...\n"
" For eSDHC to function, I2C2 ");
if (esdhc_disables_uart0()) {
printf("and UART0 should be disabled.\n");
printf(" Redirecting stderr, stdout and stdin to UART1...\n");
console_assign(stderr, "eserial1");
console_assign(stdout, "eserial1");
console_assign(stdin, "eserial1");
printf("Switched to UART1 (initial log has been printed to "
"UART0).\n");
clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
PLPPAR1_ESDHC_4BITS_VAL);
clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
PLPDIR1_ESDHC_4BITS_VAL);
bcsr6 |= BCSR6_SD_CARD_4BITS;
} else {
printf("should be disabled.\n");
}
/* Assign I2C2 signals to eSDHC. */
clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
PLPPAR1_ESDHC_VAL);
clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
PLPDIR1_ESDHC_VAL);
/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
setbits_8(&bcsr[6], bcsr6);
return fsl_esdhc_mmc_init(bd);
}
static void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd)
{
const char *status = "disabled";
int off = -1;
if (!hwconfig("esdhc"))
return;
if (esdhc_disables_uart0())
fdt_board_disable_serial(blob, bd, "serial0");
while (1) {
const u32 *idx;
int len;
off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
if (off < 0)
break;
idx = fdt_getprop(blob, off, "cell-index", &len);
if (!idx || len != sizeof(*idx))
continue;
if (*idx == 1) {
fdt_setprop(blob, off, "status", status,
strlen(status) + 1);
break;
}
}
if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
if (off < 0) {
printf("WARNING: could not find esdhc node\n");
return;
}
fdt_delprop(blob, off, "sdhci,1-bit-only");
}
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) {}
#endif
static void fdt_board_fixup_qe_usb(void *blob, struct bd_info *bd)
{
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
else
setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
clrbits_8(&bcsr[17], BCSR17_USBVCC);
clrbits_8(&bcsr[17], BCSR17_USBMODE);
do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
"peripheral", sizeof("peripheral"), 1);
} else {
setbits_8(&bcsr[17], BCSR17_USBVCC);
setbits_8(&bcsr[17], BCSR17_USBMODE);
}
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
#if defined(CONFIG_PQ_MDS_PIB)
pib_init();
#endif
fsl_pcie_init_board(0);
}
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
int nodeoff, off, err;
unsigned int val;
const u32 *ph;
const u32 *index;
/* fixup device tree for supporting rmii mode */
nodeoff = -1;
while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
"ucc_geth")) >= 0) {
err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
"clk16");
if (err < 0) {
printf("WARNING: could not set tx-clock-name %s.\n",
fdt_strerror(err));
break;
}
err = fdt_fixup_phy_connection(blob, nodeoff,
PHY_INTERFACE_MODE_RMII);
if (err < 0) {
printf("WARNING: could not set phy-connection-type "
"%s.\n", fdt_strerror(err));
break;
}
index = fdt_getprop(blob, nodeoff, "cell-index", 0);
if (index == NULL) {
printf("WARNING: could not get cell-index of ucc\n");
break;
}
ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
if (ph == NULL) {
printf("WARNING: could not get phy-handle of ucc\n");
break;
}
off = fdt_node_offset_by_phandle(blob, *ph);
if (off < 0) {
printf("WARNING: could not get phy node %s.\n",
fdt_strerror(err));
break;
}
val = 0x7 + *index; /* RMII phy address starts from 0x8 */
err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
if (err < 0) {
printf("WARNING: could not set reg for phy-handle "
"%s.\n", fdt_strerror(err));
break;
}
}
#endif
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
return 0;
}
#endif

94
board/freescale/mpc8569mds/tlb.c
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@ -1,94 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 Initializations */
/*
* TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
* 0xfc000000 32MB NAND FLASH (CS3)
* 0xfe000000 32MB NOR FLASH (CS0)
*/
#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
* 0xa00000000 256M PCIe MEM (lower half)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLBe 3: 256M Non-cacheable, guarded
* 0xb00000000 256M PCIe MEM (higher half)
*/
SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
(CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
/*
* TLBe 4: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe280_0000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

15
board/freescale/mx25pdk/Kconfig
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@ -1,15 +0,0 @@
if TARGET_MX25PDK
config SYS_BOARD
default "mx25pdk"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx25"
config SYS_CONFIG_NAME
default "mx25pdk"
endif

6
board/freescale/mx25pdk/MAINTAINERS
View File

@ -1,6 +0,0 @@
MX25PDK BOARD
M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx25pdk/
F: include/configs/mx25pdk.h
F: configs/mx25pdk_defconfig

7
board/freescale/mx25pdk/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
obj-y := mx25pdk.o

64
board/freescale/mx25pdk/imximage.cfg
View File

@ -1,64 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* EIM config-CS5 init -- CPLD */
DATA 4 0xB8002050 0x0000D843
DATA 4 0xB8002054 0x22252521
DATA 4 0xB8002058 0x22220A00
/* DDR2 init */
DATA 4 0xB8001004 0x0076E83A
DATA 4 0xB8001010 0x00000204
DATA 4 0xB8001000 0x92210000
DATA 4 0x80000f00 0x12344321
DATA 4 0xB8001000 0xB2210000
DATA 1 0x82000000 0xda
DATA 1 0x83000000 0xda
DATA 1 0x81000400 0xda
DATA 1 0x80000333 0xda
DATA 4 0xB8001000 0x92210000
DATA 1 0x80000400 0x12345678
DATA 4 0xB8001000 0xA2210000
DATA 4 0x80000000 0x87654321
DATA 4 0x80000000 0x87654321
DATA 4 0xB8001000 0xB2210000
DATA 1 0x80000233 0xda
DATA 1 0x81000780 0xda
DATA 1 0x81000400 0xda
DATA 4 0xB8001000 0x82216080
DATA 4 0x43FAC454 0x00001000
DATA 4 0x53F80008 0x20034000
/* Enable the clocks */
DATA 4 0x53f8000c 0x1fffffff
DATA 4 0x53f80010 0xffffffff
DATA 4 0x53f80014 0xfdfff

199
board/freescale/mx25pdk/mx25pdk.c
View File

@ -1,199 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011 Freescale Semiconductor, Inc.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx25.h>
#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc34704.h>
#define FEC_RESET_B IMX_GPIO_NR(4, 8)
#define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
#define CARD_DETECT IMX_GPIO_NR(2, 1)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{IMX_MMC_SDHC1_BASE},
};
#endif
/*
* FIXME: need to revisit this
* The original code enabled PUE and 100-k pull-down without PKE, so the right
* value here is likely:
* 0 for no pull
* or:
* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
*/
#define FEC_OUT_PAD_CTRL 0
#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
PAD_CTL_ODE)
static void mx25pdk_fec_init(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
};
static const iomux_v3_cfg_t i2c_pads[] = {
NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* Assert RESET and ENABLE low */
gpio_direction_output(FEC_RESET_B, 0);
gpio_direction_output(FEC_ENABLE_B, 0);
udelay(10);
/* Deassert RESET and ENABLE */
gpio_set_value(FEC_RESET_B, 1);
gpio_set_value(FEC_ENABLE_B, 1);
/* Setup I2C pins so that PMIC can turn on PHY supply */
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
/*
* Set up input pins with hysteresis and 100-k pull-ups
*/
#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
/*
* FIXME: need to revisit this
* The original code enabled PUE and 100-k pull-down without PKE, so the right
* value here is likely:
* 0 for no pull
* or:
* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
*/
#define UART1_OUT_PAD_CTRL 0
static void mx25pdk_uart1_init(void)
{
static const iomux_v3_cfg_t uart1_pads[] = {
NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
int board_early_init_f(void)
{
mx25pdk_uart1_init();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int board_late_init(void)
{
struct pmic *p;
int ret;
mx25pdk_fec_init();
ret = pmic_init(I2C_0);
if (ret)
return ret;
p = pmic_get("FSL_PMIC");
if (!p)
return -ENODEV;
/* Turn on Ethernet PHY and LCD supplies */
pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
return 0;
}
#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
/* Set up the Card Detect pin. */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
gpio_direction_input(CARD_DETECT);
return !gpio_get_value(CARD_DETECT);
}
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sdhc1_pads[] = {
NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
/*
* Set the eSDHC1 PER clock to the maximum frequency lower than or equal
* to 50 MHz that can be obtained, which requires to use UPLL as the
* clock source. This actually gives 48 MHz.
*/
imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int checkboard(void)
{
puts("Board: MX25PDK\n");
return 0;
}
/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
void lowlevel_init(void) {}

15
board/freescale/mx53ard/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_MX53ARD
config SYS_BOARD
default "mx53ard"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "mx53ard"
endif

6
board/freescale/mx53ard/MAINTAINERS
View File

@ -1,6 +0,0 @@
MX53ARD BOARD
M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53ard/
F: include/configs/mx53ard.h
F: configs/mx53ard_defconfig

7
board/freescale/mx53ard/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
obj-y := mx53ard.o

82
board/freescale/mx53ard/imximage_dd3.cfg
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@ -1,82 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
DATA 4 0x53fa8564 0x00300040
DATA 4 0x53fa8568 0x00300040
DATA 4 0x53fa8570 0x00300000
DATA 4 0x53fa8574 0x00300000
DATA 4 0x53fa8578 0x00300000
DATA 4 0x53fa857c 0x00300040
DATA 4 0x53fa8580 0x00300040
DATA 4 0x53fa8584 0x00300000
DATA 4 0x53fa8588 0x00300000
DATA 4 0x53fa8590 0x00300040
DATA 4 0x53fa8594 0x00300000
DATA 4 0x53fa86f0 0x00300000
DATA 4 0x53fa86f4 0x00000000
DATA 4 0x53fa86fc 0x00000000
DATA 4 0x53fa8714 0x00000000
DATA 4 0x53fa8718 0x00300000
DATA 4 0x53fa871c 0x00300000
DATA 4 0x53fa8720 0x00300000
DATA 4 0x53fa8724 0x04000000
DATA 4 0x53fa8728 0x00300000
DATA 4 0x53fa872c 0x00300000
DATA 4 0x63fd9088 0x35343535
DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000

319
board/freescale/mx53ard/mx53ard.c
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@ -1,319 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#define ETHERNET_INT IMX_GPIO_NR(2, 31)
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
u32 size1, size2;
size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
#ifdef CONFIG_NAND_MXC
static void setup_iomux_nand(void)
{
static const iomux_v3_cfg_t nand_pads[] = {
NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
PAD_CTL_PUS_100K_UP),
NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
};
u32 i, reg;
reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
reg &= ~M4IF_GENP_WEIM_MM_MASK;
__raw_writel(reg, M4IF_BASE_ADDR + 0xc);
for (i = 0x4; i < 0x94; i += 0x18) {
reg = __raw_readl(WEIM_BASE_ADDR + i);
reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
__raw_writel(reg, WEIM_BASE_ADDR + i);
}
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
#else
static void setup_iomux_nand(void)
{
}
#endif
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_input(IMX_GPIO_NR(1, 1));
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
gpio_direction_input(IMX_GPIO_NR(1, 4));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
else
ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
return ret;
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
};
static const iomux_v3_cfg_t sd2_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
};
u32 index;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(sd2_pads,
ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
#endif
static void weim_smc911x_iomux(void)
{
static const iomux_v3_cfg_t weim_smc911x_pads[] = {
/* Data bus */
NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
/* Address lines */
NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
/* other EIM signals for ethernet */
MX53_PAD_EIM_OE__EMI_WEIM_OE,
MX53_PAD_EIM_RW__EMI_WEIM_RW,
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
};
/* ETHERNET_INT as GPIO2_31 */
imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
gpio_direction_input(ETHERNET_INT);
/* WEIM bus */
imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
ARRAY_SIZE(weim_smc911x_pads));
}
static void weim_cs1_settings(void)
{
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
writel(0x0, &weim_regs->cs1gcr2);
writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
writel(0x0, &weim_regs->cs1wcr2);
writel(0x0, &weim_regs->wcr);
set_chipselect_size(CS0_64M_CS1_64M);
}
int board_early_init_f(void)
{
setup_iomux_nand();
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int board_eth_init(struct bd_info *bis)
{
int rc = -ENODEV;
weim_smc911x_iomux();
weim_cs1_settings();
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
int checkboard(void)
{
puts("Board: MX53ARD\n");
return 0;
}

15
board/freescale/mx53smd/Kconfig
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@ -1,15 +0,0 @@
if TARGET_MX53SMD
config SYS_BOARD
default "mx53smd"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "mx53smd"
endif

6
board/freescale/mx53smd/MAINTAINERS
View File

@ -1,6 +0,0 @@
MX53SMD BOARD
M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53smd/
F: include/configs/mx53smd.h
F: configs/mx53smd_defconfig

7
board/freescale/mx53smd/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
obj-y := mx53smd.o

82
board/freescale/mx53smd/imximage.cfg
View File

@ -1,82 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
DATA 4 0x53fa8564 0x00300040
DATA 4 0x53fa8568 0x00300040
DATA 4 0x53fa8570 0x00300000
DATA 4 0x53fa8574 0x00300000
DATA 4 0x53fa8578 0x00300000
DATA 4 0x53fa857c 0x00300040
DATA 4 0x53fa8580 0x00300040
DATA 4 0x53fa8584 0x00300000
DATA 4 0x53fa8588 0x00300000
DATA 4 0x53fa8590 0x00300040
DATA 4 0x53fa8594 0x00300000
DATA 4 0x53fa86f0 0x00300000
DATA 4 0x53fa86f4 0x00000000
DATA 4 0x53fa86fc 0x00000000
DATA 4 0x53fa8714 0x00000000
DATA 4 0x53fa8718 0x00300000
DATA 4 0x53fa871c 0x00300000
DATA 4 0x53fa8720 0x00300000
DATA 4 0x53fa8724 0x04000000
DATA 4 0x53fa8728 0x00300000
DATA 4 0x53fa872c 0x00300000
DATA 4 0x63fd9088 0x35343535
DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000

159
board/freescale/mx53smd/mx53smd.c
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@ -1,159 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
u32 size1, size2;
size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
PAD_CTL_HYS | PAD_CTL_PKE),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
return !gpio_get_value(IMX_GPIO_NR(3, 13));
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
MX53_PAD_EIM_DA13__GPIO3_13,
};
u32 index;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(1)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int checkboard(void)
{
puts("Board: MX53SMD\n");
return 0;
}

11
board/sks-kinkel/sksimx6/Kconfig
View File

@ -1,11 +0,0 @@
if TARGET_SKSIMX6
config SYS_BOARD
default "sksimx6"
config SYS_VENDOR
default "sks-kinkel"
config SYS_CONFIG_NAME
default "sksimx6"
endif

6
board/sks-kinkel/sksimx6/MAINTAINERS
View File

@ -1,6 +0,0 @@
SKS-Kinkel sksimx6
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/sks-kinkel/sksimx6/
F: include/configs/sksimx6.h
F: configs/sksimx6_defconfig

2
board/sks-kinkel/sksimx6/Makefile
View File

@ -1,2 +0,0 @@
#
obj-y := sksimx6.o

431
board/sks-kinkel/sksimx6/sksimx6.c
View File

@ -1,431 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <netdev.h>
#include <miiphy.h>
#include <micrel.h>
#include <common.h>
#include <malloc.h>
#include <fuse.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const gpios_pads[] = {
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
};
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
iomux_v3_cfg_t const enet_pads1[] = {
/* pin 35 - 1 (PHY_AD2) on reset */
IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 32 - 1 - (MODE0) all */
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 31 - 1 - (MODE1) all */
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 28 - 1 - (MODE2) all */
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 27 - 1 - (MODE3) all */
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* pin 42 PHY nRST */
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
#define ENET_NRST IMX_GPIO_NR(1, 25)
void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
}
int board_eth_init(struct bd_info *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
bus = fec_get_miibus(base, -1);
if (!bus)
return -EINVAL;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
ret = -EINVAL;
goto free_bus;
}
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret)
goto free_phydev;
return 0;
free_phydev:
free(phydev);
free_bus:
free(bus);
return ret;
}
int board_early_init_f(void)
{
SETUP_IOMUX_PADS(uart1_pads);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* Take in reset the ATMega processor */
SETUP_IOMUX_PADS(gpios_pads);
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC2_BASE_ADDR, 0},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
ret = 1;
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
int ret;
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
usdhc_cfg[0].max_bus_width = 4;
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
if (ret) {
printf("Warning: failed to initialize mmc dev \n");
return ret;
}
return 0;
}
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6SDL_DRIVE_STRENGTH 0x230
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
/* quad = 1066, duallite = 800 */
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
.p0_mpwldectrl0 = 0x0043004E,
.p0_mpwldectrl1 = 0x003D003F,
.p1_mpwldectrl0 = 0x00230021,
.p1_mpwldectrl1 = 0x0028003E,
.p0_mpdgctrl0 = 0x42580250,
.p0_mpdgctrl1 = 0x0238023C,
.p1_mpdgctrl0 = 0x422C0238,
.p1_mpdgctrl1 = 0x02180228,
.p0_mprddlctl = 0x44464A46,
.p1_mprddlctl = 0x44464A42,
.p0_mpwrdlctl = 0x36343236,
.p1_mpwrdlctl = 0x36343230,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_qdl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* set the default clock gate to save power */
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void spl_dram_init(void)
{
if (is_cpu_type(MXC_CPU_MX6DL)) {
mt41k128m16jt_125.mem_speed = 800;
mem_qdl.rtt_nom = 1;
mem_qdl.rtt_wr = 1;
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
} else {
printf("Wrong CPU for this board\n");
return;
}
udelay(100);
#ifdef CONFIG_MX6_DDRCAL
/* Perform DDR DRAM calibration */
mmdc_do_write_level_calibration(&mem_qdl);
mmdc_do_dqs_calibration(&mem_qdl);
#endif
}
static void check_bootcfg(void)
{
u32 val5, val6;
fuse_sense(0, 5, &val5);
fuse_sense(0, 6, &val6);
/* Check if boot from MMC */
if (val6 & 0x10) {
puts("BT_FUSE_SEL already fused, will do nothing\n");
return;
}
fuse_prog(0, 5, 0x00000840);
/* BT_FUSE_SEL */
fuse_prog(0, 6, 0x00000010);
do_reset(NULL, 0, 0, NULL);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Set fuses for new boards and reboot if not set */
check_bootcfg();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

40
configs/MPC8569MDS_ATM_defconfig
View File

@ -1,40 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8569MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="ATM"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_E1000=y
CONFIG_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

39
configs/MPC8569MDS_defconfig
View File

@ -1,39 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF80000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8569MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_E1000=y
CONFIG_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

62
configs/P2041RDB_SECURE_BOOT_defconfig
View File

@ -1,62 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y

53
configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
View File

@ -1,53 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

53
configs/P3041DS_SRIO_PCIE_BOOT_defconfig
View File

@ -1,53 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

51
configs/P4080DS_SRIO_PCIE_BOOT_defconfig
View File

@ -1,51 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

66
configs/T2080RDB_SECURE_BOOT_defconfig
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@ -1,66 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

56
configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
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@ -1,56 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_ENV_SIZE=0x2000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_CMD_IRQ is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
CONFIG_PHY_REALTEK=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

31
configs/mx25pdk_defconfig
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@ -1,31 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX25=y
CONFIG_SYS_TEXT_BASE=0x81200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_MX25PDK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
CONFIG_OF_LIBFDT=y

31
configs/mx53ard_defconfig
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@ -1,31 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_MX53ARD=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXC=y
CONFIG_MII=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0xF4000000
CONFIG_MXC_UART=y
CONFIG_OF_LIBFDT=y

25
configs/mx53smd_defconfig
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@ -1,25 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_MX53SMD=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_OF_LIBFDT=y

53
configs/sksimx6_defconfig
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@ -1,53 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6QDL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_SKSIMX6=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x64000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y

489
include/configs/MPC8569MDS.h
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@ -1,489 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*/
/*
* mpc8569mds board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
/* Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
#ifdef CONFIG_ATM
#define CONFIG_PQ_MDS_PIB
#define CONFIG_PQ_MDS_PIB_ATM
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_HWCONFIG
/*
* Config the L2 Cache as L2 SRAM
*/
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (512 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
#define CONFIG_SYS_DDR_TIMING_3 0x00020000
#define CONFIG_SYS_DDR_TIMING_0 0x00330004
#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
#define CONFIG_SYS_DDR_TIMING_4 0x00220001
#define CONFIG_SYS_DDR_TIMING_5 0x03402400
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
#define CONFIG_SYS_DDR_CDR_1 0x80040000
#define CONFIG_SYS_DDR_CDR_2 0x00000000
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
#define CONFIG_SYS_DDR_CONTROL2 0x24400000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00010000
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BCSR_BASE 0xf8000000
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
/*Chip select 0 - Flash*/
#define CONFIG_FLASH_BR_PRELIM 0xfe000801
#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
/*Chip select 1 - BCSR*/
#define CONFIG_SYS_BR1_PRELIM 0xf8000801
#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
/*Chip select 4 - PIB*/
#define CONFIG_SYS_BR4_PRELIM 0xf8008801
#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
/*Chip select 5 - PIB*/
#define CONFIG_SYS_BR5_PRELIM 0xf8010801
#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Chip select 3 - NAND */
#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xFC000000
#else
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#endif
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START \
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define PLPPAR1_I2C_BIT_MASK 0x0000000F
#define PLPPAR1_I2C2_VAL 0x00000000
#define PLPPAR1_ESDHC_VAL 0x0000000A
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
#define PLPDIR1_ESDHC_VAL 0x00000006
#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
/*
* General PCI
* Memory Addresses are mapped 1-1. I/O is mapped from 0
*/
#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
*/
#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_UEC_ETH1 /* GETH1 */
#define CONFIG_HAS_ETH0
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH1 */
#define CONFIG_UEC_ETH2 /* GETH2 */
#define CONFIG_HAS_ETH1
#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH2 */
#define CONFIG_UEC_ETH3 /* GETH3 */
#define CONFIG_HAS_ETH2
#ifdef CONFIG_UEC_ETH3
#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 2
#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH3 */
#define CONFIG_UEC_ETH4 /* GETH4 */
#define CONFIG_HAS_ETH3
#ifdef CONFIG_UEC_ETH4
#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 3
#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
#endif /* CONFIG_UEC_ETH4 */
#undef CONFIG_UEC_ETH6 /* GETH6 */
#define CONFIG_HAS_ETH5
#ifdef CONFIG_UEC_ETH6
#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC6_PHY_ADDR 4
#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH6 */
#undef CONFIG_UEC_ETH8 /* GETH8 */
#define CONFIG_HAS_ETH7
#ifdef CONFIG_UEC_ETH8
#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC8_PHY_ADDR 6
#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
#endif /* CONFIG_UEC_ETH8 */
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/*
* Environment
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_HOSTNAME "mpc8569mds"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=600000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs\0" \
"ramargs=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs\0" \
#define CONFIG_NFSBOOTCOMMAND \
"run nfsargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"run ramargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

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include/configs/mx25pdk.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011 Freescale Semiconductor, Inc.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
/* Physical Memory Map */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Memory Test */
/* Serial Info */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* No NOR flash present */
/* U-Boot general configuration */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
/* ESDHC driver */
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* PMIC Configs */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
/* RTC */
#define CONFIG_RTC_IMXDI
/* Fuse API support */
#define CONFIG_FSL_IIM
/* Ethernet Configs */
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x82000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if mmc dev ${mmcdev}; then " \
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
"setexpr fw_sz ${filesize} / 0x200; " \
"setexpr fw_sz ${fw_sz} + 1; " \
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
/* Miscellaneous configurable options */
#endif /* __CONFIG_H */

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include/configs/mx53ard.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX53ARD Freescale board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_MXC_UART_BASE UART1_BASE
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* Eth Configs */
#define CONFIG_HAS_ETH1
/* Command definition */
#define CONFIG_ETHPRIME "smc911x"
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=zImage\0" \
"console=ttymxc0\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x78000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if mmc dev ${mmcdev}; then " \
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
"setexpr fw_sz ${filesize} / 0x200; " \
"setexpr fw_sz ${fw_sz} + 1; " \
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${uimage}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
#define MX53ARD_CS1RCR2 RBEN(2)
#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
#endif /* __CONFIG_H */

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include/configs/mx53smd.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX53SMD Freescale board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_MXC_UART_BASE UART1_BASE
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* Command definition */
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm\0" \
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#endif /* __CONFIG_H */

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include/configs/sksimx6.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*/
#ifndef __SKSIMX6_CONFIG_H
#define __SKSIMX6_CONFIG_H
#include "mx6_common.h"
#include "imx6_spl.h"
/* Serial */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CONFIG_PHY_MICREL_KSZ9021
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_SPEED 100000
/* Filesystem support */
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* Environment organization */
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off\0" \
"addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
"bootcmd=run mmcboot\0" \
"bootfile=uImage\0" \
"bootimage=uImage\0" \
"console=ttymxc0\0" \
"fdt_addr_r=0x18000000\0" \
"fdt_file=imx6dl-sks-cts.dtb\0" \
"fdt_high=0xffffffff\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"miscargs=quiet\0" \
"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
"mmcboot=if run mmcload;then " \
"run mmcargs addcons addmisc;" \
"bootm;fi\0" \
"mmcload=mmc rescan;" \
"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p1\0" \
"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
"tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
"run nfsargs addip addcons addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"nfsargs=setenv bootargs root=/dev/nfs " \
"nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
#endif